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09/24/2013
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13675442
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11/13/2012
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05/16/2013
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PROTECTIVE TREATMENT FOR POROUS MATERIALS
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11/17/2015
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13676063
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11/13/2012
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05/15/2014
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FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN
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03/25/2014
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13676174
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11/14/2012
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03/21/2013
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CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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01/19/2016
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13676412
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11/14/2012
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05/15/2014
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SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE
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05/26/2015
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13676483
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11/14/2012
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05/15/2014
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Title:
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REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
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11/25/2014
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13676575
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11/14/2012
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05/15/2014
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Title:
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REPLACEMENT METAL GATE STRUCTURE FOR CMOS DEVICE
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09/09/2014
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13676817
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11/14/2012
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05/15/2014
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Title:
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COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
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02/11/2014
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13677373
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11/15/2012
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Title:
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ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
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07/19/2016
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13677542
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11/15/2012
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04/17/2014
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Title:
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System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
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06/16/2015
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13677610
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11/15/2012
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05/15/2014
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ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES
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09/23/2014
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13677647
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11/15/2012
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05/15/2014
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Title:
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CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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01/07/2014
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13677863
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11/15/2012
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Title:
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SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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12/08/2015
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13677908
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11/15/2012
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05/01/2014
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Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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06/02/2015
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13677954
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11/15/2012
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05/15/2014
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Title:
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DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
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08/04/2015
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13677997
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11/15/2012
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05/15/2014
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Title:
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SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
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02/24/2015
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13678011
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11/15/2012
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05/15/2014
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METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SEMICONDUCTIVE RESISTOR STRUCTURES IN A FINFET ARCHITECTURE
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02/24/2015
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13678054
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11/15/2012
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Pub Dt:
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05/15/2014
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF
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12/02/2014
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13678111
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11/15/2012
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04/17/2014
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EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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09/16/2014
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13678124
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11/15/2012
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05/15/2014
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Title:
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SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS
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02/18/2014
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13679222
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11/16/2012
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Title:
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STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
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06/09/2015
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13679284
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11/16/2012
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05/22/2014
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LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS
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02/04/2014
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13679357
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11/16/2012
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03/21/2013
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SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
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09/02/2014
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13681761
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11/20/2012
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05/22/2014
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DENSE FINFET SRAM
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08/26/2014
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13682056
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11/20/2012
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05/22/2014
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POLYGON RECOVERY FOR VLSI MASK CORRECTION
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05/06/2014
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13682769
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11/21/2012
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05/22/2014
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FINFET FORMATION USING DOUBLE PATTERNING MEMORIZATION
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12/17/2013
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13682771
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11/21/2012
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USE OF POLARIZATION AND COMPOSITE ILLUMINATION SOURCE FOR ADVANCED OPTICAL LITHOGRAPHY
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04/26/2016
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13683508
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11/21/2012
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05/22/2014
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POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
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03/24/2015
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13684818
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11/26/2012
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05/29/2014
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FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS
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02/03/2015
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13684842
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11/26/2012
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05/29/2014
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DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
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06/10/2014
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13684869
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11/26/2012
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05/29/2014
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REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
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06/16/2015
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13685733
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11/27/2012
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05/29/2014
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Finfet Semiconductor Device Having Increased Gate Height Control
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04/15/2014
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13685735
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11/27/2012
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LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
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12/16/2014
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13685779
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11/27/2012
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05/29/2014
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SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY
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07/08/2014
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13686203
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11/27/2012
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05/29/2014
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TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS
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10/14/2014
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13686263
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11/27/2012
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04/04/2013
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METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
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12/23/2014
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13686377
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11/27/2012
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05/29/2014
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PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
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01/28/2014
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13686422
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11/27/2012
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04/11/2013
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ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE
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06/09/2015
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13686969
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11/28/2012
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05/29/2014
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DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION
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06/03/2014
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13687218
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11/28/2012
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04/11/2013
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Ball Grid Array with Improved Single-Ended and Differential Signal Performance
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01/07/2014
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13687240
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11/28/2012
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05/16/2013
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METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
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03/10/2015
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13687314
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11/28/2012
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05/15/2014
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CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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08/12/2014
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13687355
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11/28/2012
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05/29/2014
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METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
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09/09/2014
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13687877
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11/28/2012
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04/04/2013
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RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
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11/18/2014
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13688259
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11/29/2012
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05/29/2014
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SEMICONDUCTOR DEVICE HAVING A METAL GATE RECESS
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03/04/2014
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13688595
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11/29/2012
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INTEGRATED CIRCUIT HAVING LOCAL MAXIMUM OPERATING VOLTAGE
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06/16/2015
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13689044
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11/29/2012
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05/29/2014
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ISOLATING FAILING LATCHES USING A LOGIC BUILT-IN SELF-TEST
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06/03/2014
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13689052
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11/29/2012
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05/08/2014
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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09/06/2016
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13689090
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11/29/2012
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05/29/2014
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LIGHT ACTIVATED TEST CONNECTIONS
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02/10/2015
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13689437
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11/29/2012
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05/29/2014
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STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS
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08/26/2014
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13689838
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11/30/2012
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06/05/2014
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HETEROJUNCTION BIPOLAR TRANSISTOR
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04/08/2014
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13689839
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11/30/2012
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE DEVICE CONTACTS
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07/15/2014
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13689844
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11/30/2012
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06/05/2014
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING LOW RESISTANCE METAL GATE STRUCTURES
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01/06/2015
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13689924
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11/30/2012
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06/05/2014
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UNIFORM FINFET GATE HEIGHT
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09/09/2014
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13689948
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11/30/2012
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06/05/2014
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UNIFORM FINFET GATE HEIGHT
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02/17/2015
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13689979
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11/30/2012
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06/05/2014
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NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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02/03/2015
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13690209
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11/30/2012
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06/05/2014
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TECHNIQUES FOR ROUTING SIGNAL WIRES IN AN INTEGRATED CIRCUIT DESIGN
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02/03/2015
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13690240
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11/30/2012
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06/05/2014
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Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
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05/12/2015
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13690867
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11/30/2012
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06/05/2014
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SEMICONDUCTOR DEVICE WITH REPLACEMENT METAL GATE AND METHOD FOR SELECTIVE DEPOSITION OF MATERIAL FOR REPLACEMENT METAL GATE
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08/18/2015
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13691129
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11/30/2012
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04/11/2013
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MULTI COMPONENT DIELECTRIC LAYER
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08/26/2014
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13692069
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Filing Dt:
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12/03/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
Title:
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INDUCING CHANNEL STRESS IN SEMICONDUCTOR-ON-INSULATOR DEVICES BY BASE SUBSTRATE OXIDATION
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13692603
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Filing Dt:
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12/03/2012
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Publication #:
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Pub Dt:
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05/22/2014
| | | | |
Title:
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DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
04/15/2014
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Application #:
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13693094
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Filing Dt:
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12/04/2012
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Title:
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SEMICONDUCTOR DEVICE HAVING A GATE FORMED ON A UNIFORM SURFACE AND METHOD FOR FORMING THE SAME
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Patent #:
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Issue Dt:
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05/27/2014
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Application #:
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13693285
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Filing Dt:
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12/04/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
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NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
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Patent #:
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Issue Dt:
|
02/17/2015
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Application #:
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13693627
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Filing Dt:
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12/04/2012
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Publication #:
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Pub Dt:
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06/05/2014
| | | | |
Title:
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ASYMMETRIC TEMPLATES FOR FORMING NON-PERIODIC PATTERNS USING DIRECTES SELF-ASSEMBLY MATERIALS
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Patent #:
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Issue Dt:
|
01/13/2015
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Application #:
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13693749
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Filing Dt:
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12/04/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
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FAR BACK END OF THE LINE STACK ENCAPSULATION
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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13705261
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Filing Dt:
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12/05/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
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COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE
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Patent #:
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Issue Dt:
|
06/09/2015
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Application #:
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13705300
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Filing Dt:
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12/05/2012
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Publication #:
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Pub Dt:
|
05/30/2013
| | | | |
Title:
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DYNAMICALLY LIMITING ENERGY CONSUMED BY COOLING APPARATUS
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Patent #:
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|
Issue Dt:
|
03/18/2014
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Application #:
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13705477
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Filing Dt:
|
12/05/2012
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Title:
|
Finfet eDram Strap Connection Structure
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Patent #:
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Issue Dt:
|
07/28/2015
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Application #:
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13705717
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Filing Dt:
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12/05/2012
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Publication #:
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Pub Dt:
|
06/05/2014
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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Patent #:
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|
Issue Dt:
|
12/17/2013
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Application #:
|
13705920
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Filing Dt:
|
12/05/2012
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Title:
|
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
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|
Patent #:
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|
Issue Dt:
|
02/04/2014
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Application #:
|
13707058
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Filing Dt:
|
12/06/2012
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Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
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Application #:
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13708126
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Filing Dt:
|
12/07/2012
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Publication #:
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Pub Dt:
|
06/12/2014
| | | | |
Title:
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Preventing FIN Erosion and Limiting Epi Overburden in FinFET Structures by Composite Hardmask
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Patent #:
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|
Issue Dt:
|
11/12/2013
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Application #:
|
13708499
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Filing Dt:
|
12/07/2012
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Publication #:
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Pub Dt:
|
04/18/2013
| | | | |
Title:
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SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
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|
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Patent #:
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|
Issue Dt:
|
08/26/2014
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Application #:
|
13708531
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Filing Dt:
|
12/07/2012
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Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BULK FINFET WITH SUPER STEEP RETROGRADE WELL
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|
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Patent #:
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|
Issue Dt:
|
04/14/2015
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Application #:
|
13708988
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Filing Dt:
|
12/08/2012
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Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME
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|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13709095
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
EPITAXIAL GROWN EXTREMELY SHALLOW EXTENSION REGION
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|
|
Patent #:
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|
Issue Dt:
|
05/13/2014
|
Application #:
|
13709397
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
METHOD OF FORMING SELF-ASSEMBLED PATTERNS USING BLOCK COPOLYMERS, AND ARTICLES THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13709541
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DOUBLE SIDEWALL IMAGE TRANSFER PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
05/20/2014
|
Application #:
|
13709662
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Filing Dt:
|
12/10/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13709748
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
VECTORIZATION OF BIT-LEVEL NETLISTS
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|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13710498
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE RESOLUTION ENHANCEMENT BY ETCHING MULTIPLE SIDES OF A MASK
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|
|
Patent #:
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|
Issue Dt:
|
11/11/2014
|
Application #:
|
13710551
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Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
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|
|
Patent #:
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|
Issue Dt:
|
11/25/2014
|
Application #:
|
13710561
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Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
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|
|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
|
13710575
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
CONTACT LANDING PADS FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13710616
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONTROLLED APPLICATION OF OERSTED FIELD TO MAGNETIC MEMORY STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13710710
|
Filing Dt:
|
12/11/2012
|
Publication #:
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|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Automated Fault and Recovery System
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|
|
Patent #:
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|
Issue Dt:
|
03/17/2015
|
Application #:
|
13710953
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13711813
|
Filing Dt:
|
12/12/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER
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|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13712234
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
HIGH DENSITY SERIAL CAPACITOR DEVICE AND METHODS OF MAKING SUCH A CAPACITOR DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/17/2015
|
Application #:
|
13712567
|
Filing Dt:
|
12/12/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
EFFICIENT USE OF MIRRORED STORAGE CLOUDS
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|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13713759
|
Filing Dt:
|
12/13/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
QUANTUM CIRCUIT WITHIN WAVEGUIDE-BEYOND-CUTOFF
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|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13714049
|
Filing Dt:
|
12/13/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SILICIDE CONTACTS ON NON-PLANAR STRUCTURES
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|
|
Patent #:
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|
Issue Dt:
|
06/09/2015
|
Application #:
|
13714404
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Filing Dt:
|
12/14/2012
|
Publication #:
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Pub Dt:
|
06/19/2014
| | | | |
Title:
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ELECTROSTATIC DISCHARGE RESISTANT DIODES
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|
|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
|
13716686
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Filing Dt:
|
12/17/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE BY PERFORMING AN EPITAXIAL GROWTH PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
11/14/2017
|
Application #:
|
13716693
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Filing Dt:
|
12/17/2012
|
Publication #:
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|
Pub Dt:
|
05/02/2013
| | | | |
Title:
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METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION
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|
Patent #:
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|
Issue Dt:
|
04/21/2015
|
Application #:
|
13716731
|
Filing Dt:
|
12/17/2012
|
Publication #:
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|
Pub Dt:
|
05/02/2013
| | | | |
Title:
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ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
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|
|
Patent #:
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|
Issue Dt:
|
03/29/2016
|
Application #:
|
13716758
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
METHODS OF FORMING FINS FOR A FINFET DEVICE WHEREIN THE FINS HAVE A HIGH GERMANIUM CONTENT
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|
|
Patent #:
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|
Issue Dt:
|
02/03/2015
|
Application #:
|
13717079
|
Filing Dt:
|
12/17/2012
|
Publication #:
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|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
THERMAL SPIN TORQURE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
11/04/2014
|
Application #:
|
13717235
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE
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|
|
Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
|
13717701
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA
|
|