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Total properties:
17
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10413052
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Filing Dt:
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04/14/2003
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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EFFECTIVE PROXIMITY EFFECT CORRECTION METHODOLOGY
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10672620
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Filing Dt:
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09/26/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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CONTACT PRINTING USING A MAGNIFIED MASK IMAGE
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10694474
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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MASK DATA PREPARATION
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Patent #:
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Issue Dt:
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04/21/2009
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Application #:
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11060927
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Filing Dt:
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02/18/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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SYSTEM FOR DESIGNING INTEGRATED CIRCUITS WITH ENHANCED MANUFACTURABILITY
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Patent #:
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Issue Dt:
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02/03/2009
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Application #:
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11091067
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Filing Dt:
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03/28/2005
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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SYSTEM FOR SIMPLIFYING LAYOUT PROCESSING
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11091305
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Filing Dt:
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03/28/2005
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Publication #:
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Pub Dt:
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09/29/2005
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Title:
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SYSTEM FOR INTEGRATED CIRCUIT LAYOUT PARTITION AND EXTRACTION FOR INDEPENDENT LAYOUT PROCESSING
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Patent #:
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Issue Dt:
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12/01/2009
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Application #:
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11221528
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Filing Dt:
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09/08/2005
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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MODEL-BASED PATTERN CHARACTERIZATION TO GENERATE RULES FOR RULE-MODEL-BASED HYBRID OPTICAL PROXIMITY CORRECTION
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Patent #:
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Issue Dt:
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03/15/2011
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Application #:
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11221533
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Filing Dt:
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09/08/2005
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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CREATING AND APPLYING VARIABLE BIAS RULES IN RULE-BASED OPTICAL PROXIMITY CORRECTION FOR REDUCED COMPLEXITY
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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11273685
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Filing Dt:
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11/14/2005
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
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Title:
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INTEGRATED CIRCUIT DESIGN USING MODIFIED CELLS
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11350515
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Filing Dt:
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02/09/2006
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Publication #:
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Pub Dt:
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06/15/2006
| | | | |
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Title:
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EFFECTIVE PROXIMITY EFFECT CORRECTION METHODOLOGY
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|
|
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Patent #:
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|
Issue Dt:
|
11/03/2009
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Application #:
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11442110
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Filing Dt:
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05/26/2006
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Publication #:
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Pub Dt:
|
09/28/2006
| | | | |
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Title:
|
MASK DATA PREPARATION
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|
|
|
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Patent #:
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|
Issue Dt:
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04/03/2012
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Application #:
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12306340
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Filing Dt:
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07/02/2009
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Publication #:
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Pub Dt:
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06/10/2010
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Title:
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METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT PHYSICAL LAYOUT
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|
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Patent #:
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|
Issue Dt:
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07/15/2014
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Application #:
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12322489
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Filing Dt:
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02/02/2009
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Publication #:
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Pub Dt:
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09/24/2009
| | | | |
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Title:
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System for simplifying layout processing
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|
|
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Patent #:
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|
Issue Dt:
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10/02/2012
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Application #:
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12592674
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Filing Dt:
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12/01/2009
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|
Publication #:
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Pub Dt:
|
06/17/2010
| | | | |
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Title:
|
MODEL-BASED PATTERN CHARACTERIZATION TO GENERATE RULES FOR RULE-MODEL-BASED HYBRID OPTICAL PROXIMITY CORRECTION
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|
|
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12593392
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Filing Dt:
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04/01/2010
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Publication #:
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Pub Dt:
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07/22/2010
| | | | |
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Title:
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SEMICONDUCTOR LAYOUT SCANNING METHOD AND SYSTEM
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|
|
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Patent #:
|
|
Issue Dt:
|
09/11/2012
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Application #:
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12666988
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Filing Dt:
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12/28/2009
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Publication #:
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Pub Dt:
|
08/05/2010
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Title:
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SEMICONDUCTOR LAYOUT MODIFICATION METHOD BASED ON DESIGN RULE AND USER CONSTRAINTS
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|
|
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Patent #:
|
|
Issue Dt:
|
09/11/2012
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Application #:
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13044931
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Filing Dt:
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03/10/2011
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Title:
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CLEANING TOOL DEVICE FOR VERTICAL BLINDS
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