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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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12199690
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Filing Dt:
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08/27/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12206310
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Filing Dt:
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09/08/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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PROCESS OF FABRICATING A WORKPIECE USING A TEST MASK
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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12228691
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Filing Dt:
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08/15/2008
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Publication #:
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Pub Dt:
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02/18/2010
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Title:
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METHOD OF MEASURING FLASH MEMORY CELL CURRENT
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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12231369
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Filing Dt:
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09/02/2008
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12240627
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Filing Dt:
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09/29/2008
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Publication #:
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Pub Dt:
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04/01/2010
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Title:
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METHOD FOR USING POROUS LOW DIELECTRIC FILMS IN SEMICONDUCTOR MANUFACTURING
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Patent #:
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Issue Dt:
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05/26/2015
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Application #:
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12249261
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Filing Dt:
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10/10/2008
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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SYSTEM AND METHOD FOR MULTI-LAYER GLOBAL BITLINES
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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12253207
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Filing Dt:
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10/16/2008
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Publication #:
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Pub Dt:
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04/22/2010
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Title:
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SYSTEMS AND METHODS FOR DOWNLOADING CODE AND DATA INTO A SECURE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12266512
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Filing Dt:
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11/06/2008
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Publication #:
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Pub Dt:
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05/06/2010
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Title:
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FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
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Patent #:
|
|
Issue Dt:
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10/23/2012
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Application #:
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12267017
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Filing Dt:
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11/07/2008
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Publication #:
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Pub Dt:
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05/13/2010
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Title:
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ERROR CORRECTION FOR FLASH MEMORY
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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12273289
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Filing Dt:
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11/18/2008
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Publication #:
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Pub Dt:
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05/20/2010
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Title:
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ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT
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Patent #:
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Issue Dt:
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01/21/2014
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Application #:
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12284002
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Filing Dt:
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09/17/2008
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Publication #:
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Pub Dt:
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03/18/2010
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Title:
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ELECTRICALLY PROGRAMMABLE AND ERASABLE MEMORY DEVICE AND METHOD OF FABRICATION THEREOF
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|
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Patent #:
|
|
Issue Dt:
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03/29/2016
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Application #:
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12286149
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Filing Dt:
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09/29/2008
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Publication #:
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|
Pub Dt:
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04/01/2010
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Title:
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Ruthenium interconnect with high aspect ratio and method of fabrication thereof
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Patent #:
|
|
Issue Dt:
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05/27/2014
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Application #:
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12313134
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Filing Dt:
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11/17/2008
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Publication #:
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Pub Dt:
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05/20/2010
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Title:
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HIGH ULTRAVIOLET LIGHT ABSORBANCE SILICON OXYNITRIDE FILM FOR IMPROVED FLASH MEMORY DEVICE PERFORMANCE
|
|
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Patent #:
|
|
Issue Dt:
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03/25/2014
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Application #:
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12322105
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Filing Dt:
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01/28/2009
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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Self-aligned double patterning for memory and other microelectronic devices
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Patent #:
|
|
Issue Dt:
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03/05/2013
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Application #:
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12326388
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Filing Dt:
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12/02/2008
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Publication #:
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|
Pub Dt:
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06/03/2010
| | | | |
Title:
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MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
09/25/2012
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Application #:
|
12337134
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Filing Dt:
|
12/17/2008
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Publication #:
|
|
Pub Dt:
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03/04/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
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Application #:
|
12337963
|
Filing Dt:
|
12/18/2008
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Publication #:
|
|
Pub Dt:
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06/24/2010
| | | | |
Title:
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RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
|
|
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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12340295
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Filing Dt:
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12/19/2008
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Publication #:
|
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Pub Dt:
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06/24/2010
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Title:
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RADIATION-DETECTING STRUCTURES
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Patent #:
|
|
Issue Dt:
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02/18/2014
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Application #:
|
12342016
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Filing Dt:
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12/22/2008
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Publication #:
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|
Pub Dt:
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06/24/2010
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Title:
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HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
|
|
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Patent #:
|
|
Issue Dt:
|
03/17/2015
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Application #:
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12366519
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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FRACTURED ERASE SYSTEM AND METHOD
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|
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Patent #:
|
|
Issue Dt:
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04/08/2014
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Application #:
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12368023
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Filing Dt:
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02/09/2009
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
08/28/2012
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Application #:
|
12368835
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Filing Dt:
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02/10/2009
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Publication #:
|
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Pub Dt:
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08/12/2010
| | | | |
Title:
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SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA
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|
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Patent #:
|
|
Issue Dt:
|
10/06/2015
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Application #:
|
12390550
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Filing Dt:
|
02/23/2009
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Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12432441
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
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11/04/2010
| | | | |
Title:
|
SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12433159
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
DIRECT POINTER ACCESS AND XIP REDIRECTOR FOR EMULATION OF MEMORY-MAPPED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12468615
|
Filing Dt:
|
05/19/2009
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12473037
|
Filing Dt:
|
05/27/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
IMPROVEMENT IN CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12473081
|
Filing Dt:
|
05/27/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12489226
|
Filing Dt:
|
06/22/2009
|
Publication #:
|
|
Pub Dt:
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12/23/2010
| | | | |
Title:
|
A NAND FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
12556199
|
Filing Dt:
|
09/09/2009
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
Title:
|
VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12575137
|
Filing Dt:
|
10/07/2009
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12644457
|
Filing Dt:
|
12/22/2009
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
Title:
|
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12646279
|
Filing Dt:
|
12/23/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
12648059
|
Filing Dt:
|
12/28/2009
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
LINE-EDGE ROUGHNESS IMPROVEMENT FOR SMALL PITCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12683732
|
Filing Dt:
|
01/07/2010
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12690590
|
Filing Dt:
|
01/20/2010
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
12690617
|
Filing Dt:
|
01/20/2010
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
FIELD UPGRADABLE FIRMWARE FOR ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12691633
|
Filing Dt:
|
01/21/2010
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
HIGH SPEED MEMORY HAVING A PROGRAMMABLE READ PREAMBLE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
12696409
|
Filing Dt:
|
01/29/2010
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
12697707
|
Filing Dt:
|
02/01/2010
|
Publication #:
|
|
Pub Dt:
|
06/03/2010
| | | | |
Title:
|
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12699635
|
Filing Dt:
|
02/03/2010
|
Publication #:
|
|
Pub Dt:
|
06/03/2010
| | | | |
Title:
|
SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
12701391
|
Filing Dt:
|
02/05/2010
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
12703586
|
Filing Dt:
|
02/10/2010
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
PLANAR CELL ONO CUT USING IN-SITU POLYMER DEPOSITION AND ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
12706710
|
Filing Dt:
|
02/16/2010
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12720547
|
Filing Dt:
|
03/09/2010
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12722014
|
Filing Dt:
|
03/11/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
NAND ARRAY SOURCE/DRAIN DOPING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12722083
|
Filing Dt:
|
03/11/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12723582
|
Filing Dt:
|
03/12/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12723589
|
Filing Dt:
|
03/12/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12723590
|
Filing Dt:
|
03/12/2010
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
HOME AND BUILDING AUTOMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12729905
|
Filing Dt:
|
03/23/2010
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12770805
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12783351
|
Filing Dt:
|
05/19/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
PARTIAL LOCAL SELF BOOSTING FOR NAND
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12790578
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
STRAPPING CONTACT FOR CHARGE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
12792129
|
Filing Dt:
|
06/02/2010
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
Title:
|
ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12818866
|
Filing Dt:
|
06/18/2010
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
METHOD AND STRUCTURE OF MINIMIZING MOLD BLEEDING ON A SUBSTRATE SURFACE OF A SEMICONDUCTOR PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12824352
|
Filing Dt:
|
06/28/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
HIGH READ SPEED MEMORY WITH GATE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12826366
|
Filing Dt:
|
06/29/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12840063
|
Filing Dt:
|
07/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE BY CONSIDERING THE EXTINCTION COEFFICIENT DURING ETCHING OF AN INTERLAYER INSULATING FILM
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12842409
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Filing Dt:
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07/23/2010
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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BITLINE VOLTAGE DRIVER
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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12844392
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Filing Dt:
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07/27/2010
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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12852970
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Filing Dt:
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08/09/2010
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Publication #:
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Pub Dt:
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04/07/2011
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Title:
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REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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01/22/2013
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Application #:
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12853856
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Filing Dt:
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08/10/2010
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Publication #:
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Pub Dt:
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02/16/2012
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Title:
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STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12877661
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Filing Dt:
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09/08/2010
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Publication #:
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Pub Dt:
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03/10/2011
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Title:
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STRUCTURE, METHOD AND SYSTEM FOR ASSESSING BONDING OF ELECTRODES IN FCB PACKAGING
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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12879992
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Filing Dt:
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09/10/2010
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Publication #:
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Pub Dt:
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03/15/2012
| | | | |
Title:
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Apparatus and method for read preamble disable
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12880018
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Filing Dt:
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09/10/2010
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Publication #:
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Pub Dt:
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03/15/2012
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Title:
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APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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12900370
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Filing Dt:
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10/07/2010
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Publication #:
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Pub Dt:
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02/03/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
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Patent #:
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Issue Dt:
|
09/11/2012
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Application #:
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12901990
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Filing Dt:
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10/11/2010
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Publication #:
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Pub Dt:
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07/28/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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12910331
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Filing Dt:
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10/22/2010
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Publication #:
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Pub Dt:
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02/17/2011
| | | | |
Title:
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SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12912602
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Filing Dt:
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10/26/2010
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Publication #:
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Pub Dt:
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06/30/2011
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Title:
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FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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05/14/2013
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Application #:
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12943679
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Filing Dt:
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11/10/2010
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Publication #:
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Pub Dt:
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03/10/2011
| | | | |
Title:
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MEMORY DEVICE PERIPHERAL INTERCONNECTS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12960411
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Filing Dt:
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12/03/2010
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Publication #:
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Pub Dt:
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06/07/2012
| | | | |
Title:
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METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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12960437
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Filing Dt:
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12/03/2010
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Publication #:
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Pub Dt:
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06/07/2012
| | | | |
Title:
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DUAL SPACER FORMATION IN FLASH MEMORY
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Patent #:
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Issue Dt:
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01/19/2016
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Application #:
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12961379
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Filing Dt:
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12/06/2010
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Publication #:
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Pub Dt:
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04/28/2011
| | | | |
Title:
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WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
|
|
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Patent #:
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Issue Dt:
|
07/05/2016
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Application #:
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12962479
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Filing Dt:
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12/07/2010
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Publication #:
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Pub Dt:
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03/31/2011
| | | | |
Title:
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FLIP-CHIP PACKAGE COVERED WITH TAPE
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|
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Patent #:
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Issue Dt:
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10/20/2015
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Application #:
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12964523
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Filing Dt:
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12/09/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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HIGH PERFORMANCE LOW PROFILE QFN/LGA
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|
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Patent #:
|
|
Issue Dt:
|
09/25/2012
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Application #:
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12964594
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Filing Dt:
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12/09/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL
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|
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Patent #:
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Issue Dt:
|
10/09/2012
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Application #:
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12970675
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Filing Dt:
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12/16/2010
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Publication #:
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Pub Dt:
|
06/02/2011
| | | | |
Title:
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LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
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Patent #:
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Issue Dt:
|
11/20/2012
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Application #:
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12970687
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Filing Dt:
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12/16/2010
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Publication #:
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Pub Dt:
|
04/14/2011
| | | | |
Title:
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LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
|
|
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Patent #:
|
|
Issue Dt:
|
06/11/2013
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Application #:
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12971818
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Filing Dt:
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12/17/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING
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|
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Patent #:
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Issue Dt:
|
09/11/2012
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Application #:
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12973631
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS
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|
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Patent #:
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Issue Dt:
|
08/09/2016
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Application #:
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12973756
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING
|
|
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Patent #:
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NONE
|
Issue Dt:
|
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Application #:
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12979654
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Filing Dt:
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12/28/2010
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Publication #:
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Pub Dt:
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06/28/2012
| | | | |
Title:
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SYSTEM, METHOD AND APPARATUS FOR REDUCING PLASMA NOISE ON POWER PATH OF ELECTROSTATIC CHUCK
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
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Application #:
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12982006
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Filing Dt:
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12/30/2010
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Publication #:
|
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Pub Dt:
|
07/05/2012
| | | | |
Title:
|
MEMORY WITH EXTENDED CHARGE TRAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
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Application #:
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13015072
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Filing Dt:
|
01/27/2011
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Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
|
|
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Patent #:
|
|
Issue Dt:
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11/05/2013
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Application #:
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13020692
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Filing Dt:
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02/03/2011
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Publication #:
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Pub Dt:
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06/02/2011
| | | | |
Title:
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SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
|
|
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Patent #:
|
|
Issue Dt:
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07/31/2012
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Application #:
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13025979
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Filing Dt:
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02/11/2011
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Publication #:
|
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Pub Dt:
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06/09/2011
| | | | |
Title:
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PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
|
|
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Patent #:
|
|
Issue Dt:
|
02/05/2013
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Application #:
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13026075
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Filing Dt:
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02/11/2011
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Publication #:
|
|
Pub Dt:
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06/16/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
|
|
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Patent #:
|
|
Issue Dt:
|
12/02/2014
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Application #:
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13044313
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Filing Dt:
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03/09/2011
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Publication #:
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Pub Dt:
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06/30/2011
| | | | |
Title:
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METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
|
|
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13052865
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Filing Dt:
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03/21/2011
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13069269
|
Filing Dt:
|
03/22/2011
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Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
13069710
|
Filing Dt:
|
03/23/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2012
|
Application #:
|
13094744
|
Filing Dt:
|
04/26/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
13107724
|
Filing Dt:
|
05/13/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
13123698
|
Filing Dt:
|
04/11/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
13153558
|
Filing Dt:
|
06/06/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13154616
|
Filing Dt:
|
06/07/2011
|
Publication #:
|
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Pub Dt:
|
09/29/2011
| | | | |
Title:
|
DETERMINING A LOGIC STATE BASED ON CURRENTS RECEIVED BY A SENSE AMPLIFER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2012
|
Application #:
|
13156122
|
Filing Dt:
|
06/08/2011
|
Publication #:
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|
Pub Dt:
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09/29/2011
| | | | |
Title:
|
METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
13156763
|
Filing Dt:
|
06/09/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13156766
|
Filing Dt:
|
06/09/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
|
|