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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09187172
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Filing Dt:
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11/06/1998
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Title:
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RECESSED CHANNEL STRUCTURE FOR MANUFACTURING SHALLOW SOURCE/DRAIN EXTENSIONS
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09187232
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Filing Dt:
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11/06/1998
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Title:
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METHOD FOR FORMING A DUAL DAMASCENE TRENCH AND UNDERLYING BORDERLESS VIA IN LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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04/24/2001
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09187252
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING PUNCH-THROUGH SUPPRESSION
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09187391
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Filing Dt:
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11/06/1998
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Title:
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ANTIREFLECTIVE SILICONOXYNITRIDE HARDMASK LAYER USED DURING ETCHING PROCESSES IN INTEGRATED CIRCUIT FABRICATION
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Issue Dt:
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05/29/2001
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09187427
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Filing Dt:
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11/06/1998
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Title:
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FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM AT SILICIDATION
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09187428
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Filing Dt:
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11/06/1998
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN IMPROVED GATE ELECTRODE PROFILE
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09187430
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FORMING A DUAL DAMASCENE TRENCH AND BORDERLESS VIA STRUCTURE
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09187498
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF MANUFACTURING A TRANSISTOR WITH LOCAL INSULATOR STRUCTURE
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09187520
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Filing Dt:
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11/06/1998
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Title:
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LOW RESISTANCE METAL CONTACT TECHNOLOGY
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09187521
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Filing Dt:
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11/06/1998
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Title:
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FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED FILM INTO AND THROUGH A SILICIDE DURING SILICIDATION
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09187524
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF CONTROLLING EFFECTIVE CHANNEL LENGTH OF SEMICONDUCTOR DEVICE BY NON-DOPING IMPLANTATION AT ELEVATED ENERGIES
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09187542
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Filing Dt:
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11/06/1998
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Title:
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FERROELECTRIC-ENHANCED TANTALUM PENTOXIDE FOR DIELECTRIC MATERIAL APPLICATIONS IN CMOS DEVICES
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09187630
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Filing Dt:
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11/06/1998
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Title:
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DUAL AMORPHIZATION IMPLANT PROCESS FOR ULTRA-SHALLOW DRAIN AND SOURCE EXTENSIONS
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Issue Dt:
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11/16/1999
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09187635
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Filing Dt:
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11/06/1998
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Title:
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DAMASCENE PROCESS FOR FORMING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS AND POCKET IN ULSI MOSFET
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Patent #:
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Issue Dt:
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08/28/2001
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09187861
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Filing Dt:
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11/06/1998
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Title:
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INTEGRATED CIRCUIT HAVING ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09187890
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Filing Dt:
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11/06/1998
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Title:
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09187894
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Filing Dt:
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11/06/1998
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Title:
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ASYMMETRICAL IGFET DEVICES WITH SPACERS FORMED BY HDP TECHNIQUES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09188085
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Filing Dt:
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11/06/1998
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Title:
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MASK FOR ASYMMETRICAL TRANSISTOR FORMATION WITH PAIRED TRANSISTORS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09189228
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Filing Dt:
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11/11/1998
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Title:
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SYSTEM FOR CONTROLLING REFLECTION RETICLE TEMPERATURE IN MICROLITHOGRAPHY
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Issue Dt:
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03/21/2000
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09189278
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Filing Dt:
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11/10/1998
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Title:
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OXIDE FORMATION TECHNIQUE USING THIN FILM SILICON DEPOSITION
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Issue Dt:
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08/10/1999
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09189279
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Filing Dt:
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11/10/1998
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Title:
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NITROGENATED GATE STRUCTURE FOR IMPROVED TRANSISTOR PERFORMANCE AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09190768
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Filing Dt:
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11/12/1998
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Title:
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METHOD FOR REMOVING COPPER RESIDUE FROM SURFACES OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09190986
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Filing Dt:
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11/12/1998
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Title:
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MANUFACTURING REFERENCE DATABASE
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09191138
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Filing Dt:
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11/13/1998
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Title:
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SUBTRENCH CONDUCTOR FORMED WITH LARGE TILT ANGLE IMPLANT
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09193262
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Filing Dt:
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11/18/1998
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED ACTIVE, LIGHTLY-DOPED DRAIN, AND HALO REGIONS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09193619
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Filing Dt:
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11/17/1998
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Title:
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METHOD OF MAKING SEMICONDUCTOR DEVICE HAVING SACRIFICIAL SALICIDATION LAYER
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09195092
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Filing Dt:
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11/18/1998
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Title:
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SILICON NITRIDE ETCH BATH SYSTEM
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Patent #:
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Issue Dt:
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11/16/1999
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09195181
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Filing Dt:
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11/17/1998
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Title:
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FLEXIBLE RESOURCE ACCESS IN A MICROPROCESSOR
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Issue Dt:
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11/14/2000
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Application #:
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09195195
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND SYSTEM FOR GENERATING PRODUCT PERFORMANCE HISTORY
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06/04/2002
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09195300
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Filing Dt:
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11/18/1998
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Title:
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SEMICONDUCTOR WAFER REVIEW SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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09195336
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Filing Dt:
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11/18/1998
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Title:
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SEMICONDUCTOR DEVICE WITH VERTICAL HALO REGION AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
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07/11/2000
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09195592
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Filing Dt:
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11/18/1998
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Title:
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TRENCH ISOLATION STRUCTURE PARTIALLY BOUND BETWEEN A PAIR OF LOW K DIELECTRIC STRUCTURES
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09196439
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Filing Dt:
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11/20/1998
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Title:
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METHOD OF FORMING ASYMMETRICALLY DOPED SOURCE/DRAIN REGIONS
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Issue Dt:
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03/12/2002
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09197020
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Filing Dt:
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11/20/1998
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Title:
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PIEZO PROGRAMMABLE RETICLE FOR EUV LITHOGRAPHY
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09198120
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11/23/1998
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Title:
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METHOD FOR CONCURRENTLY DISPATCHING MICROCODE AND DIRECTLY-DECODED INSTRUCTIONS IN A MICROPROCESSOR
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Issue Dt:
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03/06/2001
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09198195
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11/23/1998
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Title:
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METHOD OF FORMING ULTRA-THIN OXIDES WITH LOW TEMPERATURE OXIDATION
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Issue Dt:
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09/19/2000
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09198362
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Filing Dt:
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11/24/1998
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Title:
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METHOD OF FORMING A VOID FREE COPPER INTERCONNECTS
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Patent #:
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Issue Dt:
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10/31/2000
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09199266
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11/25/1998
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Title:
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CHEMICALLY REMOVABLE CU CMP SLURRY ABRASIVE
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09199267
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Filing Dt:
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11/25/1998
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Title:
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COPPER DENDRITE PREVENTION BY CHEMICAL REMOVAL OF DIELECTRIC
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Issue Dt:
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12/19/2000
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Application #:
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09199347
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Filing Dt:
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11/25/1998
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Title:
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CHEMICAL TREATMENT FOR PREVENTING COPPER DENDRITE FORMATION AND GROWTH
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Issue Dt:
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06/13/2000
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Application #:
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09199348
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Filing Dt:
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11/25/1998
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Title:
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METHOD OF PREVENTING COPPER DENDRITE FORMATION AND GROWTH
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Issue Dt:
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01/02/2001
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Application #:
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09199352
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Filing Dt:
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11/25/1998
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Title:
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CHEMICALLY REMOVABLE CU CMP SLURRY ABRASIVE
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Issue Dt:
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12/19/2000
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09199674
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11/25/1998
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METHOD OF FORMING A METAL GATE ELECTRODE USING REPLACED POLYSILICON STRUCTURE
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Issue Dt:
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06/26/2001
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Application #:
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09199967
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Filing Dt:
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11/25/1998
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Title:
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INTERRUPT GATING METHOD FOR PCI BRIDGES
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Issue Dt:
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09/26/2000
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Application #:
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09200016
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Filing Dt:
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11/25/1998
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Title:
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IN-SITU SION DEPOSITION/BAKE/TEOS DEPOSITION PROCESS FOR REDUCTION OF DEFECTS IN INTERLEVEL DIELECTRIC FOR INTEGRATED CIRCUIT INTERCONNECTS
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Issue Dt:
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01/23/2001
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Application #:
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09201995
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Filing Dt:
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12/01/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING GATE ELECTRODE SHARED BETWEEN TWO SETS OF ACTIVE REGIONS AND FABRICATION THEREOF
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09203012
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Filing Dt:
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12/01/1998
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Title:
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SEMICONDUCTOR DEVICE AND FABRICATION METHOD USING A GERMANIUM SACRIFICIAL GATE ELECTRODE
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Issue Dt:
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12/26/2000
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Application #:
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09203150
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH AMORPHOUS SILICON HARD MASK FOR VIA ETCH APPLICATION
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09203283
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH NITRIDE HARD MASK FOR VIA ETCH APPLICATION
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09203447
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Filing Dt:
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12/01/1998
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Title:
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METHOD FOR TRANSFERRING PATTERNS CREATED BY LITHOGRAPHY
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Issue Dt:
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12/19/2000
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09203450
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Filing Dt:
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12/01/1998
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Title:
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THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09203572
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Filing Dt:
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12/02/1998
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Title:
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INTEGRATION OF LOW-K SIOF AS INTER-LAYER DIELECTRIC
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Issue Dt:
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02/15/2000
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09203773
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Filing Dt:
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12/02/1998
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Title:
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MULTI-LEVEL TRANSISTOR FABRICATION METHOD HAVING AN INVERTED, UPPER LEVEL TRANSISTOR WHICH SHARES A GATE CONDUCTOR WITH A NON-INVERTED, LOWER LEVEL TRANSISTOR
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Issue Dt:
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12/05/2000
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09203774
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND SILICON/OXIDE HARD MASK FOR METAL ETCH
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Issue Dt:
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03/13/2001
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Application #:
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09204216
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Filing Dt:
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND BARRIER METAL/OXIDE HARD MASK FOR METAL ETCH
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09204630
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Filing Dt:
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND SION/OXIDE HARD MASK FOR METAL ETCH
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Issue Dt:
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01/09/2001
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Application #:
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09204651
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12/02/1998
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Title:
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ULTRA-THIN RESIST AND OXIDE/NITRIDE HARD MASK FOR METAL ETCH
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Patent #:
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Issue Dt:
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04/24/2001
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09204967
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Filing Dt:
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12/03/1998
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Title:
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METHOD OF MAKING AN ELEVATED SOURCE/DRAIN WITH ENHANCED GRADED SIDEWALLS FOR TRANSISTOR SCALING INTEGRATED WITH SPACER FORMATION
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Issue Dt:
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01/30/2001
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09204978
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Filing Dt:
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12/03/1998
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Title:
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MINIMIZING CACHE OVERHEAD BY STORING DATA FOR COMMUNICATIONS BETWEEN A PERIPHERAL DEVICE AND A HOST SYSTEM INTO SEPARATE LOCATIONS IN MEMORY
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Issue Dt:
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02/06/2001
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09204998
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Filing Dt:
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12/02/1998
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Title:
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METHOD OF FORMING A MOSFET TRANSISTOR WITH A SHALLOW ABRUPT RETROGRADE DOPANT PROFILE
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Issue Dt:
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03/27/2001
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09205010
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Filing Dt:
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12/04/1998
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MARK PROTECTION WITH TRANSPARENT FILM
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Issue Dt:
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12/26/2000
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09205068
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12/04/1998
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Title:
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ANTIREFLECTIVE COATING USED IN THE FABRICATION OF MICROCIRCUIT STRUCTURES IN 0.18 MICRON AND SMALLER TECHNOLOGIES
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Issue Dt:
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12/21/1999
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09205321
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12/04/1998
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Title:
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ARGON DOPED EPITAXIAL LAYERS FOR INHIBITING PUNCHTHROUGH WITHIN A SEMICONDUCTOR DEVICE
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Issue Dt:
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03/13/2001
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09205443
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12/04/1998
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Title:
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USE OF SACRIFICIAL DIELECTRIC STRUCTURE TO FORM SEMICONDUCTOR DEVICE WITH A SELF-ALIGNED THRESHOLD ADJUST AND OVERLYING LOW-RESISTANCE GATE
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Issue Dt:
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05/02/2000
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09205483
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Filing Dt:
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12/04/1998
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Title:
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METHOD FOR DETERMINING THE EFFCIENCY OF A PLANARIZATION PROCESSS
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Issue Dt:
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02/20/2001
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Application #:
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09205522
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Filing Dt:
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12/03/1998
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Title:
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METHOD FOR FORMING A SHALLOW JUNCTION IN A SEMICONDUCTOR DEVICE USING ANTIMONY DIMER
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Issue Dt:
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05/09/2000
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09205583
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12/04/1998
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Title:
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METHOD FOR FABRICATING DUAL LAYER PROTECTIVE BARRIER COPPER METALLIZATION
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09205585
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12/04/1998
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Title:
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APPARATUS AND METHOD FOR MEASURING THE LENGTH OF A TRANSMISSION CABLE
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09205589
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Filing Dt:
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12/04/1998
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Title:
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SINGLE POINT HIGH RESOLUTION TIME RESOLVED PHOTOEMISSION MICROSCOPY SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09205616
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Filing Dt:
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12/04/1998
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Title:
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METHOD OF MANUFACTURING MOSFET WITH DIFFERENTIAL GATE OXIDE THICKNESS ON THE SAME IC CHIP
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Patent #:
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Issue Dt:
|
01/23/2001
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Application #:
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09205790
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Filing Dt:
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12/04/1998
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Title:
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LITHOGRAPHY REFLECTIVE MASK
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Patent #:
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Issue Dt:
|
04/11/2000
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Application #:
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09205791
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Filing Dt:
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12/04/1998
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Title:
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BACKSIDE POLISH EUV MASK AND METHOD OF MANUFACTURE
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Patent #:
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|
Issue Dt:
|
09/05/2000
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Application #:
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09205897
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Filing Dt:
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12/04/1998
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Title:
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ILLUMINATION MODIFICATION SCHEME SYNTHESIS USING LENS CHARACTERIZATION DATA
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Patent #:
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Issue Dt:
|
08/07/2001
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Application #:
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09205898
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Filing Dt:
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12/04/1998
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Title:
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METHODOLOGY FOR EXTRACTING EFFECTIVE LENS ABERRATIONS USING A NEURAL NETWORK
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Patent #:
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Issue Dt:
|
01/11/2000
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Application #:
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09205958
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Filing Dt:
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12/04/1998
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|
Title:
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REWORKABLE EUV MASK MATERIALS
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Patent #:
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Issue Dt:
|
03/27/2001
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Application #:
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09206163
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Filing Dt:
|
12/07/1998
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Title:
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PREVENTION OF CU DENDRITE FORMATION AND GROWTH
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Patent #:
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Issue Dt:
|
01/23/2001
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Application #:
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09206169
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Filing Dt:
|
12/07/1998
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|
Title:
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PREVENTING CU DENDRITE FORMATION AND GROWTH
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Patent #:
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Issue Dt:
|
07/22/2003
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Application #:
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09206170
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Filing Dt:
|
12/07/1998
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Title:
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CHEMICALLY PEVENTING CU DENDRITE FORMATION AND GROWTH BY IMMERSION
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Patent #:
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Issue Dt:
|
03/26/2002
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Application #:
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09206550
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Filing Dt:
|
12/07/1998
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Title:
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SEMICONDUCTOR TOPOGRAPHY HAVING IMPROVED ACTIVE DEVICE ISOLATION AND REDUCED DOPANT MIGRATION
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Patent #:
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Issue Dt:
|
09/26/2000
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Application #:
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09206669
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Filing Dt:
|
12/07/1998
|
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Title:
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METHOD FOR FORMING CONFORMAL BARRIER LAYERS
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Patent #:
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Issue Dt:
|
10/31/2000
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Application #:
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09206951
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Filing Dt:
|
12/08/1998
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING WITHOUT DAMAGING HSQ LAYER AND METAL PATTERN UTILIZING MULTIPLE DIELECTRIC LAYERS
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Patent #:
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|
Issue Dt:
|
11/20/2001
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Application #:
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09207318
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Filing Dt:
|
12/07/1998
|
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Title:
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CHEMICALLY PREVENTING COPPER DENDRITE FORMATION AND GROWTH BY SPRAYING
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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09207675
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Filing Dt:
|
12/09/1998
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Title:
|
HIGH DENSITY CAPPING LAYERS WITH IMPROVED ADHESION TO COPPER INTERCONNECTS
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Patent #:
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Issue Dt:
|
02/27/2001
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Application #:
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09207676
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Filing Dt:
|
12/09/1998
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Title:
|
H2 DIFFUSION BARRIER FORMATION BY NITROGEN INCORPORATION IN OXIDE LAYER
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09207680
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Filing Dt:
|
12/09/1998
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Title:
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METHOD OF FORMING COPPER/COPPER ALLOY INTERCONNECTION WITH REDUCED ELECTROMIGRATION
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Patent #:
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Issue Dt:
|
01/21/2003
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Application #:
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09207971
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Filing Dt:
|
12/09/1998
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Title:
|
METHOD AND SYSTEM FOR PAGE-STATE SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
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Patent #:
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Issue Dt:
|
04/17/2001
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Application #:
|
09208305
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Filing Dt:
|
12/09/1998
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Title:
|
METHOD AND SYSTEM FOR ORIGIN-SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
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Patent #:
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Issue Dt:
|
04/30/2002
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Application #:
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09208522
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Filing Dt:
|
12/09/1998
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Title:
|
METHOD AND SYSTEM FOR DESTINATION-SENSITIVE MEMORY CONTROL AND ACCESS IN DATA PROCESSING SYSTEMS
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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09208569
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Filing Dt:
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12/09/1998
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Title:
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METHOD AND SYSTEM FOR GENERATING AND UTILIZING SPECULATIVE MEMORY ACCESS REQUESTS IN DATA PROCESSING SYSTEMS
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Patent #:
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Issue Dt:
|
10/19/1999
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Application #:
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09208597
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Filing Dt:
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12/08/1998
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Title:
|
MANUFACTURABLE CAPPING LAYER FOR THE FABRICATION OF COBALT SALICIDE STRUCTURES
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Patent #:
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Issue Dt:
|
11/20/2001
|
Application #:
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09208713
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Filing Dt:
|
12/09/1998
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Title:
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METHOD AND SYSTEM FOR SELECTIVELY DISCONNECTING A REDUNDANT POWER DISTRIBUTION NETWORK TO IDENTIFY A SITE OF A SHORT
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Patent #:
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Issue Dt:
|
12/04/2001
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Application #:
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09208909
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Filing Dt:
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12/10/1998
|
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Title:
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PROGRAMMABLE STATE MACHINE
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|
Patent #:
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|
Issue Dt:
|
03/04/2003
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Application #:
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09209119
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Filing Dt:
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12/10/1998
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Title:
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INITIALIZING AND SAVING PERIPHERAL DEVICE CONFIGURATION STATES OF A MICROCONTROLLER USING A UTILITY PROGRAM
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Patent #:
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|
Issue Dt:
|
03/26/2002
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Application #:
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09209190
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Filing Dt:
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12/10/1998
|
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Title:
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METHOD AND APPARATUS FOR SAVING AND LOADING PERIPHERAL DEVICE STATES OF A MICROCONTROLLER VIA A SCAN PATH
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Patent #:
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|
Issue Dt:
|
12/27/2005
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Application #:
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09217213
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Filing Dt:
|
12/21/1998
|
|
Title:
|
ISOLATION STRUCTURE HAVING IMPLANTED SILICON ATOMS AT THE TOP CORNER OF THE ISOLATION TRENCH FILLING VACANCIES AND INTERSTITIAL SITES
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Patent #:
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Issue Dt:
|
10/07/2003
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Application #:
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09217367
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Filing Dt:
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12/21/1998
|
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Title:
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FLEXIBLE PROBE/PROBE RESPONSE ROUTING FOR MAINTAINING COHERENCY
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Patent #:
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Issue Dt:
|
08/14/2001
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Application #:
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09217649
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Filing Dt:
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12/21/1998
|
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Title:
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MESSAGING SCHEME TO MAINTAIN CACHE COHERENCY AND CONSERVE SYSTEM MEMORY BANDWIDTH DURING A MEMORY READ OPERATION IN A MULTIPROCESSING COMPUTER SYSTEM
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Patent #:
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Issue Dt:
|
01/09/2001
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Application #:
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09219146
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Filing Dt:
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12/22/1998
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Title:
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SOURCE/DRAIN JUNCTION AREAS SELF ALIGNED BETWEEN A SIDEWALL SPACER AND AN ETCHED LATERAL SIDEWALL
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Patent #:
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Issue Dt:
|
01/15/2002
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Application #:
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09224820
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Filing Dt:
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01/04/1999
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Title:
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ADDRESS SPACE CONVERSION TO RETAIN SOFTWARE COMPATIBILITY IN NEW ARCHITECTURES
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Patent #:
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Issue Dt:
|
06/26/2001
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Application #:
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09224821
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Filing Dt:
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01/04/1999
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Title:
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COLLATION OF INTERRUPT CONTROL DEVICES
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