|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09225175
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
METHOD OF DEFINING COPPER SEED LAYER FOR SELECTIVE ELECTROLESS PLATING PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09225219
|
Filing Dt:
|
01/04/1999
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
|
Title:
|
NETWORK TRANSCEIVER FOR STEERING NETWORK DATA TO SELECTED PATHS BASED ON DETERMINED LINK SPEEDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
09225248
|
Filing Dt:
|
01/04/1999
|
|
Title:
|
STRUCTURE AND METHOD OF FORMATION OF BODY CONTACTS IN SOI MOSFETS TO ELIMATE FLOATING BODY EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09225539
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
METHOD OF FORMING RELIABLE COPPER INTERCONNECTS WITH IMPROVED HOLE FILLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09225541
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID LINED INTERCONNECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09225542
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH LOW K DIELECTRIC CONSTANT MATERIALS IN DIELECTRIC LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09225546
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
METHOD FOR FORMING LOW DIELECTRIC PASSIVATION OF COPPER INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09225644
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH PRESSURE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09225649
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
GRADED COMPOUND SEED LAYERS FOR SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09225658
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
SILICON OXIDE INSULATOR (SOI) SEMICONDUCTOR HAVING SELECTIVELY LINKED BODY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09225982
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER CONDITION CODE, AND MULTIMEDIA VALUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09226564
|
Filing Dt:
|
01/07/1999
|
|
Title:
|
HIGH PERFORMANCE TRANSISTOR FABRICATED ON A DIELECTRIC FILM AND METHOD OF MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09226881
|
Filing Dt:
|
01/07/1999
|
|
Title:
|
ULTRA SHALLOW EXTENSION FORMATION USING DISPOSABLE SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09227067
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY HIGH TEMPERATURE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09228347
|
Filing Dt:
|
01/11/1999
|
|
Title:
|
METHODOLOGY AND GRAPHICAL USER INTERFACE FOR BUILDING LOGIC SYNTHESIS COMMAND SCRIPTS USING MICRO-TEMPLATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09229264
|
Filing Dt:
|
01/13/1999
|
|
Title:
|
METHOD OF FORMING SUBMICRON-DIMENSIONED METAL PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09229590
|
Filing Dt:
|
01/13/1999
|
|
Title:
|
SEMICONDUCTOR INTERCONNECT INTERFACE PROCESSING BY PULSE LASER ANNEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09231427
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
METHOD OF FABRICATING A TRANSISTOR WITH A DIELECTRIC UNDERLAYER AND DEVICE INCORPORATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09231651
|
Filing Dt:
|
01/15/1999
|
|
Title:
|
DUAL-GATE MOSFET WITH CHANNEL POTENTIAL ENGINEERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09232711
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
SIGNAL MONITORING CIRCUIT FOR DETECTING ASYNCHRONOUS CLOCK LOSS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09233215
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
MECHANISM FOR CAPTURING AND REPORTING INTERRUPT EVENTS OF DIFFERENT CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2001
|
Application #:
|
09233259
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
SYSTEM FOR CANCELING SPECULATIVELY FETCHED INSTRUCTIONS FOLLOWING A BRANCH MIS-PREDICTION IN A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
09233312
|
Filing Dt:
|
01/19/1999
|
|
Title:
|
APPARATUS AND METHOD FOR PREDICTING AN END OF A MICROCODE LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09234456
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
INTERRUPT MANAGEMENT SYSTEM HAVING BATCH MECHANISM FOR HANDLING INTERRUPT EVENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09234528
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
MECHANISM TO PREVENT DATA LOSS IN CASE OF A POWER FAILURE WHILE A PC IS IN SUSPEND TO RAM STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09234855
|
Filing Dt:
|
01/22/1999
|
|
Title:
|
CMOS TRANSISTOR DESIGN FOR SHARED N+/P+ ELECTRODE WITH ENHANCED DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09234992
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
METHOD AND APPARATUS FOR MEASURING CUMULATIVE DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09237001
|
Filing Dt:
|
01/25/1999
|
|
Title:
|
METHOD FOR FABRICATING A TRENCH-GATED VERTICAL CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09237258
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
METHOD OF FORMING MULTIPLE LEVELS OF PATTERNED METALLIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09237573
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
APPARATUS FOR FORMING A COPPER INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09237584
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
COPPER/LOW DIELECTRIC INTERCONNECT FORMATION WITH REDUCED ELECTROMIGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09238047
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
NETWORK SWITCHING SYSTEM HAVING OVERFLOW BYPASS IN INTERNAL RULES CHECKER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09238051
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
HIGH PLANARITY HIGH-DENSITY IN-LAID METALLIZATION PATTERNS BY DAMASCENE-CMP PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09238081
|
Filing Dt:
|
01/26/1999
|
|
Title:
|
MULTI-LAYER GATE CONDUCTOR HAVING A DIFFUSION BARRIER IN THE BOTTOM LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09238249
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
SUBSTANTIALLY UNDETECTABLE DATA PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09238359
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
PRE-AMORPHIZATION PROCESS FOR SOURCE/DRAIN JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09238829
|
Filing Dt:
|
01/28/1999
|
|
Title:
|
READ AHEAD BUFFER FOR READ ACCESSES TO SYSTEM MEMORY BY INPUT/OUTPUT DEVICES WITH BUFFER VALID INDICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09241265
|
Filing Dt:
|
02/01/1999
|
|
Title:
|
FIELD LEAKAGE BY USING A THIN LAYER OF NITRIDE DEPOSITED BY CHEMICAL VAPOR DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09244416
|
Filing Dt:
|
02/04/1999
|
|
Title:
|
MECHANISM FOR ACCUMULATING DATA TO DETERMINE AVERAGE VALUES OF PERFORMANCE PARAMETERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09244913
|
Filing Dt:
|
02/04/1999
|
|
Title:
|
BORON IMPLANTED DIELECTRIC STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09245161
|
Filing Dt:
|
02/04/1999
|
|
Title:
|
STI PUNCH-THROUGH DEFECTS AND STRESS REDUCTION BY HIGH TEMPERATURE OXIDE REFLOW PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09245727
|
Filing Dt:
|
02/08/1999
|
|
Title:
|
MOSFET WITH GATE PLUG USING DIFFERENTIAL OXIDE GROWTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09246270
|
Filing Dt:
|
02/08/1999
|
|
Title:
|
Fetching Instructions From An Instruction Cache Using Sequential Way Prediction
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09246462
|
Filing Dt:
|
02/09/1999
|
|
Title:
|
ULTRA-THIN GATE OXIDE FORMATION USING AN N2O PLASMA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09247659
|
Filing Dt:
|
02/10/1999
|
|
Title:
|
MANAGEMENT OF MOVE REQUESTS FROM A FACTORY SYSTEM TO AN AUTOMATED MATERIAL HANDLING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09247876
|
Filing Dt:
|
02/10/1999
|
|
Title:
|
SCALABLE VIRTUAL TIMER ARCHITECTURE FOR EFFICIENTLY IMPLEMENTING MULTIPLE HARDWARE TIMERS WITH MINIMAL SILICON OVERHEAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09248432
|
Filing Dt:
|
02/11/1999
|
|
Title:
|
METHOD FOR FORMING AN INTEGRATED CIRCUIT MEMORY CELL AND PRODUCT THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09248433
|
Filing Dt:
|
02/11/1999
|
|
Title:
|
INTEGRATED CIRCUIT TRANSISTOR WITH LOW-RESISTIVITY SOURCE/DRAIN STRUCTURES AT LEAST PARTIALLY RECESSED WITHIN A DIELECTRIC BASE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
09248723
|
Filing Dt:
|
02/10/1999
|
|
Title:
|
NOVEL METALLIZATION STACK STRUCTURE TO IMPROVE ELECTROMIGRATION RESISTANCE AND KEEP LOW RESISTIVITY OF ULSI INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09250174
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH A MODULATED GATE OXIDE THICKNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2000
|
Application #:
|
09250981
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
RECORDER BUFFER AND A METHOD FOR ALLOCATING A FIXED AMOUNT OF STORAGE FOR INSTRUCTION RESULTS INDEPENDENT OF A NUMBER OF CONCURRENTLY DISPATCHED INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09251012
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
LOCATION DEPENDENT AUTOMATIC DEFECT CLASSIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09251059
|
Filing Dt:
|
02/18/1999
|
|
Title:
|
DISSOLVABLE DIELECTRIC METHOD AND STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09252184
|
Filing Dt:
|
02/18/1999
|
|
Title:
|
METHOD OF FORMING LOW DIELECTRIC TUNGSTEN LINED INTERCONNECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09252898
|
Filing Dt:
|
02/18/1999
|
|
Title:
|
UNIFIED MULTI-FUNCTION OPERATION SCHEDULER FOR OUT-OF-ORDER EXCUTION IN A SUPERSCALAR PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09253466
|
Filing Dt:
|
02/19/1999
|
|
Title:
|
METHOD AND APPARATUS FOR INSTRUCTION QUEUE COMPRESSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09253479
|
Filing Dt:
|
02/19/1999
|
|
Title:
|
FABRICATION OF A VIA PLUG HAVING HIGH ASPECT RATIO WITH DIFFUSION BARRIER LAYER EFFECTIVELY SURROUNDING THE VIA PLUG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09253480
|
Filing Dt:
|
02/19/1999
|
|
Title:
|
METHOD FOR FILLING A DUAL DAMASCENE OPENING HAVING HIGH ASPECT RATIO TO MINIMIZE ELECTROMIGRATION FAILURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09255203
|
Filing Dt:
|
02/22/1999
|
|
Title:
|
STEP DRAIN AND SOURCE JUNCTION FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09255604
|
Filing Dt:
|
02/22/1999
|
|
Title:
|
PROCESS FOR FORMING ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09255707
|
Filing Dt:
|
02/23/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PROCESSING HIGH AND LOW PRIORITY FRAME DATA TRANSMITTED IN A DATA COMMUNICATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09255917
|
Filing Dt:
|
02/23/1999
|
|
Title:
|
HIGH K INTEGRATION OF GATE DIELECTRIC WITH INTEGRATED SPACER FORMATION FOR HIGH SPEED CMOS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09256541
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
METHOD OF FABRICATING SUB-MICRON METAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09256779
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY AND SELECTIVELY DOWN SHIFTING LINK SPEED BASED ON LOCAL CONFIGURATION SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
09256780
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
ARRANGEMENT IN A NETWORK REPEATER FOR MONITORING LINK INTEGRITY BY MONITORING SYMBOL ERRORS ACROSS MULTIPLE DETECTION INTERVALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09256781
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
METHOD OF FORMING JUNCTION-LEAKAGE FREE METAL SILICIDE IN A SEMICONDUCTOR WAFER BY AMORPHIZATION OF REFACTORY METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09256782
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
METHOD OF FORMING JUNCTION-LEAKAGE FREE METAL SILICIDE IN A SEMICONDUCTOR WAFER BY AMORPHIZATION OF SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
09257521
|
Filing Dt:
|
02/25/1999
|
|
Title:
|
COMMUNICATION PROTOCOL PROCESSOR HAVING MULTIPLE MICROPROCESSOR CORES CONNECTED IN SERIES AND DYNAMICALLY REPROGRAMMED DURING OPERATION VIA INSTRUCTIONS TRANSMITTED ALONG THE SAME DATA PATHS USED TO CONVEY COMMUNICATION DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09258763
|
Filing Dt:
|
02/26/1999
|
|
Title:
|
VARIABLE SYMBOLIC LINKS FOR A FILE IN A UNIX OPERATING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09258834
|
Filing Dt:
|
02/26/1999
|
|
Title:
|
SEMICONDUCTOR FABRICATION EXTENDED PARTICLE COLLECTION CUP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09258959
|
Filing Dt:
|
03/01/1999
|
|
Title:
|
EXTREME ULTRAVIOLET LITHOGRAPHY REFLECTIVE MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09260255
|
Filing Dt:
|
03/02/1999
|
|
Title:
|
METHOD OF FORMING A SUPER-SHALLOW AMORPHOUS LAYER IN SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09260790
|
Filing Dt:
|
03/01/1999
|
|
Title:
|
METHOD FOR PREPARING NARROW PHOTORESIST LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09260821
|
Filing Dt:
|
03/02/1999
|
|
Title:
|
METHOD FOR FABRICATING A MOSFET DEVICE STRUCTURE WHICH FACILITATES MITIGATION OF JUNCTION CAPACITANCE AND FLOATING BODY EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09261116
|
Filing Dt:
|
03/03/1999
|
|
Title:
|
APPARATUS AND METHOD FOR DETECTING MICROBRANCHES EARLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09261273
|
Filing Dt:
|
03/03/1999
|
|
Title:
|
MULTIPLE SEMICONDUCTOR-ON-INSULATOR THRESHOLD VOLTAGE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09261886
|
Filing Dt:
|
03/03/1999
|
|
Title:
|
APPARATUS AND METHOD FOR FLOATING POINT EXCHANGE DISPATCH WITH REDUCED LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09262214
|
Filing Dt:
|
03/04/1999
|
|
Title:
|
DUMMY PATTERNING FOR SEMICONDUCTOR MANUFACTURING PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09263557
|
Filing Dt:
|
03/08/1999
|
|
Title:
|
MOS TRANSISTOR WITH ASSISTED-GATE FOR ULTRA-LARGE-SCALE INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09270240
|
Filing Dt:
|
03/15/1999
|
|
Title:
|
SYSTEM FOR USING AN INDEPENDENT CLOCK TO COORDINATE ACCESS TO DATA REGISTERS WITHIN A MODULE BETWEEN PERIPHERAL DEVICE AND A HOST SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09276422
|
Filing Dt:
|
03/25/1999
|
|
Title:
|
METHODS FOR IDENTIFYING SOURCES OF PATTERNS IN PROCESSING EFFECTS IN MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2002
|
Application #:
|
09276839
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
METHOD FOR RAMPED CURRENT DENSITY PLATING OF SEMICONDUCTOR VIAS AND TRENCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09277511
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
METHOD FOR FABRICATING HIGH PERMITIVITY DIELECTRIC STACKS HAVING LOW BUFFER OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09280391
|
Filing Dt:
|
03/29/1999
|
|
Title:
|
(METHOD OF MAKING) A CHEMICAL-MECHANICAL POLISHING SLURRY THAT REDUCES WAFER DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09280648
|
Filing Dt:
|
03/29/1999
|
|
Title:
|
A SYSTEM FOR TESTING TRANSMITTER LOGIC OF A PHYSICAL LAYER DEVICE IN A LOCAL AREA NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09281079
|
Filing Dt:
|
03/30/1999
|
|
Title:
|
DETECTING FULL CONDITIONS IN A QUEUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09281975
|
Filing Dt:
|
03/31/1999
|
|
Title:
|
FRAME ASSEMBLY IN DEQUEUING BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09282033
|
Filing Dt:
|
03/30/1999
|
|
Title:
|
METHOD OF MAKING DISPOSABLE CHANNEL MASKING FOR BOTH SOURCE/DRAIN AND LDD IMPLANT AND SUBSEQUENT GATE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09283753
|
Filing Dt:
|
04/02/1999
|
|
Title:
|
POLYSILICON GATE HAVING A METAL PLUG FOR REDUCED GATE RESISTANCE WITHIN A TRENCH EXTENDING INTO THE POLYSILICON LAYER OF THE GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09283754
|
Filing Dt:
|
04/02/1999
|
|
Title:
|
PLASMA TREATMENT TO REDUCE STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09283889
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
METHOD TO PRODUCE SMALL SPACE PATTERN USING PLASMA POLYMERIZATION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09285388
|
Filing Dt:
|
04/02/1999
|
|
Title:
|
METHOD OF REDUCING STRESS CORROSION INDUCED VOIDING OF PATTERNED METAL LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09286401
|
Filing Dt:
|
04/05/1999
|
|
Title:
|
FORMING MINIMAL SIZE SPACES IN INTEGRATED CIRCUIT CONDUCTIVE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09286997
|
Filing Dt:
|
04/07/1999
|
|
Title:
|
ADAPTIVE TRANSMISSION SYSTEM IN A NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09289669
|
Filing Dt:
|
04/12/1999
|
|
Title:
|
HIGH DENSITY ISOLATION USING AN IMPLANT AS A POLISH STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09289950
|
Filing Dt:
|
04/13/1999
|
|
Title:
|
NETWORK TRANSCEIVER HAVING MEDIA INDEPENDENT INTERFACE OPERABLE IN A GENERAL PURPOSE SERIAL INTERFACE MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09289951
|
Filing Dt:
|
04/13/1999
|
|
Title:
|
NETWORK TRANSCEIVER HAVING CIRCUITRY FOR REFERENCING TRANSMIT DATA TO A SELECTED INPUT CLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09289953
|
Filing Dt:
|
04/13/1999
|
|
Title:
|
HANDSHAKING BETWEEN REPEATER AND PHYSICAL LAYER DEVICE IN A VARIABLE RATE NETWORK TRANSCEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09290086
|
Filing Dt:
|
04/12/1999
|
|
Title:
|
PROCESS FOR FABRICATING A METAL SEMICONDUCTOR DEVICE COMPONENT BY LATERAL OXIDIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09290087
|
Filing Dt:
|
04/12/1999
|
|
Title:
|
PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE COMPONENT USING A SELECTIVE SILICIDATION REACTION
|
|
