|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09357969
|
Filing Dt:
|
07/21/1999
|
|
Title:
|
SPACER-ASSISTED ULTRANARROW SHALLOW TRENCH ISOLATION FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09359502
|
Filing Dt:
|
07/23/1999
|
|
Title:
|
METHOD OF FORMING RECTANGULAR SHAPED SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09359988
|
Filing Dt:
|
07/22/1999
|
|
Title:
|
STATISTICAL PROCESS CONTROL SYSTEM WITH NORMALIZED CONTROL CHARTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09362636
|
Filing Dt:
|
07/26/1999
|
|
Title:
|
EFFICIENT PROCESS TOOL UTILIZATION IN SEMICONDUCTOR MANUFACTURING USING AN ADDITIONAL PROCESS TOOL STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09364976
|
Filing Dt:
|
07/31/1999
|
|
Title:
|
METHOD FOR SHAPING PHOTORESIST MASK TO IMPROVE HIGH ASPECT RATIO ION IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09365407
|
Filing Dt:
|
08/02/1999
|
|
Title:
|
SIMPLIFIED METHOD OF PATTERNING POLYSILICON GATE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09366216
|
Filing Dt:
|
08/02/1999
|
|
Title:
|
SIMPLIFIED METHOD OF PATTERNING POLYSILICON GATE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09366486
|
Filing Dt:
|
08/03/1999
|
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING POLYSILICON FEATURE CRITICAL DIMENSION DURING PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09369099
|
Filing Dt:
|
08/05/1999
|
|
Title:
|
FABRICATION OF FIELD EFFECT TRANSISTORS HAVING DUAL GATES WITH GATE DIELECTRICS OF HIGH DIELECTRIC CONSTANT USING LOWERED TEMPERATURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09369217
|
Filing Dt:
|
08/05/1999
|
|
Title:
|
FABRICATION OF FIELD EFFECT TRANSISTORS HAVING DUAL GATES WITH GATE DIELECTRICS OF HIGH DIELECTRIC CONSTANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09369602
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
HIGH-TEMPERATURE FLUORINATED CHEMISTRY REMOVAL OF CONTACT BARC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09370789
|
Filing Dt:
|
08/05/1999
|
|
Title:
|
OPTIMIZED ALLOCATION OF MULTI-PIPELINE EXECUTABLE AND SPECIFIC PIPELINE EXECUTABLE INSTRUCTIONS TO EXECUTION PIPELINES BASED ON CRITERIA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09371498
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD AND APPARATUS FOR CHARACTERIZING A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09371550
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD AND APPARATUS FOR RUN-TO-RUN CONTROLLING OF OVERLAY REGISTRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09371561
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD FOR IDENTIFYING AND CONTROLLING IMPACT OF AMBIENT CONDITIONS ON PHOTOLITHOGRAPHY PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09371635
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
METHOD FOR ADJUSTING INCOMING FILM THICKNESS UNIFORMITY SUCH THAT VARIATIONS ACROSS THE FILM AFTER POLISHING ARE MINIMIZED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
09371665
|
Filing Dt:
|
08/10/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING RUN-TO-RUN CONTROL IN A BATCH MANUFACTURING ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09371919
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
SHALLOW TRENCH ISOLATION FORMATION WITHOUT PLANARIZATION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09371921
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
PROTECTIVE OXIDE BUFFER LAYER FOR ARC REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09371922
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
THERMALLY GROWN PROTECTIVE OXIDE BUFFER LAYER FOR ARC REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09372014
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING WITHIN-WAFER UNIFORMITY IN CHEMICAL MECHANICAL POLISHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09372515
|
Filing Dt:
|
08/11/1999
|
|
Title:
|
METHOD FOR DETERMINING A POLISHING RECIPE BASED UPON THE MEASURED PRE-POLISH THICKNESS OF A PROCESS LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
09372705
|
Filing Dt:
|
08/11/1999
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2001
| | | | |
|
Title:
|
TRANSISTOR WITH DYNAMIC SOURCE/DRAIN EXTENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09373218
|
Filing Dt:
|
08/12/1999
|
|
Title:
|
INCORPORATION OF CRITICAL DIMENSION MEASUREMENTS AS DISTURBANCES TO LITHOGRAPHY OVERLAY RUN TO RUN CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09373482
|
Filing Dt:
|
08/12/1999
|
|
Title:
|
INTEGRATED CIRCUIT WITH IMPROVED ADHESION BETWEEN INTERFACES OF CONDUCTIVE AND DIELECTRIC SURFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09373483
|
Filing Dt:
|
08/12/1999
|
|
Title:
|
SURFACE TREATMENT OF LOW-K SIOF TO PREVENT METAL INTERACTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09373571
|
Filing Dt:
|
08/13/1999
|
|
Title:
|
EXPOSURE DURING REWORK FOR ENHANCED RESIST REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09375004
|
Filing Dt:
|
08/16/1999
|
|
Title:
|
METHOD OF USING A SILICON OXYNITRIDE ARC FOR FINAL METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
09375120
|
Filing Dt:
|
08/16/1999
|
|
Title:
|
METHOD AND APPARATUS FOR ADAPTIVE FRAME TRACKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09375588
|
Filing Dt:
|
08/17/1999
|
|
Title:
|
PRACTICAL WAY TO REMOVE HEAT FROM SOI DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09378348
|
Filing Dt:
|
08/20/1999
|
|
Title:
|
FEEDBACK CONTROL OF DEPOSITION THICKNESS BASED ON POLISH PLANARIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
09378870
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
SDRAM READ PREFETCH FROM MULTIPLE MASTER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09378873
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
DIRECT MEMORY ACCESS CONTROLLER WITH CHANNEL WIDTH CONFIGURABILITY SUPPORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09378985
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
METHOD AND APPARATUS FOR NON-CONCURRENT ARBITRATION OF MULTIPLE BUSSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09379014
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
SYNCHRONIZING DATA BETWEEN DIFFERING CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09379020
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
FLEXIBLE ADDRESS PROGRAMMING WITH WRAP BLOCKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
09379047
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
SUBSTRATE REMOVAL AS A FUNCTION OF EMITTED PHOTONS AT THE BACK SIDE OF A SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09379456
|
Filing Dt:
|
08/23/1999
|
|
Title:
|
FLEXIBLE PC/AT-COMPATIBLE MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09383480
|
Filing Dt:
|
08/26/1999
|
|
Title:
|
UNICODE-BASED DRIVERS, DEVICE CONFIGURATION INTERFACE AND METHODOLGY FOR CONFIGURING SIMILAR BUT POTENTIALLY INCOMPATIBLE PERIPHERAL DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09383733
|
Filing Dt:
|
08/26/1999
|
|
Title:
|
NAVIGATION USING 3-D DETECTABLE PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
09383876
|
Filing Dt:
|
08/26/1999
|
|
Title:
|
POLISHING UNIFORMITY VIA PAD CONDITIONING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
09386112
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
DUAL-DIFFERENTIAL INTERFEROMETRY FOR SILICON DEVICE DAMAGE DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09386650
|
Filing Dt:
|
08/31/1999
|
|
Title:
|
SYSTEM AND METHOD FOR INITIATING A SERIAL DATA TRANSFER BETWEEN TWO CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09387024
|
Filing Dt:
|
08/31/1999
|
|
Title:
|
MASSIVELY PARALLEL INSTRUCTION PREDECODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
09387174
|
Filing Dt:
|
08/31/1999
|
|
Title:
|
SCHEDULING METHOD FOR AUTOMATED WORK-CELL TRANSFER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09387175
|
Filing Dt:
|
08/31/1999
|
|
Title:
|
REALTIME DECISION MAKING SYSTEM FOR REDUCTION OF TIME DELAYS IN AN AUTOMATED MATERIAL HANDLING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09391301
|
Filing Dt:
|
09/07/1999
|
|
Title:
|
METHOD FOR FABRICATING HIGH-PERFORMANCE SUBMICRON MOSFET WITH LATERAL ASYMMETRIC CHANNEL AND A LIGHTLY DOPED DRAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09391303
|
Filing Dt:
|
09/07/1999
|
|
Title:
|
METHOD FOR FABRICATING HIGH-PERFORMANCE SUBMICRON MOSFET WITH LATERAL ASYMMETRIC CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09392230
|
Filing Dt:
|
09/08/1999
|
|
Title:
|
EXTREME ULTRAVIOLET LITHOGRAPHY MASK BLANK AND MANUFACTURING METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09392300
|
Filing Dt:
|
09/08/1999
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR CONFIGURED TO PREDICT RETURN ADDRESSES FROM A RETURN STACK STORAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09393176
|
Filing Dt:
|
09/09/1999
|
|
Title:
|
METHOD AND APPARATUS FOR INTEGRATING NEAR REAL-TIME FAULT DETECTION IN AN APC FRAMEWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09397217
|
Filing Dt:
|
09/16/1999
|
|
Title:
|
SOURCE/DRAIN DOPING TECHNIQUE FOR ULTRA-THIN-BODY SOI MOS TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09397292
|
Filing Dt:
|
09/15/1999
|
|
Title:
|
DEFECT COLLECTING STRUCTURES FOR PHOTOLITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09398246
|
Filing Dt:
|
09/17/1999
|
|
Title:
|
MOS-GATE TUNNELING-INJECTION BIPOLAR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09398624
|
Filing Dt:
|
09/17/1999
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2003
| | | | |
|
Title:
|
RESPONSE VIRTUAL CHANNEL FOR HANDLING ALL RESPONSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09398641
|
Filing Dt:
|
09/17/1999
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
|
Title:
|
ULTRA-THIN RESIST SHALLOW TRENCH PROCESS USING HIGH SELECTIVITY NITRIDE ETCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09398642
|
Filing Dt:
|
09/17/1999
|
|
Title:
|
METHOD FOR CREATING THINNER RESIST COATING THAT ALSO HAS FEWER PINHOLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09398955
|
Filing Dt:
|
09/17/1999
|
|
Title:
|
IMPLEMENTING LOCKS IN A DISTRIBUTED PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09400524
|
Filing Dt:
|
09/20/1999
|
|
Title:
|
REDUCED CHANNEL LENGTH LIGHTLY DOPED DRAIN TRANSISTOR USING A SUB-AMORPHOUS LARGE TILT ANGLE IMPLANT TO PROVIDE ENHANCED LATERAL DIFFUSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09401089
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
METHOD AND APPARATUS FOR GENERATING REAL-TIME DATA FROM STATIC FILES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09401090
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
PROCESS CONTROL WITH CONTROL SIGNAL DERIVED FROM METROLOGY OF A REPETITIVE CRITICAL DIMENSION FEATURE OF A TEST STRUCTURE ON THE WORK PIECE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09401585
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
METHOD FOR CONTROLLING PHOTORESIST REMOVAL PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09401586
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
STEPPER WITH EXPOSURE TIME MONITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09405266
|
Filing Dt:
|
09/23/1999
|
|
Title:
|
METHOD FOR REDUCING LATERAL DOPANT GRADIENT IN SOURCE/DRAIN EXTENSION OF MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09405831
|
Filing Dt:
|
09/24/1999
|
|
Title:
|
PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09406169
|
Filing Dt:
|
09/23/1999
|
|
Title:
|
METHOD FOR FORMING SOI FILM BY LASER ANNEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09406451
|
Filing Dt:
|
09/27/1999
|
|
Title:
|
HIGH-SPEED LATERAL BIPOLAR DEVICE IN SOI PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
09407504
|
Filing Dt:
|
09/28/1999
|
|
Title:
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METHOD AND APPARATUS FOR THE CHANNELIZATION OF CELL OR PACKET TRAFFIC OVER STANDARD PC BUSES
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09408241
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Filing Dt:
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09/29/1999
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Title:
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USE OF CONTAMINATION-FREE MANUFACTURING DATA IN FAULT DETECTION AND CLASSIFICATION AS WELL AS IN RUN-TO-CONTROL
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09408881
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Filing Dt:
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09/29/1999
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Title:
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SUSBTRATE REMOVAL AS A FUNCTION OF RESISTANCE AT THE BACK SIDE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09409088
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Filing Dt:
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09/30/1999
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Title:
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QUADRANT AVALANCHE PHOTODIODE TIME-RESOLVED DETECTION
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09409974
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Filing Dt:
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09/30/1999
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Title:
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PICOSECOND IMAGING CIRCUIT ANALYSIS PROBE AND SYSTEM
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09410526
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Filing Dt:
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10/01/1999
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Title:
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MARK PROTECTION SCHEME WITH NO MASKING
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09410852
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Filing Dt:
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10/01/1999
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Title:
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COMPUTER SYSTEM IMPLEMENTING FLUSH OPERATION
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09412215
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Filing Dt:
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10/05/1999
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Title:
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CONTROLLING AN ETCHING PROCESS OF MULTIPLE LAYERS BASED UPON THICKNESS RATIO OF THE DIELECTRIC LAYERS
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09412216
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Filing Dt:
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10/05/1999
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Title:
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METHOD AND APPARATUS FOR CONTROLLING PHOTOLITHOGRAPHY PARAMETERS BASED ON PHOTORESIST IMAGES
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09412679
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Filing Dt:
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10/05/1999
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Title:
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METHOD AND APPARATUS FOR MONITORING CONTROLLER PERFORMANCE USING STATISTICAL PROCESS CONTROL
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09413737
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Filing Dt:
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10/06/1999
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Title:
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OPTIMIZATION OF LOGIC GATES WITH CRISS-CROSS IMPLANTS TO FORM ASYMMETRIC CHANNEL REGIONS
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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09413965
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Filing Dt:
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10/07/1999
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Title:
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MULTIPLE PROTECTED MODE EXECUTION ENVIRONMENTS USING MULTIPLE REGISTER SETS AND META-PROTECTED INSTRUCTIONS
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09414107
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Filing Dt:
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10/07/1999
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Title:
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METHOD AND APPARATUS FOR OPTIMAL WAFER-BY-WAFER PROCESSING
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09414190
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Filing Dt:
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10/07/1999
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Title:
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METHOD AND APPARATUS FOR AUTOMATIC CALIBRATION OF CRITICAL DIMENSION METROLOGY TOOL
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09415427
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Filing Dt:
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10/08/1999
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Title:
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HOME-APPLIANCE NETWORK WITH NODES IDENTIFIED BY DIRECT-SEQUENCE SPREADING CODES
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09415892
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Filing Dt:
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10/08/1999
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Title:
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USER-PRIORITIZED CACHE REPLACEMENT
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09416071
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Filing Dt:
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10/12/1999
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Title:
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METHOD AND APPARATUS FOR HIERARCHICAL STORAGE OF DATA FOR EFFICIENT ARCHIVING AND RETRIEVAL OF DATA
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09416275
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Filing Dt:
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10/14/1999
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Title:
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PREDICTOR MISS DECODER UPDATING LINE PREDICTOR STORING INSTRUCTION FETCH ADDRESS AND ALIGNMENT INFORMATION UPON INSTRUCTION DECODE TERMINATION CONDITION
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09416383
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Filing Dt:
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10/12/1999
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Title:
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ELECTROLESS PLATED SEMICONDUCTOR VIAS AND CHANNELS
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09417839
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Filing Dt:
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10/14/1999
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Title:
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METHOD OF FORMING COBALT SILICIDE
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09417840
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Filing Dt:
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10/14/1999
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Title:
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METHOD OF FORMING A LOCAL INTERCONNECT WITH IMPROVED ETCH SELECTIVITY OF SILICON DIOXIDE/SILICIDE
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09417842
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Filing Dt:
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10/14/1999
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Title:
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METHOD OF FORMING A LOCAL INTERCONNECT WITH IMPROVED ETCH SELECTIVITY OF SILICON DIOXIDE/SILICIDE
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09418276
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Filing Dt:
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10/14/1999
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Title:
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METHOD FOR EFFECTIVE FABRICATION OF A FIELD EFFECT TRANSISTOR WITH ELEVATED DRAIN AND SOURCE CONTACT STRUCTURES
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09418407
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Filing Dt:
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10/14/1999
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Title:
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FORMING A REMOVABLE SPACER OF UNIFORM WIDTH ON SIDEWALLS OF A GATE OF A FIELD EFFECT TRANSISTOR DURING A DIFFERENTIAL RAPID THERMAL ANNEAL PROCESS
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09419832
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Filing Dt:
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10/14/1999
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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TRAINING LINE PREDICTOR FOR BRANCH TARGETS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09420605
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Filing Dt:
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10/18/1999
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Title:
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SILICON-ON-INSULATOR CONFIGURATION WHICH IS COMPATIBLE WITH BULK CMOS ARCHITECTURE
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09420972
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Filing Dt:
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10/20/1999
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Title:
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FIELD EFFECT TRANSISTOR WITH NON-FLOATING BODY AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09421305
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Filing Dt:
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10/20/1999
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Publication #:
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Pub Dt:
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02/28/2002
| | | | |
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Title:
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FIELD EFFECT TRANSISTOR WITH NON-FLOATING BODY AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09421639
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Filing Dt:
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10/20/1999
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Title:
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METHOD OF FORMATION OF PSEUDO-SOI STRUCTURES WITH DIRECT CONTACT OF TRANSISTOR BODY TO THE SUBSTRATE
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09422260
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Filing Dt:
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10/21/1999
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Title:
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APPARATUS AND METHOD FOR IMPLEMENTING A HOME NETWORK USING CUSTOMER-PREMISES POWER LINES
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09422310
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Filing Dt:
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10/21/1999
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Title:
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SIMULTANEOUS HEATING AND EXPOSURE OF RETICLE WITH PATTERN PLACEMENT CORRECTION
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09422591
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Filing Dt:
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10/21/1999
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Title:
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DYNAMIC WIEGHTED ROUND ROBIN QUEUING
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09422592
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Filing Dt:
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10/21/1999
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Title:
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METHODOLOGY FOR MITIGATING FORMATION OF T-TOPS IN PHOTORESIST
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