|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09564211
|
Filing Dt:
|
05/04/2000
|
|
Title:
|
Method and system of managing wafers in a semiconductor device production facility
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
09564408
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
Use of RTA furnace for photoresist baking
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09565691
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
UV-ENHANCED SILYLATION PROCESS TO INCREASE ETCH RESISTANCE OF ULTRA THIN RESISTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09565858
|
Filing Dt:
|
05/05/2000
|
|
Title:
|
Method for forming a semiconductor device with a tailored well profile
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09566216
|
Filing Dt:
|
05/05/2000
|
|
Title:
|
Dependency table for reducing dependency checking hardware
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
09566732
|
Filing Dt:
|
05/09/2000
|
|
Title:
|
ARRANGEMENT FOR READING A PRESCRIBED LOCATION OF A FIFO BUFFER IN A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09568181
|
Filing Dt:
|
05/09/2000
|
|
Title:
|
APPARATUS AND METHOD OF IMPLEMENTING A UNIVERSAL HOME NETWORK ON A CUSTOMER PREMISES UPN TELEPHONE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09568182
|
Filing Dt:
|
05/09/2000
|
|
Title:
|
APPARATUS AND METHOD OF COUPLING HOME NETWORK SIGNALS BETWEEN AN ANALOG PHONE LINE AND A DIGITAL UPN LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09569039
|
Filing Dt:
|
05/11/2000
|
|
Title:
|
SPECULATIVE OPENING OF A NEW PAGE WHEN APPROACHING PAGE BOUNDARY DURING READ/WRITE OF ISOCHRONOUS STREAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09569753
|
Filing Dt:
|
05/12/2000
|
|
Title:
|
UNIVERSAL MULTI-TOOL ADAPTER FOR RECONFIGURING A WAFER PROCESSING LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09575463
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
09576511
|
Filing Dt:
|
05/23/2000
|
|
Title:
|
BROADBAND DISTRIBUTION OF SECS-II DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09577403
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED GENERATION OF TEST SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
09577527
|
Filing Dt:
|
05/24/2000
|
|
Title:
|
GRAPHICS SUBSYSTEM INCLUDING A RAMDAC IC WITH DIGITAL VIDEO STORAGE INTERFACE FOR CONNECTION TO A GRAPHICS BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
09577677
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
IMMEDIATE NEGATIVE ACKNOWLEDGEMENT FOR A COMMUNICATION NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
09577706
|
Filing Dt:
|
05/23/2000
|
|
Title:
|
Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09577756
|
Filing Dt:
|
05/23/2000
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING DEPOSITION PROCESS USING RESIDUAL GAS ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09577769
|
Filing Dt:
|
05/24/2000
|
|
Title:
|
METHOD FOR CONTROLLING DEPOSITION PARAMETERS BASED ON POLYSILICON GRAIN SIZE FEEDBACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09578101
|
Filing Dt:
|
05/22/2000
|
|
Title:
|
INTEGRATED WAFER STOCKER AND SORTER WITH INTEGRITY VERIFICATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09578954
|
Filing Dt:
|
05/25/2000
|
|
Title:
|
INDEX GENERATION FOR HISTORY BASED BRANCH PREDICTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09579245
|
Filing Dt:
|
05/25/2000
|
|
Title:
|
BRANCH PREDICTOR THAT SELECTS BETWEEN PREDICTIONS BASED ON STORED PREDICTION SELECTOR AND BRANCH PREDICTOR INDEX GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2002
|
Application #:
|
09579310
|
Filing Dt:
|
05/25/2000
|
|
Title:
|
Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
09580098
|
Filing Dt:
|
05/30/2000
|
|
Title:
|
TEMPERATURE CONTROL OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
09583617
|
Filing Dt:
|
05/31/2000
|
|
Title:
|
ELECTRICAL PROBING OF SOI CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
09584301
|
Filing Dt:
|
05/31/2000
|
|
Title:
|
METHOD AND APPARATUS FOR POWERING DOWN THE CPU/MEMORY CONTROLLER COMPLEX WHILE PRESERVING THE SELF REFRESH STATE OF MEMORY IN THE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09585199
|
Filing Dt:
|
06/01/2000
|
|
Title:
|
METHOD FOR RELATING PHOTOLITHOGRAPHY OVERLAY TARGET DAMAGE AND CHEMICAL MECHANICAL PLANARIZATION (CMP) FAULT DETECTION TO CMP TOOL INDENTIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09586516
|
Filing Dt:
|
06/02/2000
|
|
Title:
|
METHOD OF FORMING SELF-ALIGNED EXTENSION JUNCTION FOR REDUCED GATE CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
09586575
|
Filing Dt:
|
06/02/2000
|
|
Title:
|
FIFO WITH UNDO-PUSH CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
09588295
|
Filing Dt:
|
06/07/2000
|
|
Title:
|
PACKET CLASSIFICATION USING HASH KEY SIGNATURES GENERATED FROM INTERRUPTED HASH FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09589378
|
Filing Dt:
|
06/07/2000
|
|
Title:
|
Poly gate CD passivation for metrology control
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09589839
|
Filing Dt:
|
06/08/2000
|
|
Title:
|
Methods and apparatus for forming a copper interconnect
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09590685
|
Filing Dt:
|
06/09/2000
|
|
Title:
|
SYSTEM AND METHOD FOR NETWORK MANAGEMENT OF LOCAL AREA NETWORKS HAVING NON-BLOCKING NETWORK SWITCHES CONFIGURED FOR SWITCHING DATA PACKETS BETWEEN SUBNETWORKS BASED ON MANAGEMENT POLICIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09591085
|
Filing Dt:
|
06/09/2000
|
|
Title:
|
SYSTEM AND METHOD FOR ILLUMINATING A SEMICONDUCTOR PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09591163
|
Filing Dt:
|
06/09/2000
|
|
Title:
|
SYSTEM AND METHOD FOR ILLUMINATING A SEMICONDUCTOR PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2002
|
Application #:
|
09591967
|
Filing Dt:
|
06/12/2000
|
|
Title:
|
METHOD OF ENDPOINTING PLASMA STRIP PROCESS BY MEASURING WAFER TEMPERATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09592124
|
Filing Dt:
|
06/12/2000
|
|
Title:
|
METHOD AND SYSTEM FOR FORMING A LONG CHANNEL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09592164
|
Filing Dt:
|
06/13/2000
|
|
Title:
|
Method of electroless ag layer formation for cu interconnects
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09592275
|
Filing Dt:
|
06/12/2000
|
|
Title:
|
TOP INFRARED HEATING FOR BONDING OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09593669
|
Filing Dt:
|
06/14/2000
|
|
Title:
|
Method of manufacturing a semiconductor device having copper interconnects
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
09593912
|
Filing Dt:
|
06/14/2000
|
|
Title:
|
SYSTEM AND METHOD FOR INTERFACING BETWEEN A MEDIA ACCESS CONTROLLER AND A NUMBER OF PHYSICAL LAYER DEVICES USING TIME DIVISION MULTIPLEXING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09594232
|
Filing Dt:
|
06/14/2000
|
|
Title:
|
SYSTEM AND METHOD FOR INTERFACING BETWEEN A MEDIA ACCESS CONTROLLER AND A NUMBER OF PHYSICAL LAYER DEVICES USING DATA ADDRESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09594604
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
ARRANGEMENT FOR IDENTIFYING DATA PACKET TYPES FROM MULTIPLE PROTOCOL FORMATS ON A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09594606
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
APPARATUS AND METHOD FOR STORING MIN TERMS IN NETWORK SWITCH PORT MEMORY FOR ACCESS AND COMPACTNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
09594607
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
FRAME IDENTIFIER FOR IDENTIFYING LAYER 2 DATA PACKET TYPES FOR UPPER LAYER PACKET CLASSIFICATION IN A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
09594608
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
APPARATUS AND METHOD FOR SPECIFYING SUCCESSIVE BYTE LOCATIONS FOR EVALUATING DATA PACKETS IN A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
09595039
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
PROGRAMMABLE BI-DIRECTIONAL MII TESTING METHODOLOGY AND DEVICE INCLUDING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09595597
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
TRANSLATION LOOKASIDE BUFFER FLUSH FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09595598
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING BUS ACCESS FOR BUS AGENTS HAVING VARYING PRIORITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09596178
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
Method for developing ultra-thin resist films
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09596260
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
METHOD AND APPARATUS FOR INTERFACING A STATISTICAL PROCESS CONTROL SYSTEM WITH A MANUFACTURING PROCESS CONTROL FRAMEWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09596636
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
PROVIDING GLOBAL TRANSLATIONS WITH ADDRESS SPACE NUMBERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09596820
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
GATE ETCH PROCESS WITH EXTENDED CD TRIM CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09596954
|
Filing Dt:
|
06/16/2000
|
|
Title:
|
MODIFICATION OF MASK LAYOUT DATA TO IMPROVE MASK FIDELITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2002
|
Application #:
|
09596993
|
Filing Dt:
|
06/20/2000
|
|
Title:
|
Hard mask for integrated circuit fabrication
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09597098
|
Filing Dt:
|
06/20/2000
|
|
Title:
|
Process utilizing a cap layer optimized to reduce gate line over-melt
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
09597370
|
Filing Dt:
|
06/19/2000
|
|
Title:
|
METHOD OF TESTING A NETWORK DEVICE THROUGH A MEDIUM INDEPENDENT INTERFACE (MII)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09597623
|
Filing Dt:
|
06/20/2000
|
|
Title:
|
Dual amorphization process optimized to reduce gate line over-melt
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09598531
|
Filing Dt:
|
06/21/2000
|
|
Title:
|
Method of forming ultra thin gate dielectric for high performance semiconductor devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09599530
|
Filing Dt:
|
06/23/2000
|
|
Title:
|
METHOD TO REDUCE OCCURRENCES OF FILLET CRACKING IN FLIP-CHIP UNDERFILL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09602045
|
Filing Dt:
|
06/23/2000
|
|
Title:
|
SYSTEM FOR CONTROLLING TRANSISTOR SPACER WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09602443
|
Filing Dt:
|
06/23/2000
|
|
Title:
|
LOW ANGLE SOLVENT DISPENSE NOZZLE DESIGN FOR FRONT-SIDE EDGE BEAD REMOVAL IN PHOTOLITHOGRAPHY RESIST PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09602859
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
AUTOMATED PROTECTION OF IC DEVICES FROM EOS (ELECTRO OVER STRESS) DAMAGE DUE TO AN UNDESIRED DC TRANSIENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09604267
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED SYSTEM LEVEL TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09604547
|
Filing Dt:
|
06/26/2000
|
|
Title:
|
METHOD OF FABRICATING A SHALLOW TRENCH ISOLATION STRUCTURE WITH REDUCED TOPOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09604818
|
Filing Dt:
|
06/28/2000
|
|
Title:
|
MECHANISM TO CLEAR MAC ADDRESS FROM ETHERNET SWITCH ADDRESS TABLE TO ENABLE NETWORK LINK FAIL-OVER ACROSS TWO NETWORK SEGMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09605592
|
Filing Dt:
|
06/28/2000
|
|
Title:
|
PROCESSOR IC PERFORMANCE METRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09605856
|
Filing Dt:
|
06/29/2000
|
|
Title:
|
SAW BLADE FOR CUTTING INTEGRATED CIRCUIT PACKAGE BOARDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09605920
|
Filing Dt:
|
06/28/2000
|
|
Title:
|
NOVEL CAPACITIVELY COUPLED DTMOS ON SOI
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09606651
|
Filing Dt:
|
06/28/2000
|
|
Title:
|
Method of creating selectively thin silicon/oxide for making fuly and partially depleted SOI on same waffer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09606752
|
Filing Dt:
|
06/29/2000
|
|
Title:
|
IC DEVICE BURN-IN METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09607150
|
Filing Dt:
|
06/29/2000
|
|
Title:
|
DETECTING DIE SPEED VARIATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09607629
|
Filing Dt:
|
06/30/2000
|
|
Title:
|
SELECTIVELY THIN SILICON FILM FOR CREATING FULLY AND PARTIALLY DEPLETED SOI ON SAME WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
|
Application #:
|
09610865
|
Filing Dt:
|
07/06/2000
|
|
Title:
|
Multi-layered pin grid array interposer apparatus and method for testing semiconductor devices having a non-pin grid array footprint
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09610867
|
Filing Dt:
|
07/06/2000
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
|
Title:
|
System level test socket
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09611701
|
Filing Dt:
|
07/08/2000
|
|
Title:
|
METHOD FOR REDUCING THE STEP HEIGHT OF SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09612589
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
Cool frame for protecting packaged electronic devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09612771
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
FIELD EFFECT TRANSISTOR WITH ELECTRICALLY INDUCED DRAIN AND SOURCE EXTENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09612781
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
09613008
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
REAL TIME CLOCK (RTC) HAVING SEVERAL HIGHLY DESIRABLE TIMEKEEPING DEPENDABILITY AND SECURITY ATTRIBUTES, AND METHODS FOR ACCESSING A REGISTER THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09613009
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
METHODS FOR PROVIDING ESTIMATES OF THE CURRENT TIME IN A COMPUTER SYSTEM INCLUDING A LOCAL TIME SOURCE HAVING ONE OF SEVERAL POSSIBLE LEVELS OF TRUST WITH REGARD TO TIMEKEEPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
09613011
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
MULTILEVEL NETWORK FOR DISTRIBUTING TRUSTED TIME AND DELEGATING LEVELS OF TRUST REGARDING TIMEKEEPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09613087
|
Filing Dt:
|
07/10/2000
|
|
Title:
|
FABRICATION OF A NOTCHED GATE STRUCTURE FOR A FIELD EFFECT TRANSISTOR USING A SINGLE PATTERNING AND ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09614300
|
Filing Dt:
|
07/12/2000
|
|
Title:
|
SYSTEM AND METHOD FOR ADHESION IMPROVEMENT AT AN INTERFACE BETWEEN FLUORINE DOPED SILICON OXIDE AND TANTALUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09614666
|
Filing Dt:
|
07/12/2000
|
|
Title:
|
FEEDBACK CONTROL OF STRIP TIME TO REDUCE POST STRIP CRITICAL DIMENSION VARIATION IN A TRANSISTOR GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09614817
|
Filing Dt:
|
07/12/2000
|
|
Title:
|
Spring contact for providing high current power to an integrated circuit
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09614894
|
Filing Dt:
|
07/12/2000
|
|
Title:
|
SELF-ALIGNED SOI DEVICE WITH BODY CONTACT AND NISI2 GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09615481
|
Filing Dt:
|
07/13/2000
|
|
Title:
|
METHOD AND APPARATUS FOR MODELING THICKNESS PROFILES AND CONTROLLING SUBSEQUENT ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
09616473
|
Filing Dt:
|
07/14/2000
|
|
Title:
|
METHOD AND SYSTEM FOR POLISHING A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09617104
|
Filing Dt:
|
07/14/2000
|
|
Title:
|
METHOD AND APPARATUS FOR JET PRINTING A FLUX PATTERN SELECTIVELY ON FLIP-CHIP BUMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09617158
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
DELIBERATE VOID IN INNERLAYER DIELECTRIC GAPFILL TO REDUCE DIELECTRIC CONSTANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09617374
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
LOW K ILD PROCESS BY REMOVABLE ILD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09618057
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
IN-BAND MANAGEMENT OF A STACKED GROUP OF SWITCHES BY A SINGLE CPU
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
09618059
|
Filing Dt:
|
07/17/2000
|
|
Title:
|
APPARATUS AND METHOD FOR BUFFER-FREE EVALUATION OF PACKET DATA BYTES WITH MULTIPLE MIN TERMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
09618291
|
Filing Dt:
|
07/18/2000
|
|
Title:
|
FLOW CONTROL ARRANGEMENT IN A NETWORK SWITCH BASED ON PRIORITY TRAFFIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09619789
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
Damascene T-gate using a relacs flow
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09619836
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
Damascene T-gate using a spacer flow
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09619838
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
Capacitively coupled DTMOS on SOI for multiple devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09619984
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
Method and system for dust and fume removal in laser marking machines
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09620145
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
T-gate formation using modified damascene processing with two masks
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09620300
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
T-GATE FORMATION USING A MODIFIED CONVENTIONAL POLY PROCESS
|
|
