|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09620981
|
Filing Dt:
|
07/21/2000
|
|
Title:
|
FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09621156
|
Filing Dt:
|
07/21/2000
|
|
Title:
|
METHOD OF POROUS DIELECTRIC FORMATION WITH ANODIC TEMPLATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09621290
|
Filing Dt:
|
07/20/2000
|
|
Title:
|
ARGON IMPLANTATION AFTER SILICIDATION FOR IMPROVED FLOATING-BODY EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09621931
|
Filing Dt:
|
07/24/2000
|
|
Title:
|
A SYSTEM AND METHOD FOR SELECTING BETWEEN A VOLTAGE SPECIFIED BY A PROCESSOR AND AN ALTERNATE VOLTAGE TO BE SUPPLIED TO HE PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09624494
|
Filing Dt:
|
07/24/2000
|
|
Title:
|
DYNAMIC PULSE WIDTH PROGRAMMING OF PROGRAMMABLE LOGIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09624656
|
Filing Dt:
|
07/25/2000
|
|
Title:
|
METHOD OF CONTROLLING SHEET RESISTANCE OF METAL SILICIDE REGIONS BY CONTROLLING THE SALICIDE STRIP TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09624841
|
Filing Dt:
|
07/25/2000
|
|
Title:
|
INSTRUCTION QUEUE EVALUATING DEPENDENCY VECTOR IN PORTIONS DURING DIFFERENT CLOCK PHASES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
09625140
|
Filing Dt:
|
07/25/2000
|
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING FINAL CRITICAL DIMENSION CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09625367
|
Filing Dt:
|
07/26/2000
|
|
Title:
|
EDGE SEAL RING FOR COPPER DAMASCENE PROCESS AND METHOD FOR FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09625587
|
Filing Dt:
|
07/26/2000
|
|
Title:
|
Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09625620
|
Filing Dt:
|
07/26/2000
|
|
Title:
|
APPARATUS AND METHOD FOR VERIFYING PROCESS INTEGRITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09625711
|
Filing Dt:
|
07/25/2000
|
|
Title:
|
METHOD AND SYSTEM FOR CONTROLLING THE PLASMA TREATMENT OF A TITANIUM NITRIDE LAYER FORMED BY A CHEMICAL VAPOR DEPOSITION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09626454
|
Filing Dt:
|
07/26/2000
|
|
Title:
|
Method of forming capped copper interconnects with reduced hillocks
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09626455
|
Filing Dt:
|
07/26/2000
|
|
Title:
|
METHOD OF FORMING COPPER INTERCONNECT CAPPING LAYERS WITH IMPROVED INTERFACE AND ADHESION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09626556
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
Processor configured to map logical register numbers to physical register numbers using virtual register numbers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
09626604
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
METHOD AND APPARATUS FOR REMOVING SPECULATIVE MEMORY ACCESSES FROM A MEMORY ACCESS QUEUE FOR ISSUANCE TO MEMORY OR DISCARDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09626615
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A PRIVILEGE-PARTITIONED ADDRESS SPACE WITH A FIXED SET OF ATTRIBUTES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09626666
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
METHOD OF REDUCING PHOTORESIST SHADOWING DURING ANGLED IMPLANTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09626668
|
Filing Dt:
|
07/27/2000
|
|
Title:
|
METHOD FOR FORMING VERTICAL PROFILE OF POLYSILICON GATE ELECTRODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09627436
|
Filing Dt:
|
07/28/2000
|
|
Title:
|
DETERMINATION OF FLUX COVERAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
09627874
|
Filing Dt:
|
07/28/2000
|
|
Title:
|
METHOD AND APPARATUS FOR MONITORING CONSUMABLE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09628382
|
Filing Dt:
|
08/01/2000
|
|
Title:
|
METHOD FOR MAKING RAISED SOURCE/DRAIN REGIONS USING LASER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09628822
|
Filing Dt:
|
07/31/2000
|
|
Title:
|
REDUCTION OF VIA ETCH CHARGING DAMAGE THROUGH THE USE OF A CONDUCTING HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09629883
|
Filing Dt:
|
08/01/2000
|
|
Title:
|
PREVENTION OF DOPANT OUT-DIFFUSION DURING SILICIDATION AND JUNCTION FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09629925
|
Filing Dt:
|
07/31/2000
|
|
Title:
|
SYSTEM MANAGEMENT BUS ADDRESS RESOLUTION PROTOCOL PROXY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09632499
|
Filing Dt:
|
08/03/2000
|
|
Title:
|
Method and system for package orientation checking for laser mark operations
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09633208
|
Filing Dt:
|
08/07/2000
|
|
Title:
|
MULTIPLE ACTIVE LAYER STRUCTURE AND A METHOD OF MAKING SUCH A STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09633620
|
Filing Dt:
|
08/07/2000
|
|
Title:
|
Electroplating multi-trace circuit board substrates using single tie bar
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09633930
|
Filing Dt:
|
08/08/2000
|
|
Title:
|
METHOD AND APPARATUS FOR DYNAMIC SAMPLING OF A PRODUCTION LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09633960
|
Filing Dt:
|
08/08/2000
|
|
Title:
|
SILICON WAFER INCLUDING BOTH BULK AND SOI REGIONS AND METHOD FOR FORMING SAME ON A BULK SILICON WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09633963
|
Filing Dt:
|
08/08/2000
|
|
Title:
|
DEVICE AND METHOD FOR I/Q MODULATION, FREQUENCY TRANSLATION AND UPSAMPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09634990
|
Filing Dt:
|
08/08/2000
|
|
Title:
|
Shallow trench isolation formation with two source/drain masks and simplified planarization mask
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09635332
|
Filing Dt:
|
08/09/2000
|
|
Title:
|
INTEGRATED CIRCUIT CARRIER ARRANGEMENT FOR REDUCING NON-UNIFORMITY IN CURRENT FLOW THROUGH POWER PINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09636239
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR TRANSISTOR WITH RECESSED SOURCE AND DRAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09636273
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
METHOD FOR FABRICATING T-SHAPED TRANSISTOR GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09636515
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
BOAT FOR CLEANING BALL GRID ARRAY PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09636516
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
Slurry for chemical mechanical polishing of copper
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
09637015
|
Filing Dt:
|
08/14/2000
|
|
Title:
|
APPARATUS AND METHOD FOR IDENTIFYING DATA PACKET AT WIRE RATE ON A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09637100
|
Filing Dt:
|
08/10/2000
|
|
Title:
|
LOT SPECIFIC PROCESS DESIGN METHODOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
09637710
|
Filing Dt:
|
08/11/2000
|
|
Title:
|
SYSTEM AND METHOD FOR SYNCHRONIZING A SKIP PATTERN AND INITIALIZING A CLOCK FORWARDING INTERFACE IN A MULTIPLE-CLOCK SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09639380
|
Filing Dt:
|
08/15/2000
|
|
Title:
|
SELF-AMORPHIZED REGIONS FOR TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09639799
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
METHOD OF SELECTIVELY CONTROLLING CONTACT RESISTANCE BY CONTROLLING IMPURITY CONCENTRATION AND SILICIDE THICKNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09639812
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
Method and apparatus for improved planarity metallization by electroplating and CMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09640081
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
AVOIDING FLUORINE CONTAMINATION OF COPPER INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09640177
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
LASER TAILORING RETROGRADE CHANNEL PROFILE IN SURFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09640186
|
Filing Dt:
|
08/17/2000
|
|
Title:
|
NON-UNIFORM CHANNEL PROFILE VIA ENHANCED DIFFUSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09641436
|
Filing Dt:
|
08/18/2000
|
|
Title:
|
Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09641727
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
LOW RESISTANCE COMPOSITE CONTACT STRUCTURE UTILIZING A REACTION BARRIER LAYER UNDER A METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09642831
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
DETECTION OF FLUX RESIDUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09642832
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
Determination of flux prior to package assembly
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
09642959
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
OPTIMIZATION OF OPC DESIGN FACTORS UTILIZING AN ADVANCED ALGORITHM ON A LOW VOLTAGE CD-SEM SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09643072
|
Filing Dt:
|
08/21/2000
|
|
Title:
|
VERTICAL CACHE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09643343
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
Y-gate formation using damascene processing
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
09643531
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
SUPER CRITICAL DRYING OF LOW K MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09643591
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
RECORDER BUFFER CONFIGURED TO ALLOCATE STORGE FOR INSTRUCTION RESULTS CORRESPONDING TO PREDEFINED MAXIMUM NUMBER OF CONCURRENTLY RECEIVABLE INSTRUCTIONS INDEPENDENT OF A NUMBER OF INSTRUCTIONS RECEIVED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09643611
|
Filing Dt:
|
08/22/2000
|
|
Title:
|
T OR T/Y GATE FORMATION USING TRIM ETCH PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
09643847
|
Filing Dt:
|
08/23/2000
|
|
Title:
|
DESIGN TOOL FOR INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
09644464
|
Filing Dt:
|
08/23/2000
|
|
Title:
|
NETWORK TRANSMITTER WITH DATA FRAME PRIORITY MANAGEMENT FOR DATA TRANSMISSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09645923
|
Filing Dt:
|
08/24/2000
|
|
Title:
|
METHOD AND SYSTEM TO REDUCE SWITCHING SIGNAL NOISE ON A DEVICE AND A DEVICE AS RESULT THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09650538
|
Filing Dt:
|
08/30/2000
|
|
Title:
|
CVD PLASMA PROCESS TO FILL CONTACT HOLE IN DAMASCENE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09651891
|
Filing Dt:
|
08/30/2000
|
|
Title:
|
SELECTIVE EPITAXY TO REDUCE GATE/GATE DIELECTRIC INTERFACE ROUGHNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09651893
|
Filing Dt:
|
08/30/2000
|
|
Title:
|
INTEGRATED CIRCUIT PACKAGE INCORPORATING CAMOUFLAGED PROGRAMMABLE ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
09652647
|
Filing Dt:
|
08/31/2000
|
|
Title:
|
SYSTEM AND METHOD FOR MONITOING AND CONTROLLING A POWER-MANAGEABLE RESOURCE BASED UPON ACTIVITIES OF A PLURALITY OF DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09653435
|
Filing Dt:
|
09/01/2000
|
|
Title:
|
RESIST REMOVAL MONITORING BY RAMAN SPECTROSCOPY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09655700
|
Filing Dt:
|
09/06/2000
|
|
Title:
|
FILLING AN INTERCONNECT OPENING WITH DIFFERENT TYPES OF ALLOYS TO ENHANCE INTERCONNECT RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09656437
|
Filing Dt:
|
09/06/2000
|
|
Title:
|
H2 DIFFUSION BARRIER FORMATION BY NITROGEN INCORPORATION IN OXIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09660396
|
Filing Dt:
|
09/12/2000
|
|
Title:
|
PASSIVATION OF SEMICONDUCTOR DEVICE SURFACES USING AN IODINE/ETHANOL SOLUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09660723
|
Filing Dt:
|
09/13/2000
|
|
Title:
|
DRY ISOTROPIC REMOVAL OF INORGANIC ANTI-REFLECTIVE COATING AFTER POLY GATE ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09660724
|
Filing Dt:
|
09/13/2000
|
|
Title:
|
Isotropic resistor protect etch to aid in residue removal
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09661041
|
Filing Dt:
|
09/14/2000
|
|
Title:
|
FABRICATION OF METAL OXIDE STRUCTURE FOR A GATE DIELECTRIC OF A FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09661694
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Filing Dt:
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09/14/2000
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Title:
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METHOD AND APPARATUS FOR PARSING EVENT LOGS TO DETERMINE TOOL OPERABILITY
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09662016
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Filing Dt:
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09/14/2000
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Title:
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MEASUREMENT METHOD OF ZERNIKE COMA ABERRATION COEFFICIENT
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09664238
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Filing Dt:
|
09/18/2000
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Title:
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METHOD OF FORMING CONDUCTIVE INTERCONNECTIONS ON AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
|
05/14/2002
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Application #:
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09664714
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Filing Dt:
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09/19/2000
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Title:
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PASSIVATION OF SIDEWALL SPACERS USING OZONATED WATER
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Patent #:
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Issue Dt:
|
12/11/2001
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Application #:
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09666088
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Filing Dt:
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09/21/2000
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Title:
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Self-aligned damascene gate formation with low gate resistance
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Patent #:
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Issue Dt:
|
03/18/2003
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Application #:
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09666341
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Filing Dt:
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09/21/2000
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Title:
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GRINDING ARRANGEMENT AND METHOD FOR REAL-TIME VIEWING OF SAMPLES DURING CROSS-SECTIONING
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Patent #:
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Issue Dt:
|
08/17/2004
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Application #:
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09667382
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Filing Dt:
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09/22/2000
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Title:
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COUPLING DEVICE CONNECTING MULTIPLE POTS LINES IN AN HPNA ENVIRONMENT
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Patent #:
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Issue Dt:
|
04/09/2002
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Application #:
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09667573
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Filing Dt:
|
09/22/2000
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Title:
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ACTIVE MASK EXPOSURE COMPENSATION OF UNDERLYING NITRIDE THICKNESS VARIATION TO REDUCE CRITICAL DIMENSION (CD) VARIATION
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Patent #:
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Issue Dt:
|
02/04/2003
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Application #:
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09667600
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Filing Dt:
|
09/22/2000
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Title:
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METHOD OF INHIBITING LATERAL DIFFUSION BETWEEN ADJACENT WELLS BY INTRODUCING CARBON OR FLUORINE IONS INTO BOTTOM OF STI GROOVE
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|
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Patent #:
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Issue Dt:
|
02/05/2002
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Application #:
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09667601
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Filing Dt:
|
09/22/2000
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Title:
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Removable spacer technology using ion implantation for forming asymmetric MOS transistors
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|
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Patent #:
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Issue Dt:
|
01/08/2002
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Application #:
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09667602
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Filing Dt:
|
09/22/2000
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Title:
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Use of knocked-on oxygen atoms for reduction of transient enhanced diffusion
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|
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Patent #:
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Issue Dt:
|
07/23/2002
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Application #:
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09667685
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Filing Dt:
|
09/22/2000
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|
Title:
|
RETROGRADE WELL STRUCTURE FORMATION BY NITROGEN IMPLANTATION
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|
|
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Patent #:
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|
Issue Dt:
|
12/10/2002
|
Application #:
|
09668443
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Filing Dt:
|
09/22/2000
|
|
Title:
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METHOD OF FABRICATING CONDUCTOR STRUCTURES WITH METAL COMB BRIDGING AVOIDANCE
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Patent #:
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|
Issue Dt:
|
02/11/2003
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Application #:
|
09671944
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Filing Dt:
|
09/27/2000
|
|
Title:
|
SUPERCONDUCTOR BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
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|
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Patent #:
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|
Issue Dt:
|
10/05/2004
|
Application #:
|
09675292
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Filing Dt:
|
09/29/2000
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|
Title:
|
METHOD AND APPARATUS FOR DATA TRANSMISSION OVER AN AC-97 PROTOCOL LINK
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|
|
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Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
|
09675534
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Filing Dt:
|
09/29/2000
|
|
Title:
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METHOD AND APPARATUS FOR IMPROVING SIGNAL TO NOISE RATIO OF AN AERIAL IMAGE MONITOR
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Patent #:
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|
Issue Dt:
|
08/08/2006
|
Application #:
|
09676197
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Filing Dt:
|
09/28/2000
|
|
Title:
|
METHOD OF FORMING A GATE ELECTRODE ON A SEMICONDUCTOR DEVICE AND A DEVICE INCORPORATING SAME
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|
|
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Patent #:
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|
Issue Dt:
|
08/21/2001
|
Application #:
|
09677955
|
Filing Dt:
|
10/02/2000
|
|
Title:
|
Method for detecting sloped contact holes using a critical-dimension waveform
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|
|
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Patent #:
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|
Issue Dt:
|
07/02/2002
|
Application #:
|
09678503
|
Filing Dt:
|
10/02/2000
|
|
Title:
|
PLATING SYSTEM WITH REMOTE SECONDARY ANODE FOR SEMICONDUCTOR MANUFACTURING
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|
|
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Patent #:
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|
Issue Dt:
|
08/15/2006
|
Application #:
|
09678637
|
Filing Dt:
|
10/03/2000
|
|
Title:
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AUTOMATED MATERIAL HANDLING SYSTEM FOR A MANUFACTURING FACILITY DIVIDED INTO SEPARATE FABRICATION AREAS
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|
|
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Patent #:
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|
Issue Dt:
|
12/31/2002
|
Application #:
|
09678946
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Filing Dt:
|
10/03/2000
|
|
Title:
|
ATOMIC LAYER BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
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|
|
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Patent #:
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Issue Dt:
|
10/15/2002
|
Application #:
|
09679369
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
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|
|
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Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09679370
|
Filing Dt:
|
10/05/2000
|
|
Title:
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DOUBLE SILICIDE FORMATION IN POLYSILICON GATE WITHOUT SILICIDE IN SOURCE/DRAIN EXTENSIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/19/2002
|
Application #:
|
09679373
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
NITROGEN OXIDE PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/07/2002
|
Application #:
|
09679374
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
NH3/N2-PLASMA TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09679375
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
COMPOSITE SILICON NITRIDE SIDEWALL SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09679872
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09679880
|
Filing Dt:
|
10/05/2000
|
|
Title:
|
HDP TREATMENT FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09685974
|
Filing Dt:
|
10/10/2000
|
|
Title:
|
METHOD FOR FORMING POLYSILICON-GERMANIUM GATE IN CMOS TRANSISTOR AND DEVICE MADE THEREBY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09686352
|
Filing Dt:
|
10/10/2000
|
|
Title:
|
METHOD OF FABRICATING ULTRA SHALLOW JUNCTION CMOS TRANSISTORS WITH NITRIDE DISPOSABLE SPACER
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|
