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Patent #:
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|
Issue Dt:
|
04/30/2002
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Application #:
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09686476
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Filing Dt:
|
10/10/2000
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Title:
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SEMICONDUCTOR WITH LATERALLY NON-UNIFORM CHANNEL DOPING PROFILE AND MANUFACTURING METHOD THEREFOR
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Patent #:
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|
Issue Dt:
|
11/09/2004
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Application #:
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09686593
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Filing Dt:
|
10/10/2000
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Title:
|
METHOD FOR AGING TABLE ENTRIES IN A TABLE SUPPORTING MULTI-KEY SEARCHES
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Patent #:
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|
Issue Dt:
|
01/14/2003
|
Application #:
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09689063
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Filing Dt:
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10/12/2000
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Title:
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VERTICAL DOUBLE GATE TRANSISTOR STRUCTURE
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Patent #:
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Issue Dt:
|
08/26/2003
|
Application #:
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09689403
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Filing Dt:
|
10/12/2000
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|
Title:
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DEVICES AND METHODS FOR INTEGRATED CIRCUIT CONTAINER RELEASE
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|
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|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09690073
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Filing Dt:
|
10/16/2000
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|
Title:
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Field effect transistor with spacers that are removable with preservation of the gate dielectric
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|
Patent #:
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|
Issue Dt:
|
04/29/2003
|
Application #:
|
09690704
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Filing Dt:
|
10/16/2000
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Title:
|
CHEMICAL-MECHANICAL POLISHING PAD CONDITIONING SYSTEM AND METHOD
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Patent #:
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|
Issue Dt:
|
08/27/2002
|
Application #:
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09691180
|
Filing Dt:
|
10/19/2000
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|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON AND SILICIDE FOR CMOS DEVICES AND METHOD OF MAKING THE SAME WITH A REPLACEMENT GATE PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09691181
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH CVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09691188
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH CVD AMORPHOUS SILICON LAYER AND A BARRIER LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/21/2002
|
Application #:
|
09691224
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Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
09691226
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER HAVING IMPLANTED DOPANTS FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/04/2003
|
Application #:
|
09691227
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH PVD AMORPHOUS SILICON LAYER AND BARRIER LAYER FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09691228
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
High dielectric constant materials as gate dielectrics
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|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09691259
|
Filing Dt:
|
10/19/2000
|
|
Title:
|
METAL GATE WITH CVD AMORPHOUS SILICON LAYER AND SILICIDE FOR CMOS DEVICES AND METHOD OF MAKING WITH A REPLACEMENT GATE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
09691377
|
Filing Dt:
|
10/18/2000
|
|
Title:
|
INDIRECT ADDRESSING METHOD AND DEVICE INCORPORATING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
09691913
|
Filing Dt:
|
10/20/2000
|
|
Title:
|
ARRANGEMENT FOR CONVERTING BETWEEN A MEDIA INDEPENDENT INTERFACE AND A TWISTED PAIR MEDIUM USING A FIELD PROGRAMMABLE GATE ARRAY
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|
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Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
09694523
|
Filing Dt:
|
10/23/2000
|
|
Title:
|
CONSTANT-CURRENT VDDQ TESTING OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09695495
|
Filing Dt:
|
10/24/2000
|
|
Title:
|
METHOD OF USING CONTROL MODELS FOR DATA COMPRESSION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09696049
|
Filing Dt:
|
10/26/2000
|
|
Title:
|
Pattern-block flux deposition
|
|
|
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|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
09696744
|
Filing Dt:
|
10/26/2000
|
|
Title:
|
METHOD FOR PROFILING SEMICONDUCTOR DEVICE JUNCTIONS USING A VOLTAGE CONTRAST SCANNING ELECTRON MICROSCOPE
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|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09702220
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
PREDECODING MULTIPLE INSTRUCTIONS AS ONE COMBINED INSTRUCTION AND DETECTING BRANCH TO ONE OF THE INSTRUCTIONS
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|
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|
Patent #:
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|
Issue Dt:
|
08/27/2002
|
Application #:
|
09703092
|
Filing Dt:
|
10/31/2000
|
|
Title:
|
THIN RESIST WITH TRANSITION METAL HARD MASK FOR VIA ETCH APPLICATION
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09703512
|
Filing Dt:
|
10/30/2000
|
|
Title:
|
TRANSISTOR WITH ELECTRICALLY INDUCED SOURCE/DRAIN EXTENSIONS
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|
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|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09703513
|
Filing Dt:
|
10/31/2000
|
|
Title:
|
Antireflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09705121
|
Filing Dt:
|
11/01/2000
|
|
Title:
|
VOID ELIMINATING SEED LAYER AND CONDUCTOR CORE INTEGRATED CIRCUIT INTERCONNECTS
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|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09705938
|
Filing Dt:
|
11/03/2000
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING GRAIN GROWTH ROUGHENING IN CONDUCTIVE STACKS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09706498
|
Filing Dt:
|
11/03/2000
|
|
Title:
|
POLISHED HARD MASK PROCESS FOR CONDUCTOR LAYER PATTERNING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/15/2003
|
Application #:
|
09707214
|
Filing Dt:
|
11/06/2000
|
|
Title:
|
SELF-ALIGNED/MASKLESS REVERSE ETCH PROCESS USING AN INORGANIC FILM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09708104
|
Filing Dt:
|
11/03/2000
|
|
Title:
|
Chemical resist thickness reduction process
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09708216
|
Filing Dt:
|
11/07/2000
|
|
Title:
|
PROCESSOR CONFIGURED TO PREDECODE RELATIVE CONTROL TRANSFER INSTRUCTIONS AND REPLACE DISPLACEMENTS THEREIN WITH A TARGET ADDRESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09709827
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Filing Dt:
|
11/10/2000
|
|
Title:
|
SYSTEM USING HOT AND COLD FLUIDS TO HEAT AND COOL PLATE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/26/2002
|
Application #:
|
09709974
|
Filing Dt:
|
11/10/2000
|
|
Title:
|
SYSTEM AND METHOD TO FACILITATE REMOVAL OF DEFECTS FROM A SUBSTRATE
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|
|
|
Patent #:
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|
Issue Dt:
|
05/28/2002
|
Application #:
|
09711328
|
Filing Dt:
|
11/13/2000
|
|
Title:
|
Self-aligned double gate silicon-on-insulator (SOI) device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09711401
|
Filing Dt:
|
11/13/2000
|
|
Title:
|
METHOD OF MAKING HIGH PERFORMANCE TRANSISTOR WITH A REDUCED WIDTH GATE ELECTRODE AND DEVICE COMPRISING SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09711445
|
Filing Dt:
|
11/13/2000
|
|
Title:
|
METHOD OF MAKING A SELF-ALIGNED TRIPLE GATE SILICON-ON-INSULATOR DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09712320
|
Filing Dt:
|
11/14/2000
|
|
Title:
|
SOI DEVICE WITH SELF-ALIGNED SELECTIVE DAMAGE IMPLANT, AND METHOD
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|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09712646
|
Filing Dt:
|
11/14/2000
|
|
Title:
|
METHOD AND APPARATUS FOR SIMULTANEOUS ONLINE ACCESS OF VOLUME-MANAGED DATA STORAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09712995
|
Filing Dt:
|
11/15/2000
|
|
Title:
|
METHOD FOR FORMING FIELD EFFECT TRANSISTOR WITH SILICIDES OF DIFFERENT THICKNESS AND OF DIFFERENT MATERIALS FOR THE SOURCE/DRAIN AND THE GATE
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/15/2003
|
Application #:
|
09713313
|
Filing Dt:
|
11/16/2000
|
|
Title:
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METHOD OF PROMOTING VOID FREE COPPER INTERCONNECTS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/24/2004
|
Application #:
|
09715433
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
METHOD TO SUPPORT VLANS ON A PHONELINE NETWORK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09715467
|
Filing Dt:
|
11/15/2000
|
|
Title:
|
Dependency table for reducing dependency checking hardware
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
05/17/2005
|
Application #:
|
09715997
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
COMBINING VLAN TAGGING WITH OTHER NETWORK PROTOCOLS ALLOWS A USER TO TRANSFER DATA ON A NETWORK WITH ENHANCED SECURITY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09716215
|
Filing Dt:
|
11/21/2000
|
|
Title:
|
Bright field image reversal for contact hole patterning
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
08/23/2005
|
Application #:
|
09716854
|
Filing Dt:
|
11/17/2000
|
|
Title:
|
METHOD TO SELECT DYNAMICALLY BETWEEN MACS OF NETWORK DEVICE DEPENDING ON NETWORK TOPOLOGY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09723485
|
Filing Dt:
|
11/28/2000
|
|
Title:
|
METHOD AND APPARATUS FOR DETECTING VOLTAGE CONTRAST IN A SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09723553
|
Filing Dt:
|
11/27/2000
|
|
Title:
|
Mechanism for storing system level attributes in a translation lookaside buffer
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09723712
|
Filing Dt:
|
11/27/2000
|
|
Title:
|
VECTOR QUEUE STORING INSTRUCTION ORDERING DEPENDENCY BEYOND DATA DEPENDENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09723812
|
Filing Dt:
|
11/28/2000
|
|
Title:
|
Graded compound seed layers for semiconductors
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/25/2003
|
Application #:
|
09724134
|
Filing Dt:
|
11/28/2000
|
|
Title:
|
SYSTEMS AND METHODS FOR GENERATING HARDWARE DESCRIPTION CODE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/01/2005
|
Application #:
|
09725088
|
Filing Dt:
|
11/29/2000
|
|
Title:
|
ARRANGEMENT FOR VERIFYING RANDOMNESS OF TBEB ALGORITHM IN A MEDIA ACCESS CONTROLLER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09728312
|
Filing Dt:
|
11/30/2000
|
|
Title:
|
METHOD OF REDUCING CARBON, SULPHUR, AND OXYGEN IMPURITIES IN A CALCIUM-DOPED COPPER SURFACE AND SEMICONDUCTOR DEVICE THEREBY FORMED
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|
|
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|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09728314
|
Filing Dt:
|
11/30/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE FORMED BY CALCIUM DOPING A COPPER SURFACE USING A CHEMICAL SOLUTION
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|
|
|
Patent #:
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|
Issue Dt:
|
09/18/2001
|
Application #:
|
09728315
|
Filing Dt:
|
11/30/2000
|
|
Title:
|
Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed
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|
|
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|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09729295
|
Filing Dt:
|
12/04/2000
|
|
Title:
|
ELECTRON BEAM FLOOD EXPOSURE TECHNIQUE TO REDUCE THE CARBON CONTAMINATION
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|
|
|
Patent #:
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|
Issue Dt:
|
05/06/2003
|
Application #:
|
09729412
|
Filing Dt:
|
12/04/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONTROL OF SEMICONDUCTOR PROCESSING FOR REDUCING EFFECTS OF ENVIRONMENTAL EFFECTS
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|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
09729513
|
Filing Dt:
|
12/04/2000
|
|
Title:
|
USE OF SCANNING PROBE MICROSCOPE FOR DEFECT DETECTION AND REPAIR
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|
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|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09729699
|
Filing Dt:
|
12/06/2000
|
|
Publication #:
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|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
METHOD OF FORMING NICKEL SILICIDE USING A ONE-STEP RAPID THERMAL ANNEAL PROCESS AND BACKEND PROCESSING
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|
Patent #:
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|
Issue Dt:
|
11/05/2002
|
Application #:
|
09731031
|
Filing Dt:
|
12/07/2000
|
|
Publication #:
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|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
DAMASCENE NISI METAL GATE HIGH-K TRANSISTOR
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|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09731577
|
Filing Dt:
|
12/06/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
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RESIST TRIM PROCESS TO DEFINE SMALL OPENINGS IN DIELECTRIC LAYERS
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Patent #:
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|
Issue Dt:
|
02/15/2005
|
Application #:
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09731579
|
Filing Dt:
|
12/06/2000
|
|
Publication #:
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|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
METHOD FOR ADJUSTING RAPID THERMAL PROCESSING (RTP) RECIPE SETPOINTS BASED ON WAFER ELECTRICAL TEST (WET) PARAMETERS
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Patent #:
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|
Issue Dt:
|
05/14/2002
|
Application #:
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09733778
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Filing Dt:
|
12/08/2000
|
|
Title:
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METHOD OF SALICIDE FORMATION BY SILICIDING A GATE AREA PRIOR TO SLILICIDING A SOURCE AND DRAIN AREA
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Patent #:
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|
Issue Dt:
|
04/09/2002
|
Application #:
|
09734186
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Filing Dt:
|
12/12/2000
|
|
Title:
|
SILICIDE GATE TRANSISTORS
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|
|
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|
Patent #:
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|
Issue Dt:
|
01/29/2002
|
Application #:
|
09734189
|
Filing Dt:
|
12/12/2000
|
|
Title:
|
Damascene NiSi metal gate high-K transistor
|
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|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
09734207
|
Filing Dt:
|
12/12/2000
|
|
Title:
|
METAL SILICIDE GATE TRANSISTORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09735197
|
Filing Dt:
|
12/06/2000
|
|
Title:
|
PROCESSOR CONFIGURED TO FETCH A BRANCH TARGET ADDRESS FROM ONE SEVERAL INSTRUCTION CACHES RESPONSIVE TO A SIZE OF A DISPLACEMENT OF A CORRESPONDING BRANCH INSTRUCTION
|
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|
Patent #:
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|
Issue Dt:
|
02/26/2002
|
Application #:
|
09749112
|
Filing Dt:
|
12/26/2000
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2001
| | | | |
|
Title:
|
Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer
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|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
09749191
|
Filing Dt:
|
12/26/2000
|
|
Publication #:
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|
Pub Dt:
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01/22/2004
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Title:
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PREVENTION OF PRECIPITATION DEFECTS ON COPPER INTERCONNECTS DURING CPM BY USE OF SOLUTIONS CONTAINING ORGANIC COMPOUNDS WITH SILICA ADSORPTION AND COPPER CORROSION INHIBITING PROPERTIES
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09749293
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Filing Dt:
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12/27/2000
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Title:
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METHOD AND APPARATUS FOR USING LATENCY TIME AS A RUN-TO RUN CONTROL PARAMETER
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09750593
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Filing Dt:
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12/28/2000
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Publication #:
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Pub Dt:
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05/31/2001
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Title:
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Chemical-mechanical polishing slurry that reduces wafer defects
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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09750878
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Filing Dt:
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12/28/2000
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Title:
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METHOD TO SELECT TRANSMISSION RATE FOR NETWORK DEVICE
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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09752719
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Filing Dt:
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01/03/2001
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Publication #:
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Pub Dt:
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07/04/2002
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Title:
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METHOD AND APPARATUS FOR PERFORMING PRIORITY-BASED FLOW CONTROL
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09753705
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Filing Dt:
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01/03/2001
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Title:
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USE OF ENDPOINT SYSTEM TO MATCH INDIVIDUAL PROCESSING STATIONS WITHIN A TOOL
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09753809
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Filing Dt:
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01/03/2001
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Title:
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LOW DEFECT ORGANIC BARC COATING IN A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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09755008
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Filing Dt:
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01/05/2001
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Title:
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OPTICAL ANALYSIS OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09755012
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Filing Dt:
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01/05/2001
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Title:
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SOI DIE ANALYSIS OF CIRCUITRY LOGIC STATES VIA COUPLING THROUGH THE INSULATOR
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09757116
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Filing Dt:
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01/09/2001
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Title:
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APPARATUS FOR IMPROVING IMAGE DEPTH RESOLUTION IN A MAGNETIC FIELD IMAGING APPARATUS
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09757118
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Filing Dt:
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01/09/2001
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Title:
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Method and apparatus for measuring effects of packaging stresses of common IC electrical performance parameters at wafer sort
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09758487
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Filing Dt:
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01/10/2001
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Title:
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Apparatus and method for monitoring the performance of a microprocessor
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09760241
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Filing Dt:
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01/12/2001
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Title:
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CROSS-SHAPED RESIST DISPENSING SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09760421
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Filing Dt:
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01/11/2001
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Title:
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DIELECTRIC TREATMENT IN INTEGRATED CIRCUIT INTERCONNECTS
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09761953
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Filing Dt:
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01/17/2001
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Title:
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ULTRA-SHALLOW SOURCE/DRAIN EXTENSIONS
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09764132
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Filing Dt:
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01/19/2001
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Title:
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HEAT SINK GROUNDED TO A GROUNDED PACKAGE LID
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09764133
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Filing Dt:
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01/19/2001
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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MECHANICAL CLAMPER FOR HEATED SUBSTRATES AT DIE ATTACH
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09766481
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Filing Dt:
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01/19/2001
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Title:
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CIRCUIT FOR DETECTING A COOLING DEVICE IN A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09766737
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Filing Dt:
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01/22/2001
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Title:
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Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09766738
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Filing Dt:
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01/22/2001
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Title:
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METHOD FOR FORMING A THIN DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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09769890
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Filing Dt:
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01/25/2001
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Title:
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PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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09769982
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Filing Dt:
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01/25/2001
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Title:
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PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09770468
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Filing Dt:
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01/29/2001
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Title:
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ULTRA THIN ETCH STOP LAYER FOR DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09770469
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Filing Dt:
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01/29/2001
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Title:
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DIELECTRIC LAYER WITH TREATED TOP SURFACE FORMING AN ETCH STOP LAYER AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09770659
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Filing Dt:
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01/29/2001
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Title:
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ARRANGEMENT FOR TESTING PAUSE FRAME RESPONSE IN A NETWORK SWITCH
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09770730
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Filing Dt:
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01/26/2001
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Title:
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PELLICLE FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A PELLICLE
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09770733
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Filing Dt:
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01/26/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09771236
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Filing Dt:
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01/26/2001
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Title:
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PELLICLE FOR USE IN SMALL WAVELENGTH LITHOGRAPHY AND A METHOD FOR MAKING SUCH A PELLICLE USING A SILICON LAYER
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09771820
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Filing Dt:
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01/29/2001
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Title:
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PROCESS FOR REDUCING THE PITCH OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09771842
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Filing Dt:
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01/29/2001
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Title:
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PROCESS FOR REDUCING CRITICAL DIMENSIONS OF CONTACT HOLES, VIAS, AND TRENCH STRUCTURES IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09772423
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
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06/07/2001
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Title:
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NOISE ELIMINATION IN A USB CODEC
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09772577
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Filing Dt:
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01/30/2001
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Publication #:
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Pub Dt:
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08/01/2002
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Title:
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PHASE SHIFT MASK AND SYSTEM AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09772610
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Filing Dt:
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01/30/2001
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Title:
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SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09772649
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Filing Dt:
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01/30/2001
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Title:
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SOI SEMICONDUCTOR DEVICE OPENING IMPLANTATION GETTERING METHOD
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