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Patent #:
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Issue Dt:
|
03/25/2003
|
Application #:
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09772889
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Filing Dt:
|
01/31/2001
|
|
Title:
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PACKAGING SUBSTRATE COMPRISING STAGGERED VIAS
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Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
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09773906
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Filing Dt:
|
02/02/2001
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|
Title:
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PLASMA ETCH PROCESS FOR NONHOMOGENOUS FILM
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Patent #:
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|
Issue Dt:
|
12/31/2002
|
Application #:
|
09773954
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Filing Dt:
|
02/01/2001
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|
Title:
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OPTICAL TECHNIQUE TO DETECT ETCH PROCESS TERMINATION
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Patent #:
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|
Issue Dt:
|
08/19/2003
|
Application #:
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09773968
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Filing Dt:
|
02/01/2001
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|
Title:
|
DIFFERENTIAL WAVELENGTH INSPECTION SYSTEM
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|
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Patent #:
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|
Issue Dt:
|
04/30/2002
|
Application #:
|
09774138
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Filing Dt:
|
01/30/2001
|
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) TUNNELING JUNCTION TRANSISTOR SRAM CELL
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09774708
|
Filing Dt:
|
02/01/2001
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE WITH TREATMENT TO SACRIFICIAL STOP LAYER PRODUCING DIFFUSION TO AN ADJACENT LOW-K DIELECTRIC LAYER LOWERING THE CONSTANT
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|
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Patent #:
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|
Issue Dt:
|
04/02/2002
|
Application #:
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09774939
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Filing Dt:
|
01/31/2001
|
|
Title:
|
Dual gate process using self-assembled molecular layer
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Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09775016
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Filing Dt:
|
02/01/2001
|
|
Title:
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BARRIER FOR AND A METHOD OF REDUCING OUTGASSING FROM A PHOTORESIST MATERIAL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09775062
|
Filing Dt:
|
02/01/2001
|
|
Title:
|
PUPIL FILTERING FOR A LITHOGRAPHIC TOOL
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/06/2005
|
Application #:
|
09776080
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Filing Dt:
|
02/01/2001
|
|
Title:
|
TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM USING SIMD INSTRUCTIONS
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|
|
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Patent #:
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|
Issue Dt:
|
12/24/2002
|
Application #:
|
09776308
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Filing Dt:
|
02/02/2001
|
|
Title:
|
METHOD OF IN-SITU CLEANING FOR LPCVD TEOS PUMP
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/02/2004
|
Application #:
|
09776339
|
Filing Dt:
|
02/02/2001
|
|
Title:
|
PCI AND MII COMPATIBLE HOME PHONELINE NETWORKING ALLIANCE (HPNA) INTERFACE DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
09776736
|
Filing Dt:
|
02/06/2001
|
|
Title:
|
METHOD FOR MAKING A SLOT VIA FILLED DUAL DAMASCENE LOW K INTERCONNECT STRUCTURE WITHOUT MIDDLE STOP LAYER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09776748
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Filing Dt:
|
02/06/2001
|
|
Title:
|
NICKEL SILICIDE PROCESS USING STARVED SILICON DIFFUSION BARRIER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/10/2002
|
Application #:
|
09776813
|
Filing Dt:
|
02/05/2001
|
|
Title:
|
DEPOSITION OF IN-SITU DOPED SEMICONDUCTOR FILM AND UNDOPED SEMICONDUCTOR FILM IN THE SAME REACTION CHAMBER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09777637
|
Filing Dt:
|
02/06/2001
|
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE HAVING SOURCE/DRAIN SILICON-GERMANIUM REGIONS AND METHOD OF MANUFACTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09777695
|
Filing Dt:
|
02/07/2001
|
|
Title:
|
DUAL DAMASCENE WITH SILICON CARBIDE MIDDLE ETCH STOP LAYER/ARC
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2002
|
Application #:
|
09778064
|
Filing Dt:
|
02/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/08/2002
| | | | |
|
Title:
|
METHOD OF FABRICATING A SLOT DUAL DAMASCENE STRUCTURE WITHOUT MIDDLE STOP LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09778109
|
Filing Dt:
|
02/07/2001
|
|
Title:
|
SILICON CARBIDE BARC IN DUAL DAMASCENE PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09778352
|
Filing Dt:
|
02/06/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
|
Title:
|
FLOATING POINT ADDITION PIPELINE INCLUDING EXTREME VALUE, COMPARISON AND ACCUMULATE FUNCTIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09778529
|
Filing Dt:
|
02/07/2001
|
|
Title:
|
ACCURATE CONTACT CRITICAL DIMENSION MEASUREMENT USING VARIABLE THRESHOLD METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09778583
|
Filing Dt:
|
02/07/2001
|
|
Title:
|
METHOD TO IMPROVE ACCURACY OF MODEL-BASED OPTICAL PROXIMITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09778586
|
Filing Dt:
|
02/07/2001
|
|
Title:
|
TRI-TONE MASK PROCESS FOR DENSE AND ISOLATED PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
09778777
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09779986
|
Filing Dt:
|
02/09/2001
|
|
Title:
|
LOW TEMPERATURE PROCESS FOR A THIN FILM TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09779987
|
Filing Dt:
|
02/09/2001
|
|
Title:
|
PROCESS FOR MANUFACTURING MOS TRANSISTORS HAVING ELEVATED SOURCE AND DRAIN REGIONS AND A HIGH-K GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09779988
|
Filing Dt:
|
02/09/2001
|
|
Title:
|
LOW TEMPERATURE PROCESS FOR A TRANSISTOR WITH ELEVATED SOURCE AND DRAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
09780275
|
Filing Dt:
|
02/09/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/10/2002
| | | | |
|
Title:
|
ATTENUATING EXTREME ULTRAVIOLET (EUV) PHASE-SHIFTING MASK FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09780454
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
METHOD OF MAKING A SILICIDE STOP LAYER IN A DAMASCENE SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09780457
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
DUAL DAMASCENE ARRANGEMENT FOR METAL INTERCONNECTION WITH LOW K DIELECTRIC CONSTANT MATERIALS IN DIELECTRIC LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
09780476
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
AUTOMATED CONTROL OF METAL THICKNESS DURING FILM DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09781039
|
Filing Dt:
|
02/09/2001
|
|
Title:
|
LOW TEMPERATURE PROCESS TO LOCALLY FORM HIGH-K GATE DIELECTRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2002
|
Application #:
|
09781044
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
TRANSISTOR WITH AN ULTRA SHORT CHANNEL LENGTH DEFINED BY A LATERALLY DIFFUSED NITROGEN IMPLANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09781225
|
Filing Dt:
|
02/13/2001
|
|
Title:
|
ENHANCEMENT OF NICKEL SILICIDE FORMATION BY USE OF NICKEL PRE-AMORPHIZING IMPLANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09781256
|
Filing Dt:
|
02/13/2001
|
|
Title:
|
SILICON-STARVED NITRIDE SPACER DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09781357
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
LOW TEMPERATURE PROCESS TO FORM ELEVATED DRAIN AND SOURCE OF A FIELD EFFECT TRANSISTOR HAVING HIGH-K GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09781364
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN IN SOI TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09781783
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
FABRICATION OF FULLY DEPLETED FIELD EFFECT TRANSISTOR WITH HIGH-K GATE DIELECTRIC IN SOI TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09782843
|
Filing Dt:
|
02/14/2001
|
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING WAFER IDENTITY AND ORIENTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09783204
|
Filing Dt:
|
02/15/2001
|
|
Title:
|
METHOD AND APPARATUS FOR DETERMINING AN ETCH ENDPOINT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09783419
|
Filing Dt:
|
02/14/2001
|
|
Title:
|
METHOD AND APPARATUS FOR ALIGNING WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
09784629
|
Filing Dt:
|
02/15/2001
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR LOWERING MILLER CAPACITANCE FOR HIGH-SPEED MICROPROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2004
|
Application #:
|
09784790
|
Filing Dt:
|
02/15/2001
|
|
Title:
|
CHANNEL ISOLATION USING DIELECTRIC ISOLATION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09784842
|
Filing Dt:
|
02/15/2001
|
|
Title:
|
METHOD FOR LOW STRESS PLATING OF SEMICONDUCTOR VIAS AND CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09785176
|
Filing Dt:
|
02/20/2001
|
|
Title:
|
NISI CONTACTING EXTENSIONS OF ACTIVE REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09785444
|
Filing Dt:
|
02/20/2001
|
|
Title:
|
METHOD FOR PREVENTING DAMAGE OF LOW-K DIELECTRICS DURING PATTERNING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09785680
|
Filing Dt:
|
02/16/2001
|
|
Title:
|
T-SHAPED GATE ELECTRODE FOR REDUCED RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09788027
|
Filing Dt:
|
02/16/2001
|
|
Title:
|
METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09788067
|
Filing Dt:
|
02/16/2001
|
|
Title:
|
PHYSICAL RENAME REGISTER FOR EFFICIENTLY STORING FLOATING POINT, INTEGER, CONDITION CODE, AND MULTIMEDIA VALUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
09788246
|
Filing Dt:
|
02/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2001
| | | | |
|
Title:
|
METHOD FOR IMPROVED CONTROL OF LINES ADJACENT TO A SELECT GATE USING A MASK ASSIST FEATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09789134
|
Filing Dt:
|
02/20/2001
|
|
Title:
|
LEAKY LOWER INTERFACE FOR REDUCTION OF FLOATING BODY EFFECT IN SOI DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
09789140
|
Filing Dt:
|
02/20/2001
|
|
Title:
|
METHOD AND APPARATUS FOR INTEGRATING MULTIPLE PROCESS CONTROLLERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09789141
|
Filing Dt:
|
02/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/22/2002
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING SIGNAL CONTACTS AND HIGH CURRENT POWER CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09789765
|
Filing Dt:
|
02/22/2001
|
|
Title:
|
HYDROGEN PASSIVATED SILICON NITRIDE SPACERS FOR REDUCED NICKEL SILICIDE BRIDGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
09789871
|
Filing Dt:
|
02/21/2001
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING A TOOL USING A BASELINE CONTROL SCRIPT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
09789872
|
Filing Dt:
|
02/21/2001
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING PROCESS TARGET VALUES BASED ON MANUFACTURING METRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09789939
|
Filing Dt:
|
02/12/2001
|
|
Title:
|
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH AN UPSIDE DOWN T-SHAPED SEMICONDUCTOR PILLAR IN SOI TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09790135
|
Filing Dt:
|
02/21/2001
|
|
Title:
|
PROCESS FOR OBSERVING OVERLAY ERRORS ON LITHOGRAPHIC MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
09791981
|
Filing Dt:
|
02/23/2001
|
|
Title:
|
METHOD AND APPARATUS FOR ADAPTIVELY SCHEDULING TOOL MAINTENANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09792083
|
Filing Dt:
|
02/21/2001
|
|
Title:
|
AMORPHOUS AND GRADATED BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09792139
|
Filing Dt:
|
02/22/2001
|
|
Title:
|
SOI CHIP HAVING MULTIPLE THRESHOLD VOLTAGE MOSFETS BY USING MULTIPLE CHANNEL MATERIALS AND METHOD OF FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09792766
|
Filing Dt:
|
02/23/2001
|
|
Title:
|
Method of forming low resistance gate electrode
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
09793055
|
Filing Dt:
|
02/26/2001
|
|
Title:
|
METHOD OF FORMING A DOUBLE GATE TRANSISTOR HAVING AN EPITAXIAL SILICON/GERMANIUM CHANNEL REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09793986
|
Filing Dt:
|
02/28/2001
|
|
Title:
|
METHOD FOR FORMING BACKEND INTERCONNECT WITH COPPER ETCHING AND ULTRA LOW-K DIELECTRIC MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2003
|
Application #:
|
09794503
|
Filing Dt:
|
02/26/2001
|
|
Title:
|
FULL FLOW FOCUS EXPOSURE MATRIX ANALYSIS AND ELECTRICAL TESTING FOR NEW PRODUCT MASK EVALUATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09794712
|
Filing Dt:
|
02/26/2001
|
|
Title:
|
SYSTEM AND METHOD TO DETERMINE LINE EDGE ROUGHNESS AND/OR LINEWIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09794884
|
Filing Dt:
|
02/26/2001
|
|
Title:
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METHOD OF FABRICATION OF SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09795159
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Filing Dt:
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02/28/2001
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Title:
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SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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09797691
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Filing Dt:
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03/05/2001
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Title:
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INTELLIGENT EMBEDDED PROCESSOR ENABLED MECHANISM TO IMPLEMENT RSVP FUNCTION
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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09798660
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Filing Dt:
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03/02/2001
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Title:
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TWO-DIMENSIONAL INVERSE DISCRETE COSINE TRANSFORM USING SIMD INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09800166
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Filing Dt:
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03/06/2001
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Title:
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USE OF THERMAL FLOW TO REMOVE SIDE LOBES
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09800249
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Filing Dt:
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03/06/2001
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Title:
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ELIMINATION OF VOIDS AT THE OXIDE/SILICON INTERFACE IN TRENCH-BASED STRUCTURES
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09802437
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Filing Dt:
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03/09/2001
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Title:
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SILYLATION PROCESS FOR FORMING CONTACTS
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09803831
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Filing Dt:
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03/12/2001
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Title:
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METHOD OF FABRICATING ABRUPT SOURCE/DRAIN JUNCTIONS
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09803853
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Filing Dt:
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03/12/2001
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Title:
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ATTENUATED PHASE SHIFT MASK FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A MASK
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09804768
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Filing Dt:
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03/13/2001
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Publication #:
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Pub Dt:
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01/17/2002
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Title:
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LINE-ORIENTED REORDER BUFFER CONFIGURED TO SELECTIVELY STORE A MEMORY OPERATION RESULT IN ONE OF THE PLURALITY OF REORDER BUFFER STORAGE LOCATIONS CORRESPONDING TO THE EXECUTED INSTRUCTION
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09805651
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Filing Dt:
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03/13/2001
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Title:
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POST-CMP-CU DEPOSITION AND CMP TO ELIMINATE SURFACE VOIDS
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09805918
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Filing Dt:
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03/15/2001
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Title:
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CARRIER GAS MODIFICATION FOR PRESERVATION OF MASK LAYER DURING PLASMA ETCHING
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09808785
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Filing Dt:
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03/15/2001
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Title:
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ADC BASED IN-SITU DESTRUCTIVE ANALYSIS SELECTION AND METHODOLOGY THEREFOR
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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09808786
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Filing Dt:
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03/15/2001
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Title:
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EXPERIMENTAL DESIGN FOR COMPLEX SYSTEMS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09808896
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Filing Dt:
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03/15/2001
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Publication #:
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Pub Dt:
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08/30/2001
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Title:
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NON-UNIFORM GATE/DIELECTRIC FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09809016
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Filing Dt:
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03/16/2001
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Title:
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EXTERNAL CPU ASSIST WHEN PERFORMING A NETWORK ADDRESS LOOKUP
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09809133
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Filing Dt:
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03/15/2001
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Title:
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FIELD EFFECT TRANSISTOR HAVING DOPED GATE WITH PREVENTION OF CONTAMINATION FROM THE GATE DURING IMPLANTATION
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09809300
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Filing Dt:
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03/16/2001
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Title:
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PLASMA ETCHING USING COMBINATION OF CHF3 AND CH3F
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09809710
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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METHOD OF CONTROLLING A SHAPE OF AN OXIDE LAYER FORMED ON A SUBSTRATE
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09809754
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Filing Dt:
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03/13/2001
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Title:
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METHOD FOR ESTABLISHING COMPONENT ISOLATION REGIONS IN SOI SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09810348
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METAL GATE STACK WITH ETCH STOP LAYER HAVING IMPLANTED METAL SPECIES
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09810771
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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FULLY SELF-ALIGNED FET TECHNOLOGY
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09811190
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Filing Dt:
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03/16/2001
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Title:
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SYSTEM AND METHOD FOR CALIBRATING ELECTRON BEAM DEFECT INSPECTION TOOL
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09811501
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Filing Dt:
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03/19/2001
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Title:
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TEST CONTACT MECHANISM
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09811733
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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04/25/2002
| | | | |
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Title:
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SIDEWALL SPACER BASED FET ALIGNMENT TECHNOLOGY
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09812095
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Filing Dt:
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03/19/2001
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Title:
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METHOD FOR FABRICATING A BIPOLAR JUNCTION TRANSISTOR WITH TUNNELING CURRENT THROUGH THE GATE OF A FIELD EFFECT TRANSISTOR AS BASE CURRENT
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09812206
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Filing Dt:
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03/19/2001
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Title:
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METHOD FOR ULTRA THIN RESIST LINEWIDTH REDUCTION USING IMPLANTATION
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09812372
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Filing Dt:
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03/20/2001
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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SEMICONDUCTOR DEVICE WITH REDUCED LINE-TO-LINE CAPACITANCE AND CROSS TALK NOISE
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09812695
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Filing Dt:
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03/21/2001
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Title:
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REDUCTION OF METAL SILICIDE/SILICON INTERFACE ROUGHNESS BY DOPANT IMPLANTATION PROCESSING
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09813309
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Filing Dt:
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03/21/2001
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Title:
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METAL INTERCONNECTION STRUCTURE WITH DUMMY VIAS
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09814231
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Filing Dt:
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03/21/2001
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Title:
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METHOD AND APPARATUS FOR CONTROLLING OPTICAL PARAMETERS IN A STEPPER
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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09814812
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Filing Dt:
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03/23/2001
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Title:
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ACTION TAG GENERATION WITHIN A NETWORK BASED ON PRIORITY OR DIFFERENTIAL SERVICES INFORMATION
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09814813
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Filing Dt:
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03/23/2001
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Title:
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SYSTEM AND METHOD FOR PERFORMING LAYER 3 SWITCHING IN A NETWORK DEVICE
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09814815
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Filing Dt:
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03/23/2001
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Title:
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SELECTIVE ADMISSION CONTROL IN A NETWORK DEVICE
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