Total properties:
121
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2
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2
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10308661
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Filing Dt:
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12/02/2002
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED EMITTER IN A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10313508
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Filing Dt:
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12/06/2002
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Title:
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A METASTABLE BASE IN A HIGH-PERFORMANCE HBT
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10313700
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Filing Dt:
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12/07/2002
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Title:
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SYSTEM FOR FABRICATING A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10320334
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Filing Dt:
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12/16/2002
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Title:
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PROBE CARD AND PROBE NEEDLE FOR HIGH FREQUENCY TESTING
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10324341
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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BIFET VOLTAGE CONTROLLED OSCILLATOR
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10356447
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Filing Dt:
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02/01/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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METHOD FOR PATTERNING DENSELY PACKED METAL SEGMENTS IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10364550
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Filing Dt:
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02/10/2003
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Title:
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METHOD FOR CONTROLLING CRITICAL DIMENSION IN AN HBT EMITTER
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10369027
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Filing Dt:
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02/19/2003
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Title:
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METHOD FOR CONTROLLING AN EMITTER WINDOW OPENING IN AN HBT AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10371416
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Filing Dt:
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02/20/2003
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Title:
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METHOD FOR HARD MASK REMOVAL FOR DEEP TRENCH ISOLATION AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10371706
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Filing Dt:
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02/21/2003
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Title:
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METHOD FOR FABRICATING A BIPOLAR TRANSISTOR IN A BICMOS PROCESS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10375727
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Filing Dt:
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02/26/2003
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Title:
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METHOD FOR IMPROVED ALIGNMENT TOLERANCE IN A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10410937
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Filing Dt:
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04/09/2003
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Title:
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HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10431073
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Filing Dt:
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05/06/2003
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Title:
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TRANSPARENT PHASE SHIFT MASK FOR FABRICATION OF SMALL FEATURE SIZES
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10437530
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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11/18/2004
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Title:
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METHOD FOR FABRICATION OF SIGE LAYER HAVING SMALL POLY GRAINS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10437723
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Filing Dt:
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05/13/2003
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Title:
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METHOD FOR FABRICATION OF EMITTER OF A TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10442489
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITH PLANARIZING LAYER AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10442492
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS AND METHOD FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10442501
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Filing Dt:
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05/21/2003
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS AND METHOD FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10447397
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Filing Dt:
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05/28/2003
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Title:
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HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10692431
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Filing Dt:
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10/22/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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HIGH-K DIELECTRIC STACK IN A MIM CAPACITOR AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10821425
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Filing Dt:
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04/09/2004
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Title:
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METHOD FOR INTEGRATING SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE AND RELATED STRUCTURE
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