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Reel/Frame:023119/0083   Pages: 180
Recorded: 08/18/2009
Attorney Dkt #:6363-00000
Conveyance: AFFIRMATION OF PATENT ASSIGNMENT
Total properties: 2907
Page 20 of 30
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
Patent #:
6963536
Issue Dt:
11/08/2005
Application #:
09814816
Filing Dt:
03/23/2001
Title:
ADMISSION CONTROL IN A NETWORK DEVICE
2
Patent #:
6738731
Issue Dt:
05/18/2004
Application #:
09815445
Filing Dt:
03/22/2001
Title:
METHOD AND APPARATUS FOR USING TOOL STATE INFORMATION TO IDENTIFY FAULTY WAFERS
3
Patent #:
6917623
Issue Dt:
07/12/2005
Application #:
09816334
Filing Dt:
03/26/2001
Title:
SYSTEM AND METHOD FOR TRANSFERRING DATA IN A NETWORK DEVICE
4
Patent #:
6996124
Issue Dt:
02/07/2006
Application #:
09816706
Filing Dt:
03/23/2001
Title:
MECHANISM TO STRIP LARQ HEADER AND REGENERATE FCS TO SUPPORT SLEEP MODE WAKE UP
5
Patent #:
6555472
Issue Dt:
04/29/2003
Application #:
09816877
Filing Dt:
03/21/2001
Publication #:
US20020045331
Pub Dt:
04/18/2002
Title:
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE USING FEATURE TRIMMING
6
Patent #:
6713874
Issue Dt:
03/30/2004
Application #:
09817050
Filing Dt:
03/27/2001
Title:
SEMICONDUCTOR DEVICES WITH DUAL NATURE CAPPING/ARC LAYERS ON ORGANIC -DOPED SILICA GLASS INTERLAYER DIELECTRICS
7
Patent #:
6562248
Issue Dt:
05/13/2003
Application #:
09817518
Filing Dt:
03/26/2001
Title:
ACTIVE CONTROL OF PHASE SHIFT MASK ETCHING PROCESS
8
Patent #:
6709935
Issue Dt:
03/23/2004
Application #:
09817580
Filing Dt:
03/26/2001
Title:
METHOD OF LOCALLY FORMING A SILICON/GERMANIUM CHANNEL LAYER
9
Patent #:
6514867
Issue Dt:
02/04/2003
Application #:
09817586
Filing Dt:
03/26/2001
Title:
METHOD OF CREATING NARROW TRENCH LINES USING HARD MASK
10
Patent #:
6387758
Issue Dt:
05/14/2002
Application #:
09817625
Filing Dt:
03/26/2001
Title:
METHOD OF MAKING VERTICAL FIELD EFFECT TRANSISTOR HAVING CHANNEL LENGTH DETERMINED BY THE THICKNESS OF A LAYER OF DUMMY MATERIAL
11
Patent #:
6650422
Issue Dt:
11/18/2003
Application #:
09817820
Filing Dt:
03/26/2001
Publication #:
US20020135781
Pub Dt:
09/26/2002
Title:
SCATTEROMETRY TECHNIQUES TO ASCERTAIN ASYMMETRY PROFILE OF FEATURES AND GENERATE FEEDBACK OR FEEDFORWARD PROCESS CONTROL DATA ASSOCIATED THEREWITH
12
Patent #:
6583488
Issue Dt:
06/24/2003
Application #:
09817858
Filing Dt:
03/26/2001
Title:
LOW DENSITY, TENSILE STRESS REDUCING MATERIAL FOR STI TRENCH FILL
13
Patent #:
6534373
Issue Dt:
03/18/2003
Application #:
09817919
Filing Dt:
03/26/2001
Title:
MOS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT
14
Patent #:
6630288
Issue Dt:
10/07/2003
Application #:
09819342
Filing Dt:
03/28/2001
Publication #:
US20020160320
Pub Dt:
10/31/2002
Title:
PROCESS FOR FORMING SUB-LITHOGRAPHIC PHOTORESIST FEATURES BY MODIFICATION OF THE PHOTORESIST SURFACE
15
Patent #:
6716571
Issue Dt:
04/06/2004
Application #:
09819343
Filing Dt:
03/28/2001
Publication #:
US20020139773
Pub Dt:
10/03/2002
Title:
SELECTIVE PHOTORESIST HARDENING TO FACILITATE LATERAL TRIMMING
16
Patent #:
6653231
Issue Dt:
11/25/2003
Application #:
09819344
Filing Dt:
03/28/2001
Publication #:
US20020160628
Pub Dt:
10/31/2002
Title:
PROCESS FOR REDUCING THE CRITICAL DIMENSIONS OF INTEGRATED CIRCUIT DEVICE FEATURES
17
Patent #:
6815359
Issue Dt:
11/09/2004
Application #:
09819552
Filing Dt:
03/28/2001
Publication #:
US20020142607
Pub Dt:
10/03/2002
Title:
PROCESS FOR IMPROVING THE ETCH STABILITY OF ULTRA-THIN PHOTORESIST
18
Patent #:
6589709
Issue Dt:
07/08/2003
Application #:
09819692
Filing Dt:
03/28/2001
Title:
PROCESS FOR PREVENTING DEFORMATION OF PATTERNED PHOTORESIST FEATURES
19
Patent #:
6566886
Issue Dt:
05/20/2003
Application #:
09819785
Filing Dt:
03/28/2001
Title:
METHOD OF DETECTING CRYSTALLINE DEFECTS USING SOUND WAVES
20
Patent #:
6754553
Issue Dt:
06/22/2004
Application #:
09820033
Filing Dt:
03/28/2001
Publication #:
US20020059011
Pub Dt:
05/16/2002
Title:
IMPLANT MONITORING USING MULTIPLE IMPLANTING AND ANNEALING STEPS
21
Patent #:
6699727
Issue Dt:
03/02/2004
Application #:
09821675
Filing Dt:
03/29/2001
Title:
METHOD FOR PRIORITIZING PRODUCTION LOTS BASED ON GRADE ESTIMATES AND OUTPUT REQUIREMENTS
22
Patent #:
6563578
Issue Dt:
05/13/2003
Application #:
09824112
Filing Dt:
04/02/2001
Publication #:
US20020142493
Pub Dt:
10/03/2002
Title:
IN-SITU THICKNESS MEASUREMENT FOR USE IN SEMICONDUCTOR PROCESSING
23
Patent #:
6707684
Issue Dt:
03/16/2004
Application #:
09824135
Filing Dt:
04/02/2001
Title:
METHOD AND APPARATUS FOR DIRECT CONNECTION BETWEEN TWO INTEGRATED CIRCUITS VIA A CONNECTOR
24
Patent #:
6989900
Issue Dt:
01/24/2006
Application #:
09824156
Filing Dt:
04/02/2001
Title:
METHOD OF MEASURING IMPLANT PROFILES USING SCATTEROMETRIC TECHNIQUES
25
Patent #:
6511911
Issue Dt:
01/28/2003
Application #:
09824218
Filing Dt:
04/03/2001
Title:
METAL GATE STACK WITH ETCH STOP LAYER
26
Patent #:
6602723
Issue Dt:
08/05/2003
Application #:
09824285
Filing Dt:
04/02/2001
Title:
METHOD OF INTEGRATING SCATTEROMETRY METROLOGY STRUCTURES DIRECTLY INTO DIE DESIGN
27
Patent #:
6465267
Issue Dt:
10/15/2002
Application #:
09824408
Filing Dt:
04/02/2001
Title:
METHOD OF MEASURING GATE CAPACITANCE TO DETERMINE THE ELECTRICAL THICKNESS OF GATE DIELECTRICS
28
Patent #:
6664180
Issue Dt:
12/16/2003
Application #:
09824415
Filing Dt:
04/02/2001
Title:
METHOD OF FORMING SMALLER TRENCH LINE WIDTH USING A SPACER HARD MASK
29
Patent #:
6475867
Issue Dt:
11/05/2002
Application #:
09824416
Filing Dt:
04/02/2001
Title:
METHOD OF FORMING INTEGRATED CIRCUIT FEATURES BY OXIDATION OF TITANIUM HARD MASK
30
Patent #:
6514849
Issue Dt:
02/04/2003
Application #:
09824420
Filing Dt:
04/02/2001
Title:
METHOD OF FORMING SMALLER CONTACT SIZE USING A SPACER HARD MASK
31
Patent #:
6358843
Issue Dt:
03/19/2002
Application #:
09824421
Filing Dt:
04/02/2001
Title:
Method of making ultra small vias for integrated circuits
32
Patent #:
6993033
Issue Dt:
01/31/2006
Application #:
09824702
Filing Dt:
04/04/2001
Title:
METHOD AND APPARATUS FOR SYNCHRONIZING AGING OPERATIONS ASSOCIATED WITH AN ADDRESS TABLE
33
Patent #:
6877084
Issue Dt:
04/05/2005
Application #:
09824863
Filing Dt:
04/02/2001
Title:
CENTRAL PROCESSING UNIT (CPU) ACCESSING AN EXTENDED REGISTER SET IN AN EXTENDED REGISTER MODE
34
Patent #:
6410938
Issue Dt:
06/25/2002
Application #:
09824932
Filing Dt:
04/03/2001
Title:
SEMICONDUCTOR-ON-INSULATOR DEVICE WITH NITRIDED BURIED OXIDE AND METHOD OF FABRICATING
35
Patent #:
6807617
Issue Dt:
10/19/2004
Application #:
09824995
Filing Dt:
04/02/2001
Publication #:
US20020144080
Pub Dt:
10/03/2002
Title:
DESCRIPTOR TABLE STORING SEGMENT DESCRIPTORS OF VARYING SIZE
36
Patent #:
6458662
Issue Dt:
10/01/2002
Application #:
09826551
Filing Dt:
04/04/2001
Title:
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN ASYMMETRICAL DUAL-GATE SILICON-GERMANIUM (SIGE) CHANNEL MOSFET AND A DEVICE THEREBY FORMED
37
Patent #:
6514858
Issue Dt:
02/04/2003
Application #:
09829202
Filing Dt:
04/09/2001
Title:
TEST STRUCTURE FOR PROVIDING DEPTH OF POLISH FEEDBACK
38
Patent #:
6350639
Issue Dt:
02/26/2002
Application #:
09832684
Filing Dt:
04/10/2001
Title:
METHOD FOR FORMING SIMPLIFIED GRADED LDD TRANSISTOR USING CONTROLLED POLYSILICON GATE PROFILE
39
Patent #:
6509201
Issue Dt:
01/21/2003
Application #:
09832697
Filing Dt:
04/11/2001
Title:
METHOD AND APPARATUS FOR MONITORING WAFER STRESS
40
Patent #:
6563300
Issue Dt:
05/13/2003
Application #:
09832781
Filing Dt:
04/11/2001
Title:
METHOD AND APPARATUS FOR FAULT DETECTION USING MULTIPLE TOOL ERROR SIGNALS
41
Patent #:
7088852
Issue Dt:
08/08/2006
Application #:
09833247
Filing Dt:
04/11/2001
Title:
THREE-DIMENSIONAL TOMOGRAPHY
42
Patent #:
6455415
Issue Dt:
09/24/2002
Application #:
09836054
Filing Dt:
04/16/2001
Title:
METHOD OF ENCAPSULATED COPPER (CU) INTERCONNECT FORMATION
43
Patent #:
6495393
Issue Dt:
12/17/2002
Application #:
09836747
Filing Dt:
04/17/2001
Publication #:
US20010039073
Pub Dt:
11/08/2001
Title:
METHOD TO IMPROVE CHIP SCALE PACKAGE ELECTROSTATIC DISCHARGE PERFORMANCE AND SUPPRESS MARKING ARTIFACTS
44
Patent #:
6524163
Issue Dt:
02/25/2003
Application #:
09837603
Filing Dt:
04/18/2001
Title:
METHOD AND APPARATUS FOR CONTROLLING A POLISHING PROCESS BASED ON SCATTEROMETRY DERIVED FILM THICKNESS VARIATION
45
Patent #:
6540591
Issue Dt:
04/01/2003
Application #:
09837606
Filing Dt:
04/18/2001
Title:
METHOD AND APPARATUS FOR POST-POLISH THICKNESS AND UNIFORMITY CONTROL
46
Patent #:
6383888
Issue Dt:
05/07/2002
Application #:
09837712
Filing Dt:
04/18/2001
Title:
METHOD AND APPARATUS FOR SELECTING WAFER ALIGNMENT MARKS BASED ON FILM THICKNESS VARIATION
47
Patent #:
6358826
Issue Dt:
03/19/2002
Application #:
09838389
Filing Dt:
04/19/2001
Title:
DEVICE IMPROVEMENT BY LOWERING LDD RESISTANCE WITH NEW SPACER/SILICIDE PROCESS
48
Patent #:
6700659
Issue Dt:
03/02/2004
Application #:
09838671
Filing Dt:
04/19/2001
Title:
SEMICONDUCTOR ANALYSIS ARRANGEMENT AND METHOD THEREFOR
49
Patent #:
6635839
Issue Dt:
10/21/2003
Application #:
09838672
Filing Dt:
04/19/2001
Title:
SEMICONDUCTOR ANALYSIS ARRANGEMENT AND METHOD THEREFOR
50
Patent #:
6844928
Issue Dt:
01/18/2005
Application #:
09838717
Filing Dt:
04/19/2001
Title:
FIBER OPTIC SEMICONDUCTOR ANALYSIS ARRANGEMENT AND METHOD THEREFOR
51
Patent #:
6800933
Issue Dt:
10/05/2004
Application #:
09840019
Filing Dt:
04/23/2001
Title:
INTEGRATED CIRCUIT COOLING DEVICE
52
Patent #:
6514844
Issue Dt:
02/04/2003
Application #:
09840598
Filing Dt:
04/23/2001
Title:
SIDEWALL TREATMENT FOR LOW DIELECTRIC CONSTANT (LOW K) MATERIALS BY ION IMPLANTATION
53
Patent #:
6684305
Issue Dt:
01/27/2004
Application #:
09841469
Filing Dt:
04/24/2001
Title:
MULTIPROCESSOR SYSTEM IMPLEMENTING VIRTUAL MEMORY USING A SHARED MEMORY, AND A PAGE REPLACEMENT METHOD FOR MAINTAINING PAGED MEMORY COHERENCE
54
Patent #:
6383824
Issue Dt:
05/07/2002
Application #:
09843111
Filing Dt:
04/25/2001
Title:
METHOD OF USING SCATTEROMETRY MEASUREMENTS TO CONTROL DEPOSITION PROCESSES
55
Patent #:
6506650
Issue Dt:
01/14/2003
Application #:
09843782
Filing Dt:
04/27/2001
Title:
METHOD OF FABRICATION BASED ON SOLID-PHASE EPITAXY FOR A MOSFET TRANSISTOR WITH A CONTROLLED DOPANT PROFILE
56
Patent #:
6515333
Issue Dt:
02/04/2003
Application #:
09843958
Filing Dt:
04/27/2001
Title:
REMOVAL OF HEAT FROM SOI DEVICE
57
Patent #:
6475811
Issue Dt:
11/05/2002
Application #:
09844213
Filing Dt:
04/27/2001
Title:
SYSTEM FOR AND METHOD OF USING BACTERIA TO AID IN CONTACT HOLE PRINTING
58
Patent #:
6528412
Issue Dt:
03/04/2003
Application #:
09844727
Filing Dt:
04/30/2001
Title:
DEPOSITING AN ADHESION SKIN LAYER AND A CONFORMAL SEED LAYER TO FILL AN INTERCONNECT OPENING
59
Patent #:
6630385
Issue Dt:
10/07/2003
Application #:
09844773
Filing Dt:
04/27/2001
Title:
MOSFET WITH DIFFERENTIAL HALO IMPLANT AND ANNEALING STRATEGY
60
Patent #:
6420189
Issue Dt:
07/16/2002
Application #:
09844845
Filing Dt:
04/27/2001
Title:
SUPERCONDUCTING DAMASCENE INTERCONNECT FOR INTEGRATED CIRCUIT
61
Patent #:
7079975
Issue Dt:
07/18/2006
Application #:
09845231
Filing Dt:
04/30/2001
Title:
SCATTEROMETRY AND ACOUSTIC BASED ACTIVE CONTROL OF THIN FILM DEPOSITION PROCESS
62
Patent #:
6535015
Issue Dt:
03/18/2003
Application #:
09845266
Filing Dt:
04/30/2001
Title:
DEVICE AND METHOD FOR TESTING PERFORMANCE OF SILICON STRUCTURES
63
Patent #:
7052575
Issue Dt:
05/30/2006
Application #:
09845454
Filing Dt:
04/30/2001
Title:
SYSTEM AND METHOD FOR ACTIVE CONTROL OF ETCH PROCESS
64
Patent #:
6447933
Issue Dt:
09/10/2002
Application #:
09845616
Filing Dt:
04/30/2001
Title:
FORMATION OF ALLOY MATERIAL USING ALTERNATING DEPOSITIONS OF ALLOY DOPING ELEMENT AND BULK MATERIAL
65
Patent #:
6753266
Issue Dt:
06/22/2004
Application #:
09845654
Filing Dt:
04/30/2001
Title:
METHOD OF ENHANCING GATE PATTERNING PROPERTIES WITH REFLECTIVE HARD MASK
66
Patent #:
6440806
Issue Dt:
08/27/2002
Application #:
09845859
Filing Dt:
04/30/2001
Title:
METHOD FOR PRODUCING METAL-SEMICONDUCTOR COMPOUND REGIONS ON SEMICONDUCTOR DEVICES
67
Patent #:
6458686
Issue Dt:
10/01/2002
Application #:
09845980
Filing Dt:
04/30/2001
Title:
INVERSE INTEGRATED CIRCUIT FABRICATION PROCESS
68
Patent #:
6506677
Issue Dt:
01/14/2003
Application #:
09846186
Filing Dt:
05/02/2001
Title:
METHOD OF FORMING CAPPED COPPER INTERCONNECTS WITH REDUCED HILLOCK FORMATION AND IMPROVED ELECTROMIGRATION RESISTANCE
69
Patent #:
6562416
Issue Dt:
05/13/2003
Application #:
09846187
Filing Dt:
05/02/2001
Publication #:
US20020162736
Pub Dt:
11/07/2002
Title:
METHOD OF FORMING LOW RESISTANCE VIAS
70
Patent #:
6611023
Issue Dt:
08/26/2003
Application #:
09846502
Filing Dt:
05/01/2001
Title:
FIELD EFFECT TRANSISTOR WITH SELF ALLIGNED DOUBLE GATE AND METHOD OF FORMING SAME
71
Patent #:
6432822
Issue Dt:
08/13/2002
Application #:
09846611
Filing Dt:
05/02/2001
Title:
METHOD OF IMPROVING ELECTROMIGRATION RESISTANCE OF CAPPED CU
72
Patent #:
6620671
Issue Dt:
09/16/2003
Application #:
09846813
Filing Dt:
05/01/2001
Title:
METHOD OF FABRICATING TRANSISTOR HAVING A SINGLE CRYSTALLINE GATE CONDUCTOR
73
Patent #:
6448613
Issue Dt:
09/10/2002
Application #:
09846958
Filing Dt:
05/01/2001
Title:
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH MINIMIZED PARASITIC MILLER CAPACITANCE
74
Patent #:
6423604
Issue Dt:
07/23/2002
Application #:
09846969
Filing Dt:
05/01/2001
Title:
DETERMINATION OF THERMAL RESISTANCE FOR FIELD EFFECT TRANSISTOR FORMED IN SOI TECHNOLOGY
75
Patent #:
6798028
Issue Dt:
09/28/2004
Application #:
09847622
Filing Dt:
05/02/2001
Publication #:
US20020056859
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH REDUCED GATE DELAY AND METHOD OF FABRICATING THE SAME
76
Patent #:
6593037
Issue Dt:
07/15/2003
Application #:
09847803
Filing Dt:
05/02/2001
Title:
EUV MASK OR RETICLE HAVING REDUCED REFLECTIONS
77
Patent #:
6566718
Issue Dt:
05/20/2003
Application #:
09848085
Filing Dt:
05/03/2001
Publication #:
US20020056879
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH AN IMPROVED GATE CONTACT
78
Patent #:
6735649
Issue Dt:
05/11/2004
Application #:
09848652
Filing Dt:
05/03/2001
Publication #:
US20020166006
Pub Dt:
11/07/2002
Title:
MULTIPLE BUFFERS FOR REMOVING UNWANTED HEADER INFORMATION FROM RECEIVED DATA PACKETS
79
Patent #:
6498397
Issue Dt:
12/24/2002
Application #:
09848979
Filing Dt:
05/04/2001
Title:
SEED LAYER WITH ANNEALED REGION FOR INTEGRATED CIRCUIT INTERCONNECTS
80
Patent #:
6410461
Issue Dt:
06/25/2002
Application #:
09849357
Filing Dt:
05/07/2001
Title:
METHOD OF DEPOSITING SION WITH REDUCED DEFECTS
81
Patent #:
6509613
Issue Dt:
01/21/2003
Application #:
09849494
Filing Dt:
05/04/2001
Title:
SELF-ALIGNED FLOATING BODY CONTROL FOR SOI DEVICE THROUGH LEAKAGE ENHANCED BURIED OXIDE
82
Patent #:
6424009
Issue Dt:
07/23/2002
Application #:
09849560
Filing Dt:
05/04/2001
Title:
POLYSILICON INSULATOR MATERIAL IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE
83
Patent #:
6512244
Issue Dt:
01/28/2003
Application #:
09850392
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
84
Patent #:
7122863
Issue Dt:
10/17/2006
Application #:
09850393
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
85
Patent #:
6593227
Issue Dt:
07/15/2003
Application #:
09851199
Filing Dt:
05/08/2001
Title:
METHOD AND APPARATUS FOR PLANARIZING SURFACES OF SEMICONDUCTOR DEVICE CONDUCTIVE LAYERS
86
Patent #:
6709797
Issue Dt:
03/23/2004
Application #:
09851900
Filing Dt:
05/09/2001
Title:
METHOD AND APPARATUS FOR CONTROLLING FOCUS BASED ON A THICKNESS OF A LAYER OF PHOTORESIST
87
Patent #:
7065654
Issue Dt:
06/20/2006
Application #:
09852372
Filing Dt:
05/10/2001
Title:
SECURE EXECUTION BOX
88
Patent #:
6410410
Issue Dt:
06/25/2002
Application #:
09852535
Filing Dt:
05/10/2001
Publication #:
US20020061626
Pub Dt:
05/23/2002
Title:
METHOD OF FORMING LIGHTLY DOPED REGIONS IN A SEMICONDUCTOR DEVICE
89
Patent #:
6862641
Issue Dt:
03/01/2005
Application #:
09853234
Filing Dt:
05/11/2001
Title:
INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE
90
Patent #:
6531710
Issue Dt:
03/11/2003
Application #:
09853342
Filing Dt:
05/10/2001
Title:
SOI FILM FORMED BY LASER ANNEALING
91
Patent #:
7216362
Issue Dt:
05/08/2007
Application #:
09853395
Filing Dt:
05/11/2001
Title:
ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM
92
Patent #:
6832317
Issue Dt:
12/14/2004
Application #:
09853437
Filing Dt:
05/11/2001
Title:
PERSONAL COMPUTER SECURITY MECHANSIM
93
Patent #:
7043581
Issue Dt:
05/09/2006
Application #:
09853446
Filing Dt:
05/11/2001
Title:
RESOURSE SEQUESTER MECHANISM
94
Patent #:
6823451
Issue Dt:
11/23/2004
Application #:
09853447
Filing Dt:
05/11/2001
Title:
INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY
95
Patent #:
6968460
Issue Dt:
11/22/2005
Application #:
09854040
Filing Dt:
05/11/2001
Title:
CRYPTOGRAPHIC RANDOMNESS REGISTER FOR COMPUTER SYSTEM SECURITY
96
Patent #:
6725337
Issue Dt:
04/20/2004
Application #:
09859290
Filing Dt:
05/16/2001
Title:
METHOD AND SYSTEM FOR SPECULATIVELY INVALIDATING LINES IN A CACHE
97
Patent #:
6399493
Issue Dt:
06/04/2002
Application #:
09860141
Filing Dt:
05/17/2001
Title:
METHOD OF SILICIDE FORMATION BY SILICON PRETREATMENT
98
Patent #:
6464563
Issue Dt:
10/15/2002
Application #:
09860226
Filing Dt:
05/18/2001
Title:
METHOD AND APPARATUS FOR DETECTING DISHING IN A POLISHED LAYER
99
Patent #:
6549990
Issue Dt:
04/15/2003
Application #:
09862687
Filing Dt:
05/21/2001
Publication #:
US20010037434
Pub Dt:
11/01/2001
Title:
STORE TO LOAD FORWARDING USING A DEPENDENCY LINK FILE
100
Patent #:
6677170
Issue Dt:
01/13/2004
Application #:
09863596
Filing Dt:
05/23/2001
Title:
METHOD FOR DETERMINING PROCESS LAYER THICKNESS USING SCATTEROMETRY MEASUREMENTS
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
06/30/2009
Assignee
1
GLOBALFOUNDRIES INC.
P.O. BOX 309, UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BNK / MHKKG
P.O. BOX 398
AUSTIN, TX 78767-0398

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