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Reel/Frame:023119/0083   Pages: 180
Recorded: 08/18/2009
Attorney Dkt #:6363-00000
Conveyance: AFFIRMATION OF PATENT ASSIGNMENT
Total properties: 2907
Page 22 of 30
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
Patent #:
Issue Dt:
09/23/2003
Application #:
09933290
Filing Dt:
08/20/2001
Title:
A METHOD FOR SYNCHRONIZING GENERATION AND CONSUMPTION OF ISOCHRONOUS DATA
2
Patent #:
Issue Dt:
08/31/2004
Application #:
09939744
Filing Dt:
08/28/2001
Publication #:
Pub Dt:
03/06/2003
Title:
IMPROVED SILICIDE PROCESS USING HIGH K-DIELECTRICS
3
Patent #:
Issue Dt:
10/07/2003
Application #:
09943570
Filing Dt:
08/29/2001
Title:
ELECTROSTATIC LENS HAVING GLASSY GRAPHITE ELECTRODES
4
Patent #:
Issue Dt:
12/21/2004
Application #:
09951473
Filing Dt:
09/13/2001
Title:
PINHOLE DEFECT REPAIR BY RESIST FLOW
5
Patent #:
Issue Dt:
05/13/2003
Application #:
09955552
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
03/20/2003
Title:
WAFER BASED TEMPERATURE SENSORS FOR CHARACTERIZING CHEMICAL MECHANICAL POLISHING PROCESSES
6
Patent #:
Issue Dt:
12/14/2004
Application #:
09969304
Filing Dt:
10/02/2001
Title:
APPARATUS AND METHOD FOR PROVIDING AN EXTERNAL CLOCK FROM A CIRCUIT IN SLEEP MODE IN A PROCESSOR -BASED SYSTEM
7
Patent #:
Issue Dt:
12/14/2004
Application #:
09973034
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
04/25/2002
Title:
PARALLEL PLATE DEVELOPMENT WITH THE APPLICATION OF A DIFFERENTIAL VOLTAGE
8
Patent #:
Issue Dt:
08/17/2004
Application #:
09973231
Filing Dt:
10/09/2001
Title:
SYSTEM AND METHOD FOR PROCESS MONITORING OF POLYSILICON ETCH
9
Patent #:
Issue Dt:
06/17/2003
Application #:
09974217
Filing Dt:
10/09/2001
Title:
MANUFACTURING METHOD FOR FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE
10
Patent #:
Issue Dt:
05/07/2002
Application #:
09974568
Filing Dt:
10/10/2001
Title:
INSULATING AND CAPPING STRUCTURE WITH PRESERVATION OF THE LOW DIELECTRIC CONSTANT OF THE INSULATING LAYER
11
Patent #:
Issue Dt:
12/03/2002
Application #:
09975032
Filing Dt:
10/10/2001
Title:
VARIABLE GRAIN SIZE IN CONDUCTORS FOR SEMICONDUCTOR VIAS AND TRENCHES
12
Patent #:
Issue Dt:
05/13/2003
Application #:
09977922
Filing Dt:
10/15/2001
Title:
PREPARATION OF COMPOSITE HIGH-K DIELECTRICS
13
Patent #:
Issue Dt:
05/06/2003
Application #:
09977928
Filing Dt:
10/15/2001
Title:
PREPARATION OF COMPOSITE HIGH-K / STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES
14
Patent #:
Issue Dt:
04/27/2004
Application #:
09978351
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
05/22/2003
Title:
TAGGING AND ARBITRATION MECHANISM IN AN INPUT/OUTPUT NODE OF A COMPUTER SYSTEM
15
Patent #:
Issue Dt:
01/20/2004
Application #:
09978378
Filing Dt:
10/15/2001
Publication #:
Pub Dt:
05/15/2003
Title:
VIRTUAL CHANNEL BUFFER BYPASS FOR AN I/O NODE OF A COMPUTER SYSTEM
16
Patent #:
Issue Dt:
03/30/2004
Application #:
09981618
Filing Dt:
10/15/2001
Title:
APPARATUS AND METHOD FOR ALLOCATING BUFFER SPACE
17
Patent #:
Issue Dt:
10/28/2003
Application #:
09986263
Filing Dt:
11/08/2001
Title:
METHOD OF ELIMINATING VOIDS IN W PLUGS
18
Patent #:
Issue Dt:
04/27/2004
Application #:
09986267
Filing Dt:
11/08/2001
Publication #:
Pub Dt:
05/08/2003
Title:
METHOD OF FORMING RELIABLE CU INTERCONNECTS
19
Patent #:
Issue Dt:
03/16/2004
Application #:
09992447
Filing Dt:
11/16/2001
Publication #:
Pub Dt:
05/22/2003
Title:
METHOD AND APPARATUS FOR UTILIZING INTEGRATED METROLOGY DATA AS FEED-FORWARD DATA
20
Patent #:
Issue Dt:
01/21/2003
Application #:
09994128
Filing Dt:
11/26/2001
Title:
SILICON-STARVED PECVD METHOD FOR METAL GATE ELECTRODE DIELECTRIC SPACER
21
Patent #:
Issue Dt:
03/09/2004
Application #:
09994358
Filing Dt:
11/26/2001
Publication #:
Pub Dt:
02/05/2004
Title:
METHOD OF IMPLANTATION AFTER COPPER SEED DEPOSITION
22
Patent #:
Issue Dt:
03/09/2004
Application #:
09994400
Filing Dt:
11/26/2001
Title:
METHOD OF INSERTING ALLOY ELEMENTS TO REDUCE COPPER DIFFUSION AND BULK DIFFUSION
23
Patent #:
Issue Dt:
05/13/2003
Application #:
09999703
Filing Dt:
10/24/2001
Title:
METHOD AND APPARATUS FOR REDUCING ELECTROMIGRATION IN SEMICONDUCTOR INTERCONNECT LINES
24
Patent #:
Issue Dt:
12/26/2006
Application #:
10000208
Filing Dt:
10/23/2001
Title:
RE-CIRCULATION AND REUSE OF DUMMY-DISPENSED RESIST
25
Patent #:
Issue Dt:
03/18/2003
Application #:
10000493
Filing Dt:
10/23/2001
Title:
CHEMICAL FEATURE DOUBLING PROCESS
26
Patent #:
Issue Dt:
06/19/2007
Application #:
10002185
Filing Dt:
12/05/2001
Title:
ARRANGEMENT FOR INITIALIZING DIGITAL EQUALIZER SETTINGS BASED ON COMPARING DIGITAL EQUALIZER OUTPUTS TO PRESCRIBED EQUALIZER OUTPUTS
27
Patent #:
Issue Dt:
02/08/2005
Application #:
10005271
Filing Dt:
12/05/2001
Title:
MEMORY MANAGEMENT SYSTEM AND METHOD PROVIDING INCREASED MEMORY ACCESS SECURITY
28
Patent #:
Issue Dt:
10/12/2004
Application #:
10010392
Filing Dt:
12/07/2001
Title:
APPARATUS FOR SUPPRESSING PACKAGED SEMICONDUCTOR CHIP CURVATURE WHILE MINIMIZING THERMAL IMPEDANCE AND MAXIMIZING SPEED/RELIABILITY
29
Patent #:
Issue Dt:
11/23/2004
Application #:
10010569
Filing Dt:
11/13/2001
Title:
MEMORY MANAGEMENT SYSTEM AND METHOD FOR PROVIDING PHYSICAL ADDRESS BASED MEMORY ACCESS SECURITY
30
Patent #:
Issue Dt:
09/16/2008
Application #:
10011151
Filing Dt:
12/05/2001
Title:
SYSTEM AND METHOD FOR HANDLING DEVICE ACCESSES TO A MEMORY PROVIDING INCREASED MEMORY ACCESS SECURITY
31
Patent #:
Issue Dt:
12/02/2003
Application #:
10013354
Filing Dt:
12/13/2001
Title:
IN-SITU MONITORING DURING LASER THERMAL ANNEALING
32
Patent #:
Issue Dt:
06/29/2004
Application #:
10014064
Filing Dt:
12/10/2001
Title:
CMOS PROCESS WITH AN INTEGRATED, HIGH PERFORMANCE, SILICIDE AGGLOMERATION FUSE
33
Patent #:
Issue Dt:
11/04/2003
Application #:
10015802
Filing Dt:
12/17/2001
Title:
HYBRID SILICON ON INSULATOR/BULK STRAINED SILICON TECHNOLOGY
34
Patent #:
Issue Dt:
09/23/2003
Application #:
10016252
Filing Dt:
12/10/2001
Title:
METAL BRIDGING MONITOR FOR ETCH AND CMP ENDPOINT DETECTION
35
Patent #:
Issue Dt:
06/15/2004
Application #:
10016273
Filing Dt:
12/11/2001
Publication #:
Pub Dt:
01/15/2004
Title:
METHOD OF ENHANCING CLEAR FIELD PHASE SHIFT MASKS WITH BORDER REGIONS AROUND PHASE 0 AND PHASE 180 REGIONS
36
Patent #:
Issue Dt:
02/04/2003
Application #:
10016410
Filing Dt:
12/07/2001
Title:
SEMICONDUCTOR DEVICE WITH COPPER-FILLED VIA INCLUDES A COPPER-ZINC ALLO FILM FOR REDUCED ELECTROMIGRATION OF COPPER
37
Patent #:
Issue Dt:
11/16/2004
Application #:
10016439
Filing Dt:
12/11/2001
Title:
METHOD OF EXTENDING THE AREAS OF CLEAR FIELD PHASE SHIFT GENERATION
38
Patent #:
Issue Dt:
10/07/2003
Application #:
10016645
Filing Dt:
12/07/2001
Title:
METHOD OF REDUCING ELECTROMIGRATION BY ORDERING ZINC-DOPING IN AN ELECTROPLATED COPPER-ZINC INTERCONNECT AND A SEMICONDUCTOR DEVICE THEREBY FORMED
39
Patent #:
Issue Dt:
01/06/2004
Application #:
10016702
Filing Dt:
12/11/2001
Title:
METHOD OF ENHANCING CLEAR FIELD PHASE SHIFT MASKS BY ADDING PARALLEL LINE TO PHASE 0 REGION
40
Patent #:
Issue Dt:
03/23/2004
Application #:
10017464
Filing Dt:
12/18/2001
Title:
LASER ANNEAL PROCESS FOR REDUCTION OF POLYSILICON DEPLETION
41
Patent #:
Issue Dt:
12/07/2004
Application #:
10017855
Filing Dt:
12/14/2001
Publication #:
Pub Dt:
10/21/2004
Title:
ENHANCED TRANSISTOR GATE USING E-BEAM RADIATION
42
Patent #:
Issue Dt:
04/22/2003
Application #:
10020496
Filing Dt:
12/18/2001
Title:
TUNING ABSORPTION LEVELS DURING LASER THERMAL ANNEALING
43
Patent #:
Issue Dt:
06/29/2004
Application #:
10020551
Filing Dt:
10/30/2001
Publication #:
Pub Dt:
05/01/2003
Title:
METHOD AND APPARATUS FOR CASCADE CONTROL USING INTEGRATED METROLOGY
44
Patent #:
Issue Dt:
01/14/2003
Application #:
10020931
Filing Dt:
12/19/2001
Title:
REMOVABLE SPACER TECHNIQUE
45
Patent #:
Issue Dt:
01/11/2005
Application #:
10021497
Filing Dt:
12/19/2001
Title:
ARRAY OF GATE DIELECTRIC STRUCTURES TO MEASURE GATE DIELECTRIC THICKNESS AND PARASITIC CAPACITANCE
46
Patent #:
Issue Dt:
10/26/2004
Application #:
10021531
Filing Dt:
12/12/2001
Title:
MODEL BASED METAL OVERETCH CONTROL
47
Patent #:
Issue Dt:
12/20/2005
Application #:
10021676
Filing Dt:
12/12/2001
Title:
METHOD AND APPARATUS FOR SCHEDULING PRODUCTION LOTS BASED ON LOT AND TOOL HEALTH METRICS
48
Patent #:
Issue Dt:
03/02/2004
Application #:
10021828
Filing Dt:
12/12/2001
Title:
PHOTOSENSITIVE BOTTOM ANTI-REFLECTIVE COATING
49
Patent #:
Issue Dt:
11/11/2003
Application #:
10022321
Filing Dt:
12/13/2001
Title:
METHOD AND APPARATUS FOR COMBINING INTEGRATED AND OFFLINE METROLOGY FOR PROCESS CONTROL
50
Patent #:
Issue Dt:
04/27/2004
Application #:
10022847
Filing Dt:
12/20/2001
Title:
ELECTRICALLY PROGRAMMED MOS TRANSISTOR SOURCE/DRAIN SERIES RESISTANCE
51
Patent #:
Issue Dt:
09/07/2004
Application #:
10023098
Filing Dt:
12/17/2001
Title:
METHOD AND APPARATUS USING INTEGRATED METROLOGY DATA FOR PRE-PROCESS AND POST-PROCESS CONTROL
52
Patent #:
Issue Dt:
02/21/2006
Application #:
10023233
Filing Dt:
03/20/2002
Title:
MANAGING A CONTROLLER EMBEDDED IN A BRIDGE
53
Patent #:
Issue Dt:
08/23/2005
Application #:
10023310
Filing Dt:
12/17/2001
Title:
USING MICROCODE TO CORRECT ECC ERRORS IN A PROCESSOR
54
Patent #:
Issue Dt:
07/20/2004
Application #:
10023350
Filing Dt:
12/20/2001
Title:
SOI DEVICE WITH DIFFERENT SILICON THICKNESSES
55
Patent #:
Issue Dt:
11/18/2003
Application #:
10024675
Filing Dt:
12/18/2001
Title:
METHOD AND APPARATUS FOR DETERMINING A SAMPLING PLAN BASED ON PROCESS AND EQUIPMENT FINGERPRINTING
56
Patent #:
Issue Dt:
04/06/2004
Application #:
10028840
Filing Dt:
12/20/2001
Title:
READ-MODIFY-WRITE FOR PARTIAL WRITES IN A MEMORY CONTROLLER
57
Patent #:
Issue Dt:
11/08/2005
Application #:
10033142
Filing Dt:
11/01/2001
Title:
MICROCOMPUTER BRIDGE ARCHITECTURE WITH AN EMBEDDED MICROCONTROLLER
58
Patent #:
Issue Dt:
09/14/2004
Application #:
10034163
Filing Dt:
12/27/2001
Publication #:
Pub Dt:
10/16/2003
Title:
PREPARATION OF STACK HIGH-K GATE DIELECTRICS WITH NITRIDED LAYER
59
Patent #:
Issue Dt:
09/14/2004
Application #:
10034560
Filing Dt:
12/27/2001
Title:
I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE
60
Patent #:
Issue Dt:
08/10/2004
Application #:
10034790
Filing Dt:
12/27/2001
Title:
METHOD AND APPARATUS FOR IDENTIFYING MISREGISTRATION IN A COMPLIMENTARY PHASE SHIFT MASK PROCESS
61
Patent #:
Issue Dt:
02/15/2005
Application #:
10034967
Filing Dt:
12/27/2001
Title:
I/O NODE FOR A COMPUTER SYSTEM INCLUDING AN INTEGRATED GRAPHICS ENGINE AND AN INTEGRATED I/O HUB
62
Patent #:
Issue Dt:
12/06/2005
Application #:
10037403
Filing Dt:
01/04/2002
Title:
MICROPROCESSOR INCLUDING RETURN PREDICTION UNIT CONFIGURED TO DETERMINE WHETHER A STORED RETURN ADDRESS CORRESPONDS TO MORE THAN ONE CALL INSTRUCTION
63
Patent #:
Issue Dt:
09/21/2004
Application #:
10039525
Filing Dt:
11/07/2001
Title:
FEEDFORWARD TEMPERATURE CONTROL OF DEVICE UNDER TEST
64
Patent #:
Issue Dt:
08/31/2004
Application #:
10040002
Filing Dt:
11/07/2001
Title:
ELECTRICAL CONDUCTION ARRAY ON THE BOTTOM SIDE OF A TESTER THERMAL HEAD
65
Patent #:
Issue Dt:
09/02/2003
Application #:
10040325
Filing Dt:
11/07/2001
Title:
SURFACE PLASMON RESONANCE-BASED ENDPOINT DETECTION FOR CHEMICAL MECHANICAL PLANARIZATION (CMP)
66
Patent #:
Issue Dt:
02/04/2003
Application #:
10044532
Filing Dt:
01/11/2002
Title:
METHOD OF REDUCING INTERLAYER DIELECTRIC THICKNESS VARIATION FEEDING INTO A PLANARIZATION PROCESS
67
Patent #:
Issue Dt:
10/07/2003
Application #:
10044641
Filing Dt:
01/10/2002
Publication #:
Pub Dt:
07/10/2003
Title:
ADVANCED PROCESS CONTROL (APC) OF COPPER THICKNESS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OPTIMIZATION
68
Patent #:
Issue Dt:
12/31/2002
Application #:
10044642
Filing Dt:
01/11/2002
Title:
RUN-TO-RUN ETCH CONTROL BY FEEDING FORWARD MEASURED METAL THICKNESS
69
Patent #:
Issue Dt:
12/04/2007
Application #:
10044707
Filing Dt:
01/11/2002
Title:
PROCESSING TASKS WITH FAILURE RECOVERY
70
Patent #:
Issue Dt:
03/04/2003
Application #:
10044892
Filing Dt:
01/11/2002
Title:
MOSFETS WITH DIFFERING GATE DIELECTRICS AND METHOD OF FORMATION
71
Patent #:
Issue Dt:
06/29/2004
Application #:
10045895
Filing Dt:
10/29/2001
Publication #:
Pub Dt:
10/24/2002
Title:
METHOD OF FABRICATING COPPER-BASED SEMICONDUCTOR DEVICES USING A SACRIFICIAL DIELECTRIC LAYER
72
Patent #:
Issue Dt:
11/22/2005
Application #:
10046422
Filing Dt:
11/07/2001
Title:
METHOD OF CONTROLLING STEPPER PROCESS PARAMETERS BASED UPON OPTICAL PROPERTIES OF INCOMING ANTI-REFLECTING COATING LAYERS, AND SYSTEM FOR ACCOMPLISHING SAME
73
Patent #:
Issue Dt:
07/06/2004
Application #:
10050417
Filing Dt:
01/16/2002
Title:
METHODS AND SYSTEMS FOR CONTROLLING RESIST RESIDUE DEFECTS AT GATE LAYER IN A SEMICONDUCTOR DEVICE MANUFACTURING PROCESS
74
Patent #:
Issue Dt:
03/09/2004
Application #:
10050423
Filing Dt:
01/16/2002
Title:
SCATTEROMETRY BASED MEASUREMENTS OF A MOVING SUBSTRATE
75
Patent #:
Issue Dt:
11/11/2003
Application #:
10050438
Filing Dt:
01/16/2002
Title:
TREAT RESIST SURFACE TO PREVENT PATTERN COLLAPSE
76
Patent #:
Issue Dt:
08/10/2004
Application #:
10050453
Filing Dt:
01/16/2002
Title:
INTERLAYER DIELECTRIC VOID DETECTION
77
Patent #:
Issue Dt:
04/12/2005
Application #:
10050454
Filing Dt:
01/16/2002
Title:
SYSTEMS AND METHODS TO DETERMINE SEED LAYER THICKNESS OF TRENCH SIDEWALLS
78
Patent #:
Issue Dt:
05/25/2004
Application #:
10050458
Filing Dt:
01/16/2002
Title:
METHOD AND SYSTEM TO MONITOR AND CONTROL ELECTRO-STATIC DISCHARGE
79
Patent #:
Issue Dt:
07/06/2004
Application #:
10050471
Filing Dt:
01/16/2002
Title:
SYSTEM AND METHOD FOR DEVELOPER ENDPOINT DETECTION BY REFLECTOMETRY OR SCATTEROMETRY
80
Patent #:
Issue Dt:
06/08/2004
Application #:
10050484
Filing Dt:
01/16/2002
Title:
USE OF SURFACE COUPLING AGENT TO IMPROVE ADHESION
81
Patent #:
Issue Dt:
06/22/2004
Application #:
10050499
Filing Dt:
01/16/2002
Title:
ACOUSTIC MICROBALANCE FOR IN-SITU DEPOSITION PROCESS MONITORING AND CONTROL
82
Patent #:
Issue Dt:
08/03/2004
Application #:
10050626
Filing Dt:
01/16/2002
Title:
SCATTEROMETRY OF GRATING STRUCTURES TO MONITOR WAFER STRESS
83
Patent #:
Issue Dt:
09/17/2002
Application #:
10050732
Filing Dt:
01/16/2002
Title:
USING SCATTEROMETRY TO MEASURE RESIST THICKNESS AND CONTROL IMPLANT
84
Patent #:
Issue Dt:
05/03/2005
Application #:
10051448
Filing Dt:
01/18/2002
Title:
METHOD AND APPARATUS FOR PROTECTING PAGE TRANSLATIONS
85
Patent #:
Issue Dt:
05/06/2003
Application #:
10051549
Filing Dt:
01/18/2002
Title:
METHOD OF TOPOGRAPHY MANAGEMENT IN SEMICONDUCTOR FORMATION
86
Patent #:
Issue Dt:
11/11/2003
Application #:
10051790
Filing Dt:
01/17/2002
Title:
PREPARATION OF COMPOSITE HIGH-K / STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES
87
Patent #:
Issue Dt:
09/14/2004
Application #:
10052055
Filing Dt:
01/17/2002
Title:
DETERMINING A POSSIBLE CAUSE OF A FAULT IN A SEMICONDUCTOR FABRICATION PROCESS
88
Patent #:
Issue Dt:
05/27/2003
Application #:
10052060
Filing Dt:
01/17/2002
Title:
METHOD AND APPARATUS FOR ELECTRICALLY MEASURING INSULATING FILM THICKNESS
89
Patent #:
Issue Dt:
12/24/2002
Application #:
10052133
Filing Dt:
01/17/2002
Title:
FORMATION WITHOUT VACUUM BREAK OF SACRIFICIAL LAYER THAT DISSOLVES IN ACIDIC ACTIVATION SOLUTION WITHIN INTERCONNECT
90
Patent #:
Issue Dt:
10/14/2003
Application #:
10052142
Filing Dt:
01/17/2002
Title:
X-RAY REFLECTANCE SYSTEM TO DETERMINE SUITABILITY OF SION ARC LAYER
91
Patent #:
Issue Dt:
12/30/2003
Application #:
10052146
Filing Dt:
01/17/2002
Title:
GROWING A DUAL DAMASCENE STRUCTURE USING A COPPER SEED LAYER AND A DAMASCENE RESIST STRUCTURE
92
Patent #:
Issue Dt:
06/22/2004
Application #:
10052173
Filing Dt:
01/17/2002
Title:
IN-SITU CHEMICAL COMPOSITION MONITOR ON WAFER DURING PLASMA ETCHING FOR DEFECT CONTROL
93
Patent #:
Issue Dt:
02/20/2007
Application #:
10057393
Filing Dt:
01/25/2002
Title:
METHOD OF TRANSFERRING DATA TO MULTIPLE UNITS OPERATING IN A LOWER-FREQUENCY DOMAIN
94
Patent #:
Issue Dt:
12/09/2003
Application #:
10058048
Filing Dt:
01/29/2002
Title:
DUAL DAMASCENE METAL INTERCONNECT STRUCTURE WITH DIELECTRIC STUDS
95
Patent #:
Issue Dt:
03/30/2004
Application #:
10059268
Filing Dt:
01/31/2002
Title:
VAPOR TREATMENT FOR REPAIRING DAMAGE OF LOW-K DIELECTRIC
96
Patent #:
Issue Dt:
01/07/2003
Application #:
10059713
Filing Dt:
01/29/2002
Title:
ACCESSING FIRST CACHE WITH RETURN STACK TOP ENTRY AND SECOND CACHE WITH NESXT ENTRY UPON RETURN INSTRUCTION
97
Patent #:
Issue Dt:
08/10/2004
Application #:
10059934
Filing Dt:
01/29/2002
Title:
SYSTEM AND METHOD FOR PERFORMING A SPECULATIVE CACHE FILL
98
Patent #:
Issue Dt:
09/02/2003
Application #:
10060422
Filing Dt:
01/30/2002
Title:
TRANSISTOR HAVING A GATE STACK COMPRISED OF A METAL, AND A METHOD OF MAKING SAME
99
Patent #:
Issue Dt:
09/14/2004
Application #:
10060455
Filing Dt:
01/30/2002
Title:
METHOD OF DYNAMICALLY ENABLING ADDITIONAL SENSORS BASED UPON INITIAL SENSOR DATA, AND SYSTEM FOR ACCOMPLISHING SAME
100
Patent #:
Issue Dt:
02/10/2004
Application #:
10061348
Filing Dt:
02/04/2002
Title:
TWO-STEP PROCESS FOR NICKEL DEPOSITION
Assignor
1
Exec Dt:
06/30/2009
Assignee
1
P.O. BOX 309, UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BNK / MHKKG
P.O. BOX 398
AUSTIN, TX 78767-0398

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