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12/23/2003
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10061349
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02/04/2002
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08/28/2007
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10066948
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02/04/2002
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05/10/2005
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10067175
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02/04/2002
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12/30/2003
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10068396
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02/05/2002
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08/31/2004
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10073066
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02/12/2002
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02/24/2004
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10079358
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02/20/2002
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06/01/2004
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10079517
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02/22/2002
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06/10/2003
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10079861
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02/22/2002
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05/13/2003
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10082766
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02/25/2002
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04/14/2009
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10083149
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02/27/2002
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11/04/2003
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10083699
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02/26/2002
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05/13/2003
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10083710
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02/26/2002
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12/09/2003
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10083809
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02/26/2002
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07/20/2004
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10083914
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02/27/2002
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08/28/2003
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09/09/2003
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10084100
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02/27/2002
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07/20/2004
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10084321
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02/28/2002
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12/09/2003
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10084560
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02/25/2002
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04/06/2004
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10084563
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02/26/2002
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02/17/2004
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10085318
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02/27/2002
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09/17/2002
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10085348
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02/27/2002
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02/24/2004
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10085938
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02/28/2002
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05/13/2003
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10085949
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02/28/2002
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11/30/2004
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10085956
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02/28/2002
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08/28/2003
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05/10/2005
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10086505
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02/28/2002
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03/15/2005
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10090584
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03/04/2002
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12/14/2004
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10090692
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03/05/2002
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06/06/2006
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10091766
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03/05/2002
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12/21/2004
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10093055
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03/07/2002
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04/19/2005
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10093124
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03/07/2002
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07/06/2004
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10093125
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03/07/2002
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07/06/2004
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10093270
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03/07/2002
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06/29/2004
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10093346
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03/07/2002
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04/17/2003
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11/23/2004
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10093349
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03/07/2002
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03/04/2003
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10094061
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03/08/2002
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08/31/2004
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03/08/2002
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07/25/2002
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12/23/2003
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10095019
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03/11/2002
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07/11/2002
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04/20/2004
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03/14/2002
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05/31/2005
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03/14/2002
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04/29/2003
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03/13/2002
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03/04/2003
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03/14/2002
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01/27/2004
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03/14/2002
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10/07/2003
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03/14/2002
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09/28/2004
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03/15/2002
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02/10/2004
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10099109
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03/15/2002
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12/02/2003
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03/18/2002
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09/17/2002
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03/18/2002
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05/24/2005
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03/20/2002
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08/24/2004
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03/21/2002
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09/25/2003
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09/14/2004
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03/21/2002
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07/19/2005
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03/21/2002
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09/25/2003
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08/05/2003
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03/26/2002
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08/08/2002
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06/24/2003
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03/26/2002
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02/18/2003
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03/25/2002
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08/09/2005
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03/26/2002
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11/06/2007
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03/28/2002
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07/08/2003
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02/17/2009
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03/27/2002
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10/09/2007
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03/26/2002
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05/18/2004
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03/28/2002
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05/17/2005
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03/29/2002
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12/16/2003
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04/03/2002
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08/26/2003
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04/03/2002
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06/01/2004
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04/03/2002
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04/20/2004
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Filing Dt:
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04/03/2002
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Title:
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METHOD AND APPARATUS FOR DETERMINING A SAMPLING PLAN BASED ON DEFECTIVITY
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10116791
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Filing Dt:
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04/04/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR (SOI) WAFER HAVING A SI/SIGE/SI ACTIVE LAYER AND METHOD OF FABRICATION USING WAFER BONDING
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10118437
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Filing Dt:
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04/08/2002
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Title:
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REDUCING AGENT FOR HIGH-K GATE DIELECTRIC PARASITIC INTERFACIAL LAYER
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10121122
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Filing Dt:
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04/11/2002
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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INTERFACE VOID MONITORING IN A DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10122624
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Filing Dt:
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04/11/2002
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Title:
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APPARATUS AND METHOD FOR PROVIDING DATA TRANSFER BETWEEN TWO DIGITAL CIRCUITS WITH DIFFERENT CLOCK DOMAINS AND FOR SOLVING METASTABILITY PROBLEMS
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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10123588
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Filing Dt:
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04/16/2002
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Title:
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METHOD OF FORMING A METAL OR METAL NITRIDE INTERFACE LAYER BETWEEN SILICON NITRIDE AND COPPER
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10124216
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Filing Dt:
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04/16/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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DIE CORNER ALIGNMENT STRUCTURE
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10126211
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Filing Dt:
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04/19/2002
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Title:
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SEMICONDUCTOR DEVICE WITH NON-COMPOUNDED CONTACTS, AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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10127521
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Filing Dt:
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04/22/2002
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Title:
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INTEGRATION SCHEME FOR NON-FEATURE-SIZE-DEPENDENT CU-ALLOY INTRODUCTION
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10128662
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Filing Dt:
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04/22/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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SYSTEM AND METHOD FOR WAFER-BASED CONTROLLED PATTERNING OF FEATURES WITH CRITICAL DIMENSIONS
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10131904
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Filing Dt:
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04/25/2002
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Title:
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DETERMINATION OF THERMAL RESISTANCE FOR FIELD EFFECT TRANSISTOR FORMED IN SOI TECHNOLOGY
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10132235
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Filing Dt:
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04/25/2002
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Title:
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SELF-ALIGNED BARRIER FORMED WITH AN ALLOY HAVING AT LEAST TWO DOPANT ELEMENTS FOR MINIMIZED RESISTANCE OF INTERCONNECT
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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10133045
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Filing Dt:
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04/26/2002
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Title:
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OPERATING A PROCESSING TOOL IN A DEGRADED MODE UPON DETECTING A FAULT
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10133097
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Filing Dt:
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04/26/2002
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Title:
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FAULT NOTIFICATION BASED ON A SEVERITY LEVEL
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10134107
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Filing Dt:
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04/29/2002
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Title:
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SELECTING CONTROL ALGORITHMS BASED ON BUSINESS RULES
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10134244
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Filing Dt:
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04/29/2002
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Title:
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DYNAMIC PROCESS STATE ADJUSTMENT OF A PROCESSING TOOL TO REDUCE NON-UNIFORMITY
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10134564
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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SEMICONDUCTOR STRUCTURE AND METHOD FOR DETERMINING CRITICAL DIMENSIONS AND OVERLAY ERROR
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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10134883
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Filing Dt:
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04/29/2002
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Title:
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INTERCONNECT STRUCTURE FORMED IN POROUS DIELECTRIC MATERIAL WITH MINIMIZED DEGRADATION AND ELECTROMIGRATION
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10134973
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Filing Dt:
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04/29/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE HAVING SELECTIVE DOPANT IMPLANT IN INSULATOR LAYER AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10134981
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Filing Dt:
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04/29/2002
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Title:
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SELECTIVE THICKENING OF THE SOURCE-DRAIN AND GATE AREAS OF FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10135008
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Filing Dt:
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04/29/2002
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Title:
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SEMICONDUCTOR-ON-INSULATOR DEVICE WITH THERMOELECTRIC COOLER ON SURFACE
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10135175
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Filing Dt:
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04/30/2002
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Title:
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METHOD FOR PHOTORESIST TRIM ENDPOINT DETECTION
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10135461
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Filing Dt:
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04/30/2002
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Title:
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INTEGRATED I/O REMAPPING MECHANISM
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10135496
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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SYSTEM AND METHOD FOR LINKING SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10135497
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Filing Dt:
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04/30/2002
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Title:
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SYSTEM AND METHOD OF USING SPECULATIVE OPERAND SOURCES IN ORDER TO SPECULATIVELY BYPASS LOAD-STORE OPERATIONS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10135502
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Filing Dt:
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04/30/2002
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Title:
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HEAT SINK SUBASSEMBLY
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10138712
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Filing Dt:
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05/03/2002
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Title:
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METHOD AND SYSTEM FOR CONTROLLING A PROCESS TOOL
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10145519
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Filing Dt:
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05/14/2002
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Title:
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METHOD OF MAKING TRANSISTORS WITH GATE INSULATION LAYERS OF DIFFERING THICKNESS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10145915
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Filing Dt:
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05/15/2002
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Title:
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SOI MOSFET AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10145928
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Filing Dt:
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05/15/2002
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Title:
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METHOD OF FORMING AN ELECTROLESS NUCLEATION LAYER ON A VIA BOTTOM
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10145942
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Filing Dt:
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05/15/2002
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Title:
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INTEGRATED PROCESS FOR DEPOSITING LAYER OF HIGH-K DIELECTRIC WITH IN-SITU CONTROL OF K VALUE AND THICKNESS OF HIGH-K DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10145944
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Filing Dt:
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05/15/2002
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Title:
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METHOD OF FORMING AN ADHESION LAYER WITH AN ELEMENT REACTIVE WITH A BARRIER LAYER
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10145953
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Filing Dt:
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05/15/2002
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Title:
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SILICON-ON-INSULATOR (SOI) TRANSISTOR HAVING PARTIAL HETERO SOURCE/DRAIN JUNCTIONS FABRICATED WITH HIGH ENERGY GERMANIUM IMPLANTATION
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10146029
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Filing Dt:
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05/16/2002
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Title:
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FORMATION OF HIGH-K GATE DIELECTRIC LAYERS FOR MOS DEVICES FABRICATED ON STRAINED LATTICE SEMICONDUCTOR SUBSTRATES WITH MINIMIZED STRESS RELAXATION
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10147382
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Filing Dt:
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05/15/2002
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Title:
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SILICIDE-SILICON CONTACTS FOR REDUCTION OF MOSFET SOURCE-DRAIN RESISTANCES
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10150320
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Filing Dt:
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05/17/2002
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Title:
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METHOD AND APPARATUS FOR CONTROLLING COPPER BARRIER/SEED DEPOSITION PROCESSES
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