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Reel/Frame:023119/0083   Pages: 180
Recorded: 08/18/2009
Attorney Dkt #:6363-00000
Conveyance: AFFIRMATION OF PATENT ASSIGNMENT
Total properties: 2907
Page 26 of 30
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1
Patent #:
Issue Dt:
03/02/2004
Application #:
10375219
Filing Dt:
02/26/2003
Publication #:
Pub Dt:
08/07/2003
Title:
CONDUCTOR ABRASIVELESS CHEMICAL-MECHANICAL POLISHING IN INTEGRATED CIRCUIT INTERCONNECTS
2
Patent #:
Issue Dt:
03/16/2004
Application #:
10376399
Filing Dt:
02/28/2003
Title:
METHOD FOR FORMING AN ALLOYED METAL CONDUCTIVE ELEMENT OF AN INTEGRATED CIRCUIT
3
Patent #:
Issue Dt:
04/27/2004
Application #:
10379239
Filing Dt:
03/03/2003
Publication #:
Pub Dt:
07/24/2003
Title:
SELF-ALIGNED TRIPLE GATE SILICON-ON-INSULATOR (SOI) DEVICE
4
Patent #:
Issue Dt:
10/09/2007
Application #:
10379757
Filing Dt:
03/05/2003
Title:
METHOD FOR FORMING INLAID STRUCTURES FOR IC INTERCONNECTIONS
5
Patent #:
Issue Dt:
04/20/2004
Application #:
10379792
Filing Dt:
03/06/2003
Title:
METHOD FOR REDUCING GATE OXIDE SURFACE IRREGULARITIES
6
Patent #:
Issue Dt:
09/04/2007
Application #:
10379977
Filing Dt:
03/05/2003
Title:
PROGRAMMABLE PATTERN GENERATION FOR DYNAMIC BUS SIGNAL INTEGRITY ANALYSIS
7
Patent #:
Issue Dt:
08/31/2004
Application #:
10383119
Filing Dt:
03/05/2003
Title:
POLARIZATION MEASUREMENT DEVICE AND METHOD
8
Patent #:
Issue Dt:
08/10/2004
Application #:
10384350
Filing Dt:
03/07/2003
Title:
METHOD AND STRUCTURE FOR LOW-K DIELECTRIC CONSTANT APPLICATIONS
9
Patent #:
Issue Dt:
11/22/2005
Application #:
10384398
Filing Dt:
03/07/2003
Publication #:
Pub Dt:
09/09/2004
Title:
METHOD FOR FORMING A LOW-K DIELECTRIC STRUCTURE ON A SUBSTRATE
10
Patent #:
Issue Dt:
10/05/2004
Application #:
10385652
Filing Dt:
03/12/2003
Title:
ASYMMETRICAL DOUBLE GATE OR ALL-AROUND GATE MOSFET DEVICES AND METHODS FOR MAKING SAME
11
Patent #:
Issue Dt:
09/07/2004
Application #:
10385753
Filing Dt:
03/12/2003
Title:
METHOD FOR FORMING A FIN IN A FINFET DEVICE
12
Patent #:
Issue Dt:
09/09/2008
Application #:
10389456
Filing Dt:
03/14/2003
Publication #:
Pub Dt:
09/16/2004
Title:
METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS
13
Patent #:
Issue Dt:
12/12/2006
Application #:
10400598
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
03/11/2004
Title:
SEMICONDUCTOR DEVICE HAVING T-SHAPED GATE STRUCTURE COMPRISING IN SITU SIDEWALL SPACERS AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
14
Patent #:
Issue Dt:
08/03/2004
Application #:
10400706
Filing Dt:
03/27/2003
Publication #:
Pub Dt:
03/11/2004
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING T-SHAPED GATE STRUCTURE
15
Patent #:
Issue Dt:
05/29/2007
Application #:
10402166
Filing Dt:
03/26/2003
Publication #:
Pub Dt:
09/30/2004
Title:
HIGH EMISSIVITY CAPACITOR STRUCTURE
16
Patent #:
Issue Dt:
01/04/2005
Application #:
10402585
Filing Dt:
03/28/2003
Publication #:
Pub Dt:
04/01/2004
Title:
CIRCUIT ELEMENT HAVING A METAL SILICIDE REGION THERMALLY STABILIZED BY A BARRIER DIFFUSION MATERIAL
17
Patent #:
Issue Dt:
06/28/2005
Application #:
10403556
Filing Dt:
03/31/2003
Publication #:
Pub Dt:
03/04/2004
Title:
TRANSISTOR ELEMENT HAVING AN ANISOTROPIC HIGH-K GATE DIELECTRIC
18
Patent #:
Issue Dt:
11/02/2004
Application #:
10403584
Filing Dt:
03/31/2003
Publication #:
Pub Dt:
01/29/2004
Title:
METHOD OF FILLING AN OPENING IN A MATERIAL LAYER WITH AN INSULATING MATERIAL
19
Patent #:
Issue Dt:
04/04/2006
Application #:
10405295
Filing Dt:
04/02/2003
Title:
DYNAMICALLY ADJUSTABLE PROBE TIPS
20
Patent #:
Issue Dt:
11/06/2007
Application #:
10406131
Filing Dt:
04/03/2003
Title:
BMC-HOSTED BOOT ROM INTERFACE
21
Patent #:
Issue Dt:
01/11/2005
Application #:
10407754
Filing Dt:
04/04/2003
Title:
METHOD AND APPARATUS FOR FULLY ALIGNED FLIP-CHIP ASSEMBLY HAVING A VARIABLE PITCH PACKAGING SUBSTRATE
22
Patent #:
Issue Dt:
05/04/2004
Application #:
10414039
Filing Dt:
04/16/2003
Title:
HEAT SINK FASTENER
23
Patent #:
Issue Dt:
10/31/2006
Application #:
10419091
Filing Dt:
04/18/2003
Title:
METHOD FOR SELECTIVELY DISABLING INTERRUPTS ON A SECURE EXECUTION MODE-CAPABLE PROCESSOR
24
Patent #:
Issue Dt:
02/24/2009
Application #:
10419120
Filing Dt:
04/18/2003
Title:
METHOD AND APPARATUS FOR CONTROLLING OPERATION OF A SECURE EXECUTION MODE-CAPABLE PROCESSOR IN SYSTEM MANAGEMENT MODE
25
Patent #:
Issue Dt:
01/16/2007
Application #:
10419122
Filing Dt:
04/18/2003
Title:
METHOD AND APPARATUS FOR CONTROLLING INTERRUPTS IN A SECURE EXECUTION MODE-CAPABLE PROCESSOR
26
Patent #:
Issue Dt:
03/14/2006
Application #:
10419534
Filing Dt:
04/21/2003
Title:
METAL BRIDGING MONITOR FOR ETCH AND CMP ENDPOINT DETECTION
27
Patent #:
Issue Dt:
08/09/2005
Application #:
10420214
Filing Dt:
04/22/2003
Publication #:
Pub Dt:
03/04/2004
Title:
LOW-K DIELECTRIC LAYER STACK INCLUDING AN ETCH INDICATOR LAYER FOR USE IN THE DUAL DAMASCENE TECHNIQUE
28
Patent #:
Issue Dt:
07/04/2006
Application #:
10420721
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
10/28/2004
Title:
METHOD OF FORMING A METAL GATE STRUCTURE WITH TUNING OF WORK FUNCTION BY SILICON INCORPORATION
29
Patent #:
Issue Dt:
06/08/2004
Application #:
10422492
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
03/04/2004
Title:
SEMICONDUCTOR DEVICE HAVING A POLYSILICON LINE STRUCTURE WITH INCREASED METAL SILICIDE PORTIONS AND METHOD FOR FORMING THE POLYSILICON LINE STRUCTURE OF A SEMICONDUCTOR DEVICE
30
Patent #:
Issue Dt:
04/25/2006
Application #:
10423993
Filing Dt:
04/25/2003
Title:
SYSTEM AND METHOD FOR FACILITATING COMMUNICATION ACROSS AN ASYNCHRONOUS CLOCK BOUNDARY
31
Patent #:
Issue Dt:
03/21/2006
Application #:
10424420
Filing Dt:
04/28/2003
Title:
USE OF AMORPHOUS CARBON FOR GATE PATTERNING
32
Patent #:
Issue Dt:
11/30/2004
Application #:
10424675
Filing Dt:
04/28/2003
Title:
SELECTIVE STRESS-INDUCING IMPLANT AND RESULTING PATTERN DISTORTION IN AMORPHOUS CARBON PATTERNING
33
Patent #:
Issue Dt:
06/14/2005
Application #:
10425227
Filing Dt:
05/02/2003
Title:
METHOD AND APPARATUS FOR MODIFYING DESIGN CONSTRAINTS BASED ON OBSERVED PERFORMANCE
34
Patent #:
Issue Dt:
11/28/2006
Application #:
10426010
Filing Dt:
04/29/2003
Title:
APPARATUS AND METHOD FOR VIEWING DATA PROCESSOR BUS TRANSACTIONS ON ADDRESS PINS DURING MEMORY IDLE CYCLES
35
Patent #:
Issue Dt:
09/12/2006
Application #:
10426040
Filing Dt:
04/29/2003
Title:
BUS ARCHITECTURE USING DEBUG PACKETS TO MONITOR TRANSACTIONS ON AN INTERNAL DATA PROCESSOR BUS
36
Patent #:
Issue Dt:
02/28/2006
Application #:
10426049
Filing Dt:
04/29/2003
Title:
PRECISION BYPASS CLOCK FOR HIGH SPEED TESTING OF A DATA PROCESSOR
37
Patent #:
Issue Dt:
05/02/2006
Application #:
10426487
Filing Dt:
04/30/2003
Title:
APPARATUS AND METHOD FOR INITIATING A SLEEP STATE IN A SYSTEM ON A CHIP DEVICE
38
Patent #:
Issue Dt:
05/30/2006
Application #:
10426755
Filing Dt:
04/30/2003
Title:
SYSTEM AND METHOD FOR BLOCKING CACHE USE DURING DEBUGGING
39
Patent #:
Issue Dt:
10/19/2004
Application #:
10428270
Filing Dt:
05/02/2003
Title:
EUV MASK WHICH FACILITATES ELECTRO-STATIC CHUCKING
40
Patent #:
Issue Dt:
02/19/2008
Application #:
10429132
Filing Dt:
05/02/2003
Publication #:
Pub Dt:
12/09/2004
Title:
COMPUTER SYSTEM INCLUDING A BUS BRIDGE FOR CONNECTION TO A SECURITY SERVICES PROCESSOR
41
Patent #:
Issue Dt:
09/04/2007
Application #:
10429159
Filing Dt:
05/02/2003
Publication #:
Pub Dt:
11/04/2004
Title:
SPECULATION POINTERS TO IDENTIFY DATA-SPECULATIVE OPERATIONS IN MICROPROCESSOR
42
Patent #:
Issue Dt:
02/19/2008
Application #:
10434692
Filing Dt:
05/09/2003
Title:
APPARATUS AND METHOD FOR BALANCED SPINLOCK SUPPORT IN NUMA SYSTEMS
43
Patent #:
Issue Dt:
10/18/2005
Application #:
10438860
Filing Dt:
05/16/2003
Title:
LASER THERMAL ANNEALING METHOD FOR FORMING SEMICONDUCTOR LOW-K DIELECTRIC LAYER
44
Patent #:
Issue Dt:
09/28/2004
Application #:
10440847
Filing Dt:
05/19/2003
Title:
NICKEL ALLOY FOR SMOS PROCESS SILICIDATION
45
Patent #:
Issue Dt:
03/15/2005
Application #:
10441755
Filing Dt:
05/20/2003
Publication #:
Pub Dt:
05/27/2004
Title:
TEST STRUCTURE FOR DETERMINING THE STABILITY OF ELECTRONIC DEVICES COMPRISING CONNECTED SUBSTRATES
46
Patent #:
Issue Dt:
07/19/2005
Application #:
10442131
Filing Dt:
05/21/2003
Publication #:
Pub Dt:
11/25/2004
Title:
MULTIPLE-GATE MOS DEVICE AND METHOD FOR MAKING THE SAME
47
Patent #:
Issue Dt:
02/01/2005
Application #:
10442745
Filing Dt:
05/21/2003
Publication #:
Pub Dt:
06/03/2004
Title:
METHOD OF FORMING DRAIN/SOURCE EXTENSION STRUCTURES OF A FIELD EFFECT TRANSISTOR USING A DOPED HIGH-K DIELECTRIC LAYER
48
Patent #:
Issue Dt:
08/30/2005
Application #:
10442975
Filing Dt:
05/22/2003
Title:
STRAINED-SILICON DEVICE WITH DIFFERENT SILICON THICKNESSES
49
Patent #:
Issue Dt:
04/20/2004
Application #:
10443642
Filing Dt:
05/22/2003
Title:
TECHNIQUE FOR FORMING AN OXIDE/NITRIDE LAYER STACK BY CONTROLLING THE NITROGEN ION CONCENTRATION IN A NITRIDATION PLASMA
50
Patent #:
Issue Dt:
09/13/2005
Application #:
10444191
Filing Dt:
05/23/2003
Publication #:
Pub Dt:
06/24/2004
Title:
TRENCH ISOLATION STRUCTURE FOR A SEMICONDUCTOR DEVICE WITH A DIFFERENT DEGREE OF CORNER ROUNDING AND A METHOD OF MANUFACTURING THE SAME
51
Patent #:
Issue Dt:
11/21/2006
Application #:
10447047
Filing Dt:
05/28/2003
Publication #:
Pub Dt:
12/02/2004
Title:
METHOD OF FABRICATING BODY-TIED SOI TRANSISTOR HAVING HALO IMPLANT REGION UNDERLYING HAMMERHEAD PORTION OF GATE
52
Patent #:
Issue Dt:
03/22/2005
Application #:
10458802
Filing Dt:
06/16/2003
Title:
FIXTURE SUITABLE FOR USE IN COUPLING A LID TO A SUBSTRATE AND METHOD
53
Patent #:
Issue Dt:
07/27/2004
Application #:
10459328
Filing Dt:
06/11/2003
Title:
METHOD FOR FORMING DUAL INLAID STRUCTURES FOR IC INTERCONNECTIONS
54
Patent #:
Issue Dt:
02/15/2005
Application #:
10459495
Filing Dt:
06/12/2003
Publication #:
Pub Dt:
12/16/2004
Title:
MULTI-STEP CHEMICAL MECHANICAL POLISHING OF A GATE AREA IN A FINFET
55
Patent #:
Issue Dt:
06/29/2004
Application #:
10459579
Filing Dt:
06/12/2003
Title:
DUAL SILICON LAYER FOR CHEMICAL MECHANICAL POLISHING PLANARIZATION
56
Patent #:
Issue Dt:
03/15/2005
Application #:
10460165
Filing Dt:
06/13/2003
Title:
POLYSILICON TILING TO PREVENT GEOMETRY EFFECTS DURING LASER THERMAL ANNEALING
57
Patent #:
Issue Dt:
11/28/2006
Application #:
10460500
Filing Dt:
06/11/2003
Title:
PARAMETER LINKING SYSTEM FOR DATA VISUALIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
58
Patent #:
Issue Dt:
11/09/2004
Application #:
10460615
Filing Dt:
06/11/2003
Title:
METHOD OF SIMULTANEOUS DISPLAY OF DIE AND WAFER CHARACTERIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
59
Patent #:
Issue Dt:
12/14/2004
Application #:
10462667
Filing Dt:
06/17/2003
Title:
GATE DIELECTRIC QUALITY FOR REPLACEMENT METAL GATE TRANSISTORS
60
Patent #:
Issue Dt:
04/18/2006
Application #:
10463910
Filing Dt:
06/16/2003
Publication #:
Pub Dt:
06/24/2004
Title:
METHOD OF FORMING A CAP LAYER HAVING ANTI-REFLECTIVE CHARACTERISTICS ON TOP OF A LOW-K DIELECTRIC
61
Patent #:
Issue Dt:
07/05/2005
Application #:
10601401
Filing Dt:
06/23/2003
Publication #:
Pub Dt:
01/06/2005
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
62
Patent #:
Issue Dt:
11/23/2004
Application #:
10602577
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
08/05/2004
Title:
METHOD OF ASSESSING LATERAL DOPANT AND/OR CHARGE CARRIER PROFILES
63
Patent #:
Issue Dt:
10/26/2004
Application #:
10602583
Filing Dt:
06/24/2003
Publication #:
Pub Dt:
07/01/2004
Title:
SEMICONDUCTOR DEVICE HAVING AN IMPROVED STRAINED SURFACE LAYER AND METHOD OF FORMING A STRAINED SURFACE LAYER IN A SEMICONDUCTOR DEVICE
64
Patent #:
Issue Dt:
05/24/2005
Application #:
10609719
Filing Dt:
06/30/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METHODS OF FORMING A TRANSISTOR HAVING A RECESSED GATE ELECTRODE STRUCTURE
65
Patent #:
Issue Dt:
07/20/2004
Application #:
10610942
Filing Dt:
07/01/2003
Title:
METHOD AND APPARATUS FOR DETECTING NECKING OVER FIELD/ACTIVE TRANSITIONS
66
Patent #:
Issue Dt:
04/06/2004
Application #:
10613997
Filing Dt:
07/08/2003
Title:
METHOD FOR FORMING CHANNELS IN A FINFET DEVICE
67
Patent #:
Issue Dt:
08/30/2005
Application #:
10614001
Filing Dt:
07/08/2003
Title:
SELECTIVE SILICIDATION OF GATES IN SEMICONDUCTOR DEVICES TO ACHIEVE MULTIPLE THRESHOLD VOLTAGES
68
Patent #:
Issue Dt:
05/16/2006
Application #:
10614031
Filing Dt:
07/08/2003
Title:
METHOD FOR DETERMINING METAL WORK FUNCTION BY FORMATION OF SCHOTTKY DIODES WITH SHADOW MASK
69
Patent #:
Issue Dt:
06/26/2007
Application #:
10614051
Filing Dt:
07/08/2003
Title:
METHOD FOR DOPING STRUCTURES IN FINFET DEVICES
70
Patent #:
Issue Dt:
01/22/2008
Application #:
10615101
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/13/2005
Title:
STORE-TO-LOAD FORWARDING BUFFER USING INDEXED LOOKUP
71
Patent #:
Issue Dt:
10/24/2006
Application #:
10617485
Filing Dt:
07/11/2003
Publication #:
Pub Dt:
02/05/2004
Title:
ACCUMULATOR CONTROLLED PRESCALER IN A PHASED LOCKED LOOP
72
Patent #:
Issue Dt:
01/10/2006
Application #:
10619843
Filing Dt:
07/15/2003
Title:
METHOD AND APPARATUS FOR ADAPTIVE SAMPLING BASED ON PROCESS COVARIANCE
73
Patent #:
Issue Dt:
07/26/2005
Application #:
10620194
Filing Dt:
07/15/2003
Title:
FRONT SIDE SEAL TO PREVENT GERMANIUM OUTGASSING
74
Patent #:
Issue Dt:
01/10/2006
Application #:
10624420
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD OF FORMING A CONDUCTIVE BARRIER LAYER HAVING IMPROVED COVERAGE WITHIN CRITICAL OPENINGS
75
Patent #:
Issue Dt:
06/20/2006
Application #:
10624712
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
08/05/2004
Title:
TECHNIQUE FOR FORMING CONTACTS FOR BURIED DOPED REGIONS IN A SEMICONDUCTOR DEVICE
76
Patent #:
Issue Dt:
05/09/2006
Application #:
10624776
Filing Dt:
07/22/2003
Publication #:
Pub Dt:
06/24/2004
Title:
METHOD OF REMOVING FEATURES USING AN IMPROVED REMOVAL PROCESS IN THE FABRICATION OF A SEMICONDUCTOR DEVICE
77
Patent #:
Issue Dt:
08/30/2005
Application #:
10626371
Filing Dt:
07/23/2003
Title:
SEMICONDUCTOR DEVICE HAVING COPPER LINES WITH REDUCED ELECTROMIGRATION USING AN ELECTROPLATED INTERIM COPPER-ZINC ALLOY THIN FILM ON A COPPER SURFACE
78
Patent #:
Issue Dt:
02/28/2006
Application #:
10628021
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
01/27/2005
Title:
METHOD AND APPARATUS FOR MONITORING AND CONTROLLING IMAGING IN IMMERSION LITHOGRAPHY SYSTEMS
79
Patent #:
Issue Dt:
11/13/2007
Application #:
10628715
Filing Dt:
07/28/2003
Publication #:
Pub Dt:
02/05/2004
Title:
FLEXIBLE PROBE/PROBE RESPONSE ROUTING FOR MAINTAINING COHERENCY
80
Patent #:
Issue Dt:
06/14/2005
Application #:
10629436
Filing Dt:
07/29/2003
Publication #:
Pub Dt:
09/30/2004
Title:
DIODE STRUCTURE FOR SOI CIRCUITS
81
Patent #:
Issue Dt:
04/05/2005
Application #:
10632471
Filing Dt:
08/01/2003
Title:
TESTING MULTIPLE LEVELS IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
82
Patent #:
Issue Dt:
04/07/2009
Application #:
10633498
Filing Dt:
08/05/2003
Title:
SYSTEMS AND METHODS FOR COMMUNICATING IN A DISCRETE MULTITONE SYSTEM
83
Patent #:
Issue Dt:
12/28/2004
Application #:
10633499
Filing Dt:
08/05/2003
Title:
EPITAXIALLY GROWN FIN FOR FINFET
84
Patent #:
Issue Dt:
02/15/2005
Application #:
10633503
Filing Dt:
08/05/2003
Title:
METHOD FOR FORMING TRI-GATE FINFET WITH MESA ISOLATION
85
Patent #:
Issue Dt:
08/22/2006
Application #:
10633504
Filing Dt:
08/05/2003
Publication #:
Pub Dt:
02/10/2005
Title:
VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS
86
Patent #:
Issue Dt:
09/21/2004
Application #:
10633981
Filing Dt:
08/04/2003
Title:
METHOD FOR ASYMMETRIC SPACER FORMATION
87
Patent #:
Issue Dt:
01/17/2006
Application #:
10634013
Filing Dt:
08/04/2003
Publication #:
Pub Dt:
02/10/2005
Title:
DYNAMIC METROLOGY SAMPLING METHODS, AND SYSTEM FOR PERFORMING SAME
88
Patent #:
Issue Dt:
09/20/2005
Application #:
10634038
Filing Dt:
08/04/2003
Title:
DYNAMIC METROLOGY SAMPLING TECHNIQUES FOR IDENTIFIED LOTS, AND SYSTEM FOR PERFORMING SAME
89
Patent #:
Issue Dt:
06/13/2006
Application #:
10638927
Filing Dt:
08/11/2003
Publication #:
Pub Dt:
02/17/2005
Title:
METHOD AND APPARATUS FOR MONITORING AND CONTROLLING IMAGING IN IMMERSION LITHOGRAPHY SYSTEMS
90
Patent #:
Issue Dt:
09/12/2006
Application #:
10639128
Filing Dt:
08/12/2003
Title:
METHOD FOR EFFICIENT BUFFER TAG ALLOCATION
91
Patent #:
Issue Dt:
08/02/2005
Application #:
10642375
Filing Dt:
08/15/2003
Title:
STRAINED SILICON MOSFET HAVING REDUCED LEAKAGE AND METHOD OF ITS FORMATION
92
Patent #:
Issue Dt:
01/10/2006
Application #:
10642916
Filing Dt:
08/18/2003
Publication #:
Pub Dt:
04/07/2005
Title:
SHALLOW TRENCH ISOLATION (STI) REGION WITH HIGH-K LINER AND METHOD OF FORMATION
93
Patent #:
Issue Dt:
01/18/2005
Application #:
10645363
Filing Dt:
08/21/2003
Title:
REFRACTIVE INDEX SYSTEM MONITOR AND CONTROL FOR IMMERSION LITHOGRAPHY
94
Patent #:
Issue Dt:
07/29/2008
Application #:
10645364
Filing Dt:
08/21/2003
Title:
COMBINATION OF NON-LITHOGRAPHIC SHRINK TECHNIQUES AND TRIM PROCESS FOR GATE FORMATION AND LINE-EDGE ROUGHNESS REDUCTION
95
Patent #:
Issue Dt:
05/17/2005
Application #:
10649049
Filing Dt:
08/27/2003
Publication #:
Pub Dt:
08/26/2004
Title:
SOFT ERROR RESISTANT SEMICONDUCTOR DEVICE
96
Patent #:
Issue Dt:
04/05/2005
Application #:
10653105
Filing Dt:
09/03/2003
Title:
ADDITIONAL GATE CONTROL FOR A DOUBLE-GATE MOSFET
97
Patent #:
Issue Dt:
02/14/2006
Application #:
10653225
Filing Dt:
09/03/2003
Title:
METHOD FOR FORMING A TRI-GATE MOSFET
98
Patent #:
Issue Dt:
02/21/2006
Application #:
10653309
Filing Dt:
09/02/2003
Publication #:
Pub Dt:
03/03/2005
Title:
SYSTEM AND METHOD OF PATTERN RECOGNITION AND METROLOGY STRUCTURE FOR AN X-INITIATIVE LAYOUT DESIGN
99
Patent #:
Issue Dt:
10/03/2006
Application #:
10653749
Filing Dt:
09/03/2003
Publication #:
Pub Dt:
03/03/2005
Title:
MICROTLB AND MICRO TAG FOR REDUCING POWER IN A PROCESSOR
100
Patent #:
Issue Dt:
03/29/2005
Application #:
10653802
Filing Dt:
09/03/2003
Title:
CIRCULAR BUFFER USING GROUPING FOR FIND FIRST FUNCTION
Assignor
1
Exec Dt:
06/30/2009
Assignee
1
P.O. BOX 309, UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
BNK / MHKKG
P.O. BOX 398
AUSTIN, TX 78767-0398

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