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Reel/Frame:	023119/0083			Pages:	180
		Recorded:	08/18/2009
Attorney Dkt #:	6363-00000
Conveyance:	AFFIRMATION OF PATENT ASSIGNMENT

Total properties: 2907
Page 27 of 30
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Patent #:	7014966	Issue Dt:	03/21/2006	Application #:	10653844	Filing Dt:	09/02/2003
Publication #:	US20050048223	Pub Dt:	03/03/2005
Title:	METHOD AND APPARATUS FOR ELIMINATION OF BUBBLES IN IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY SYSTEMS

Patent #:	6955969	Issue Dt:	10/18/2005	Application #:	10654497	Filing Dt:	09/03/2003
Publication #:	US20050048743	Pub Dt:	03/03/2005
Title:	METHOD OF GROWING AS A CHANNEL REGION TO REDUCE SOURCE/DRAIN JUNCTION CAPACITANCE

Patent #:	7051300	Issue Dt:	05/23/2006	Application #:	10655390	Filing Dt:	09/04/2003
Title:	METHOD AND SYSTEM FOR ARCHITECTURAL POWER ESTIMATION

Patent #:	6849925	Issue Dt:	02/01/2005	Application #:	10656470	Filing Dt:	09/05/2003
Title:	PREPARATION OF COMPOSITE HIGH-K/STANDARD-K DIELECTRICS FOR SEMICONDUCTOR DEVICES

Patent #:	7012007	Issue Dt:	03/14/2006	Application #:	10658479	Filing Dt:	09/09/2003
Title:	STRAINED SILICON MOSFET HAVING IMPROVED THERMAL CONDUCTIVITY AND METHOD FOR ITS FABRICATION

Patent #:	6954879	Issue Dt:	10/11/2005	Application #:	10661894	Filing Dt:	09/12/2003
Title:	METHOD AND APPARATUS FOR COMMUNICATING CONFIGURATION DATA FOR A PERIPHERAL DEVICE OF A MICROCONTROLLER VIA A SCAN PATH

Patent #:	7146440	Issue Dt:	12/05/2006	Application #:	10663611	Filing Dt:	09/16/2003
Title:	DMA ACKNOWLEDGE SIGNAL FOR AN IDE DEVICE

Patent #:	7093209	Issue Dt:	08/15/2006	Application #:	10663613	Filing Dt:	09/16/2003
Publication #:	US20050060673	Pub Dt:	03/17/2005
Title:	METHOD AND APPARATUS FOR PACKAGING TEST INTEGRATED CIRCUITS

Patent #:	6960802	Issue Dt:	11/01/2005	Application #:	10663614	Filing Dt:	09/16/2003
Title:	PERFORMING PASSIVE VOLTAGE CONTRAST ON A SILICON ON INSULATOR SEMICONDUCTOR DEVICE

Patent #:	7205165	Issue Dt:	04/17/2007	Application #:	10664665	Filing Dt:	09/18/2003
Title:	METHOD FOR DETERMINING THE RELIABILITY OF DIELECTRIC LAYERS

Patent #:	6943096	Issue Dt:	09/13/2005	Application #:	10665938	Filing Dt:	09/17/2003
Title:	SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

Patent #:	6958247	Issue Dt:	10/25/2005	Application #:	10666195	Filing Dt:	09/19/2003
Publication #:	US20040214423	Pub Dt:	10/28/2004
Title:	METHOD OF ELECTROPLATING COPPER OVER A PATTERNED DIELECTRIC LAYER TO ENHANCE PROCESS UNIFORMITY OF A SUBSEQUENT CMP PROCESS

Patent #:	6995438	Issue Dt:	02/07/2006	Application #:	10674478	Filing Dt:	10/01/2003
Title:	SEMICONDUCTOR DEVICE WITH FULLY SILICIDED SOURCE/DRAIN AND DAMASCENE METAL GATE

Patent #:	6855989	Issue Dt:	02/15/2005	Application #:	10674520	Filing Dt:	10/01/2003
Title:	DAMASCENE FINFET GATE WITH SELECTIVE METAL INTERDIFFUSION

Patent #:	7133969	Issue Dt:	11/07/2006	Application #:	10676437	Filing Dt:	10/01/2003
Publication #:	US20050076180	Pub Dt:	04/07/2005
Title:	SYSTEM AND METHOD FOR HANDLING EXCEPTIONAL INSTRUCTIONS IN A TRACE CACHE BASED PROCESSOR

Patent #:	7069155	Issue Dt:	06/27/2006	Application #:	10676455	Filing Dt:	10/01/2003
Title:	REAL TIME ANALYTICAL MONITOR FOR SOFT DEFECTS ON RETICLE DURING RETICLE INSPECTION

Patent #:	7187796	Issue Dt:	03/06/2007	Application #:	10676613	Filing Dt:	10/01/2003
Title:	SYSTEMS AND METHODS THAT EMPLOY EXPOSURE COMPENSATION TO PROVIDE UNIFORM CD CONTROL ON RETICLE DURING FABRICATION

Patent #:	7043626	Issue Dt:	05/09/2006	Application #:	10676636	Filing Dt:	10/01/2003
Title:	Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Patent #:	7056646	Issue Dt:	06/06/2006	Application #:	10676749	Filing Dt:	10/01/2003
Title:	USE OF BASE DEVELOPERS AS IMMERSION LITHOGRAPHY FLUID

Patent #:	6967363	Issue Dt:	11/22/2005	Application #:	10676904	Filing Dt:	10/01/2003
Title:	LATERAL DIODE WITH MULTIPLE SPACERS

Patent #:	6764946	Issue Dt:	07/20/2004	Application #:	10676911	Filing Dt:	10/01/2003
Title:	METHOD OF CONTROLLING LINE EDGE ROUGHNESS IN RESIST FILMS

Patent #:	6879406	Issue Dt:	04/12/2005	Application #:	10677041	Filing Dt:	10/01/2003
Title:	USE OF SCATTEROMETRY AS A CONTROL TOOL IN THE MANUFACTURE OF EXTREME UV MASKS

Patent #:	6849469	Issue Dt:	02/01/2005	Application #:	10677043	Filing Dt:	10/01/2003
Title:	MONITOR AND CONTROL OF SILICIDATION USING FOURIER TRANSFORM INFRARED SCATTEROMETRY

Patent #:	6953755	Issue Dt:	10/11/2005	Application #:	10677911	Filing Dt:	10/02/2003
Publication #:	US20050072919	Pub Dt:	04/07/2005
Title:	TECHNIQUE FOR MONITORING THE STATE OF METAL LINES IN MICROSTRUCTURES

Patent #:	6902977	Issue Dt:	06/07/2005	Application #:	10678445	Filing Dt:	10/03/2003
Title:	METHOD FOR FORMING POLYSILICON GATE ON HIGH-K DIELECTRIC AND RELATED STRUCTURE

Patent #:	6849527	Issue Dt:	02/01/2005	Application #:	10684727	Filing Dt:	10/14/2003
Title:	STRAINED SILICON MOSFET HAVING IMPROVED CARRIER MOBILITY, STRAINED SILICON CMOS DEVICE, AND METHODS OF THEIR FORMATION

Patent #:	7169706	Issue Dt:	01/30/2007	Application #:	10687186	Filing Dt:	10/16/2003
Publication #:	US20050085073	Pub Dt:	04/21/2005
Title:	METHOD OF USING AN ADHESION PRECURSOR LAYER FOR CHEMICAL VAPOR DEPOSITION (CVD) COPPER DEPOSITION

Patent #:	6833625	Issue Dt:	12/21/2004	Application #:	10690434	Filing Dt:	10/21/2003
Title:	SELF-ALIGNED BARRIER FORMED WITH AN ALLOY HAVING AT LEAST TWO DOPANT ELEMENTS FOR MINIMIZED RESISTANCE OF INTERCONNECT

Patent #:	6974652	Issue Dt:	12/13/2005	Application #:	10699748	Filing Dt:	11/03/2003
Title:	LITHOGRAPHIC PHOTOMASK AND METHOD OF MANUFACTURE TO IMPROVE PHOTOMASK TEST MEASUREMENT

Patent #:	6984475	Issue Dt:	01/10/2006	Application #:	10699767	Filing Dt:	11/03/2003
Title:	EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY MASKS

Patent #:	7029958	Issue Dt:	04/18/2006	Application #:	10699887	Filing Dt:	11/04/2003
Publication #:	US20050104091	Pub Dt:	05/19/2005
Title:	SELF ALIGNED DAMASCENE GATE

Patent #:	7328339	Issue Dt:	02/05/2008	Application #:	10699947	Filing Dt:	11/03/2003
Title:	METHOD OF TESTING THE ENCRYPTION FUNCTION OF A DEVICE

Patent #:	6960774	Issue Dt:	11/01/2005	Application #:	10700175	Filing Dt:	11/03/2003
Publication #:	US20050092939	Pub Dt:	05/05/2005
Title:	FAULT DETECTION AND CONTROL METHODOLOGIES FOR ION IMPLANTATION PROCESSES, AND SYSTEM FOR PERFORMING SAME

Patent #:	7284117	Issue Dt:	10/16/2007	Application #:	10700391	Filing Dt:	11/04/2003
Title:	PROCESSOR THAT PREDICTS FLOATING POINT INSTRUCTION LATENCY BASED ON PREDICTED PRECISION

Patent #:	6969678	Issue Dt:	11/29/2005	Application #:	10700711	Filing Dt:	11/03/2003
Title:	MULTI-SILICIDE IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	6812550	Issue Dt:	11/02/2004	Application #:	10700733	Filing Dt:	11/03/2003
Title:	WAFER PATTERN VARIATION OF INTEGRATED CIRCUIT FABRICATION

Patent #:	7197727	Issue Dt:	03/27/2007	Application #:	10700902	Filing Dt:	11/04/2003
Title:	INTERCONNECT SPEED SENSING CIRCUITRY

Patent #:	6991946	Issue Dt:	01/31/2006	Application #:	10701877	Filing Dt:	11/05/2003
Title:	METHOD AND SYSTEM FOR PROVIDING BACKSIDE VOLTAGE CONTRAST FOR SILICON ON INSULATOR DEVICES

Patent #:	7020535	Issue Dt:	03/28/2006	Application #:	10702877	Filing Dt:	11/06/2003
Title:	METHOD AND APPARATUS FOR PROVIDING EXCITATION FOR A PROCESS CONTROLLER

Patent #:	6829040	Issue Dt:	12/07/2004	Application #:	10703643	Filing Dt:	11/07/2003
Title:	LITHOGRAPHY CONTRAST ENHANCEMENT TECHNIQUE BY VARYING FOCUS WITH WAVELENGTH MODULATION

Patent #:	6784073	Issue Dt:	08/31/2004	Application #:	10704508	Filing Dt:	11/07/2003
Title:	METHOD OF MAKING SEMICONDUCTOR-ON-INSULATOR DEVICE WITH THERMOELECTRIC COOLER

Patent #:	7005387	Issue Dt:	02/28/2006	Application #:	10705631	Filing Dt:	11/08/2003
Publication #:	US20050101148	Pub Dt:	05/12/2005
Title:	METHOD FOR PREVENTING AN INCREASE IN CONTACT HOLE WIDTH DURING CONTACT FORMATION

Patent #:	7074657	Issue Dt:	07/11/2006	Application #:	10706948	Filing Dt:	11/14/2003
Publication #:	US20050104140	Pub Dt:	05/19/2005
Title:	LOW-POWER MULTIPLE-CHANNEL FULLY DEPLETED QUANTUM WELL CMOSFETS

Patent #:	7185128	Issue Dt:	02/27/2007	Application #:	10714584	Filing Dt:	11/14/2003
Title:	SYSTEM AND METHOD FOR MACHINE SPECIFIC REGISTER ADDRESSING IN EXTERNAL DEVICES

Patent #:	6916696	Issue Dt:	07/12/2005	Application #:	10718459	Filing Dt:	11/20/2003
Title:	METHOD FOR MANUFACTURING A MEMORY ELEMENT

Patent #:	7256455	Issue Dt:	08/14/2007	Application #:	10720166	Filing Dt:	11/25/2003
Publication #:	US20040110097	Pub Dt:	06/10/2004
Title:	DOUBLE GATE SEMICONDUCTOR DEVICE HAVING A METAL GATE

Patent #:	7125652	Issue Dt:	10/24/2006	Application #:	10726413	Filing Dt:	12/03/2003
Publication #:	US20050122497	Pub Dt:	06/09/2005
Title:	IMMERSION LITHOGRAPHIC PROCESS USING A CONFORMING IMMERSION MEDIUM

Patent #:	6852600	Issue Dt:	02/08/2005	Application #:	10726472	Filing Dt:	12/02/2003
Title:	STRAINED SILICON MOSFET HAVING SILICON SOURCE/DRAIN REGIONS AND METHOD FOR ITS FABRICATION

Patent #:	6967175	Issue Dt:	11/22/2005	Application #:	10726619	Filing Dt:	12/04/2003
Title:	DAMASCENE GATE SEMICONDUCTOR PROCESSING WITH LOCAL THINNING OF CHANNEL REGION

Patent #:	6977717	Issue Dt:	12/20/2005	Application #:	10727385	Filing Dt:	12/04/2003
Title:	METHOD AND DEVICE FOR DETERMINING PROJECTION LENS PUPIL TRANSMISSION DISTRIBUTION AND ILLUMINATION INTENSITY DISTRIBUTION IN PHOTOLITHOGRAPHIC IMAGING SYSTEM

Patent #:	7132306	Issue Dt:	11/07/2006	Application #:	10728772	Filing Dt:	12/08/2003
Title:	METHOD OF FORMING AN INTERLEVEL DIELECTRIC LAYER EMPLOYING DIELECTRIC ETCH-BACK PROCESS WITHOUT EXTRA MASK SET

Patent #:	7183223	Issue Dt:	02/27/2007	Application #:	10728909	Filing Dt:	12/08/2003
Title:	METHODS FOR FORMING SMALL CONTACTS

Patent #:	7144818	Issue Dt:	12/05/2006	Application #:	10729479	Filing Dt:	12/05/2003
Publication #:	US20050124170	Pub Dt:	06/09/2005
Title:	SEMICONDUCTOR SUBSTRATE AND PROCESSES THEREFOR

Patent #:	7369550	Issue Dt:	05/06/2008	Application #:	10734237	Filing Dt:	12/15/2003
Title:	METHOD AND APPARATUS FOR LOCKING A TABLE IN A NETWORK SWITCH

Patent #:	6929992	Issue Dt:	08/16/2005	Application #:	10738496	Filing Dt:	12/17/2003
Title:	STRAINED SILICON MOSFETS HAVING NMOS GATES WITH WORK FUNCTIONS FOR COMPENSATING NMOS THRESHOLD VOLTAGE SHIFT

Patent #:	6943087	Issue Dt:	09/13/2005	Application #:	10738529	Filing Dt:	12/17/2003
Title:	SEMICONDUCTOR ON INSULATOR MOSFET HAVING STRAINED SILICON CHANNEL

Patent #:	7071065	Issue Dt:	07/04/2006	Application #:	10738716	Filing Dt:	12/17/2003
Title:	STRAINED SILICON PMOS HAVING SILICON GERMANIUM SOURCE/DRAIN EXTENSIONS AND METHOD FOR ITS FABRICATION

Patent #:	7482252	Issue Dt:	01/27/2009	Application #:	10740546	Filing Dt:	12/22/2003
Title:	METHOD FOR REDUCING FLOATING BODY EFFECTS IN SOI SEMICONDUCTOR DEVICE WITHOUT DEGRADING MOBILITY

Patent #:	6897122	Issue Dt:	05/24/2005	Application #:	10747205	Filing Dt:	12/30/2003
Title:	WIDE NECK SHALLOW TRENCH ISOLATION REGION TO PREVENT STRAIN RELAXATION AT SHALLOW TRENCH ISOLATION REGION EDGES

Patent #:	7022596	Issue Dt:	04/04/2006	Application #:	10747680	Filing Dt:	12/30/2003
Publication #:	US20050146059	Pub Dt:	07/07/2005
Title:	METHOD FOR FORMING RECTANGULAR-SHAPED SPACERS FOR SEMICONDUCTOR DEVICES

Patent #:	7169664	Issue Dt:	01/30/2007	Application #:	10747722	Filing Dt:	12/29/2003
Publication #:	US20040251518	Pub Dt:	12/16/2004
Title:	METHOD OF REDUCING WAFER CONTAMINATION BY REMOVING UNDER-METAL LAYERS AT THE WAFER EDGE

Patent #:	7150675	Issue Dt:	12/19/2006	Application #:	10747723	Filing Dt:	12/29/2003
Publication #:	US20040242122	Pub Dt:	12/02/2004
Title:	METHOD AND SYSTEM FOR CONTROLLING THE CHEMICAL MECHANICAL POLISHING BY USING A SENSOR SIGNAL OF A PAD CONDITIONER

Patent #:	6812076	Issue Dt:	11/02/2004	Application #:	10752691	Filing Dt:	01/08/2004
Title:	DUAL SILICON LAYER FOR CHEMICAL MECHANICAL POLISHING PLANARIZATION

Patent #:	7432557	Issue Dt:	10/07/2008	Application #:	10755344	Filing Dt:	01/13/2004
Title:	FINFET DEVICE WITH MULTIPLE CHANNELS

Patent #:	7462549	Issue Dt:	12/09/2008	Application #:	10755602	Filing Dt:	01/12/2004
Publication #:	US20050151222	Pub Dt:	07/14/2005
Title:	SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION

Patent #:	6950176	Issue Dt:	09/27/2005	Application #:	10755658	Filing Dt:	01/12/2004
Title:	METHOD AND SYSTEM FOR MONITORING EUV LITHOGRAPHY MASK FLATNESS

Patent #:	7373484	Issue Dt:	05/13/2008	Application #:	10755692	Filing Dt:	01/12/2004
Title:	CONTROLLING WRITES TO NON-RENAMED REGISTER SPACE IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR

Patent #:	7251710	Issue Dt:	07/31/2007	Application #:	10755734	Filing Dt:	01/12/2004
Title:	CACHE MEMORY SUBSYSTEM INCLUDING A FIXED LATENCY R/W PIPELINE

Patent #:	7213126	Issue Dt:	05/01/2007	Application #:	10755742	Filing Dt:	01/12/2004
Title:	METHOD AND PROCESSOR INCLUDING LOGIC FOR STORING TRACES WITHIN A TRACE CACHE

Patent #:	7238588	Issue Dt:	07/03/2007	Application #:	10755746	Filing Dt:	01/12/2004
Publication #:	US20050095807	Pub Dt:	05/05/2005
Title:	SILICON BUFFERED SHALLOW TRENCH ISOLATION

Patent #:	7138302	Issue Dt:	11/21/2006	Application #:	10755763	Filing Dt:	01/12/2004
Publication #:	US20050153486	Pub Dt:	07/14/2005
Title:	Method of fabricating an integrated circuit channel region

Patent #:	6972201	Issue Dt:	12/06/2005	Application #:	10755794	Filing Dt:	01/12/2004
Title:	USING SCATTEROMETRY TO DETECT AND CONTROL UNDERCUT FOR ARC WITH DEVELOPABLE BARCS

Patent #:	7532625	Issue Dt:	05/12/2009	Application #:	10756238	Filing Dt:	01/13/2004
Publication #:	US20050117518	Pub Dt:	06/02/2005
Title:	BLOCK TRANSFER FOR WLAN DEVICE CONTROL

Patent #:	6836017	Issue Dt:	12/28/2004	Application #:	10759170	Filing Dt:	01/20/2004
Publication #:	US20040147117	Pub Dt:	07/29/2004
Title:	PROTECTION OF LOW-K ILD DURING DAMASCENE PROCESSING WITH THIN LINER

Patent #:	6979635	Issue Dt:	12/27/2005	Application #:	10759171	Filing Dt:	01/20/2004
Title:	METHOD OF FORMING MINIATURIZED POLYCRYSTALLINE SILICON GATE ELECTRODES USING SELECTIVE OXIDATION

Patent #:	7071051	Issue Dt:	07/04/2006	Application #:	10761009	Filing Dt:	01/20/2004
Title:	METHOD FOR FORMING A THIN, HIGH QUALITY BUFFER LAYER IN A FIELD EFFECT TRANSISTOR AND RELATED STRUCTURE

Patent #:	7250645	Issue Dt:	07/31/2007	Application #:	10761374	Filing Dt:	01/22/2004
Title:	REVERSED T-SHAPED FINFET

Patent #:	7098140	Issue Dt:	08/29/2006	Application #:	10761576	Filing Dt:	01/21/2004
Publication #:	US20040266200	Pub Dt:	12/30/2004
Title:	METHOD OF COMPENSATING FOR ETCH RATE NON-UNIFORMITIES BY ION IMPLANTATION

Patent #:	6894337	Issue Dt:	05/17/2005	Application #:	10768014	Filing Dt:	02/02/2004
Title:	SYSTEM AND METHOD FOR FORMING STACKED FIN STRUCTURE USING METAL-INDUCED-CRYSTALLIZATION

Patent #:	7164185	Issue Dt:	01/16/2007	Application #:	10770629	Filing Dt:	02/02/2004
Title:	SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

Patent #:	7198964	Issue Dt:	04/03/2007	Application #:	10770681	Filing Dt:	02/03/2004
Title:	METHOD AND APPARATUS FOR DETECTING FAULTS USING PRINCIPAL COMPONENT ANALYSIS PARAMETER GROUPINGS

Patent #:	7473566	Issue Dt:	01/06/2009	Application #:	10770682	Filing Dt:	02/03/2004
Title:	METHOD AND APPARATUS FOR CONTROLLING A FILM FORMATION PROCESS WITH MULTIPLE OBJECTIVES

Patent #:	7064067	Issue Dt:	06/20/2006	Application #:	10770905	Filing Dt:	02/02/2004
Title:	REDUCTION OF LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7512787	Issue Dt:	03/31/2009	Application #:	10771019	Filing Dt:	02/03/2004
Title:	RECEIVE IPSEC IN-LINE PROCESSING OF MUTABLE FIELDS FOR AH ALGORITHM

Patent #:	6864184	Issue Dt:	03/08/2005	Application #:	10772830	Filing Dt:	02/05/2004
Title:	METHOD FOR REDUCING CRITICAL DIMENSION ATTAINABLE VIA THE USE OF AN ORGANIC CONFORMING LAYER

Patent #:	7422828	Issue Dt:	09/09/2008	Application #:	10774099	Filing Dt:	02/06/2004
Title:	MASK CD MEASUREMENT MONITOR OUTSIDE OF THE PELLICLE AREA

Patent #:	7065737	Issue Dt:	06/20/2006	Application #:	10790296	Filing Dt:	03/01/2004
Publication #:	US20050193362	Pub Dt:	09/01/2005
Title:	MULTI-LAYER OVERLAY MEASUREMENT AND CORRECTION TECHNIQUE FOR IC MANUFACTURING

Patent #:	7056804	Issue Dt:	06/06/2006	Application #:	10790366	Filing Dt:	03/01/2004
Title:	SHALLOW TRENCH ISOLATION POLISH STOP LAYER FOR REDUCED TOPOGRAPHY

Patent #:	7122455	Issue Dt:	10/17/2006	Application #:	10790567	Filing Dt:	03/01/2004
Title:	PATTERNING WITH RIGID ORGANIC UNDER-LAYER

Patent #:	7494872	Issue Dt:	02/24/2009	Application #:	10790852	Filing Dt:	03/02/2004
Publication #:	US20050023611	Pub Dt:	02/03/2005
Title:	FIELD EFFECT TRANSISTOR HAVING A DOPED GATE ELECTRODE WITH REDUCED GATE DEPLETION AND METHOD OF FORMING THE TRANSISTOR

Patent #:	7023059	Issue Dt:	04/04/2006	Application #:	10791094	Filing Dt:	03/01/2004
Title:	TRENCHES TO REDUCE LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY

Patent #:	7015076	Issue Dt:	03/21/2006	Application #:	10791098	Filing Dt:	03/01/2004
Title:	SELECTABLE OPEN CIRCUIT AND ANTI-FUSE ELEMENT, AND FABRICATION METHOD THEREFOR

Patent #:	7135879	Issue Dt:	11/14/2006	Application #:	10791130	Filing Dt:	03/01/2004
Title:	TEST STRUCTURE AND METHOD FOR FAILURE ANALYSIS OF SMALL CONTACTS IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT

Patent #:	7276328	Issue Dt:	10/02/2007	Application #:	10791259	Filing Dt:	03/02/2004
Title:	LITHOGRAPHY MASK UTILIZING ASYMMETRIC LIGHT SOURCE

Patent #:	6977718	Issue Dt:	12/20/2005	Application #:	10791263	Filing Dt:	03/02/2004
Title:	LITHOGRAPHY METHOD AND SYSTEM WITH ADJUSTABLE REFLECTOR

Patent #:	7091106	Issue Dt:	08/15/2006	Application #:	10791759	Filing Dt:	03/04/2004
Publication #:	US20050196928	Pub Dt:	09/08/2005
Title:	METHOD OF REDUCING STI DIVOT FORMATION DURING SEMICONDUCTOR DEVICE FABRICATION

Patent #:	7071564	Issue Dt:	07/04/2006	Application #:	10791904	Filing Dt:	03/04/2004
Title:	COMPOSITE TANTALUM CAPPED INLAID COPPER WITH REDUCED ELECTROMIGRATION AND REDUCED STRESS MIGRATION

Patent #:	6876037	Issue Dt:	04/05/2005	Application #:	10796731	Filing Dt:	03/09/2004
Publication #:	US20040169227	Pub Dt:	09/02/2004
Title:	DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRISING THE RESULTING DOPED REGIONS

Patent #:	7115498	Issue Dt:	10/03/2006	Application #:	10803852	Filing Dt:	03/18/2004
Title:	METHOD OF ULTRA-LOW ENERGY ION IMPLANTATION TO FORM ALLOY LAYERS IN COPPER

100

Patent #:	7084758	Issue Dt:	08/01/2006	Application #:	10804308	Filing Dt:	03/19/2004
Title:	LOCATION-BASED REMINDERS

Assignor

ADVANCED MICRO DEVICES, INC.

Exec Dt:

06/30/2009

Assignee

GLOBALFOUNDRIES INC.

P.O. BOX 309, UGLAND HOUSE

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	BNK / MHKKG
	P.O. BOX 398
	AUSTIN, TX 78767-0398

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