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|
|
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Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08823817
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Filing Dt:
|
03/24/1997
|
|
Title:
|
METHOD OF MAKING STATIC RANDOW ACCESS MEMORY CELL HAVING A TRENCH FIELD PLATE FOR INCREASED CAPACITANCE
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Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08824323
|
Filing Dt:
|
03/26/1997
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|
Title:
|
COMPACT, DUAL-TRANSISTOR INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08824830
|
Filing Dt:
|
03/26/1997
|
|
Title:
|
SEMICONDUCTOR TRENCH ISOLATION STRUCTURE FORMED SUBSTANTIALLY WITHIN A SINGLE CHAMBER
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|
|
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|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08825015
|
Filing Dt:
|
03/26/1997
|
|
Title:
|
PEFORMING A SEMICONDUCTOR FABRICATION SEQUENCE WITHIN A COMMON CHAMBER AND WITHOUT OPENING THE CHAMBER BEGINNING WITH FORMING A FIELD DIELECTRIC AND CONCLUDING WITH A GATE DIELECTRIC
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|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08825029
|
Filing Dt:
|
03/26/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING GATE OXIDE FORMED BY SELECTIVE OXIDE REMOVAL AND METHOD OF MANUFACTURE THEREOF
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|
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|
Patent #:
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|
Issue Dt:
|
06/09/1998
|
Application #:
|
08826884
|
Filing Dt:
|
04/08/1997
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR EMPLOYING A WAY PREDICTION UNIT TO PREDICT THE WAY OF AN INSTRUCTION FETCH ADDRESS AND TO CONCURRENTLY PROVIDE A BRANCH PREDICTION ADDRESS CORRESPONDING TO THE FETCH ADDRESS
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|
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|
Patent #:
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|
Issue Dt:
|
12/15/1998
|
Application #:
|
08827675
|
Filing Dt:
|
04/10/1997
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|
Title:
|
INTRUSION CONTROL IN REPEATER BASED NETWORKS
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|
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|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08829704
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Filing Dt:
|
03/26/1997
|
|
Title:
|
CHEMICAL-MECHANICAL POLISHING SLURRY FORMULATION AND METHOD FOR TUNGSTEN AND TITANIUM THIN FILMS
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|
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|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08831194
|
Filing Dt:
|
04/02/1997
|
|
Title:
|
A START OF ACCESS INSTUCTION COONFIGURED TO INDICATE AN ACCESS MODE FOR FETCHING MEMORY OPERANDS IN A MICROPROCESSSOR
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Patent #:
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|
Issue Dt:
|
01/26/1999
|
Application #:
|
08832657
|
Filing Dt:
|
04/04/1997
|
|
Title:
|
TRENCH-GATED VERTICAL CMOS DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08832706
|
Filing Dt:
|
04/11/1997
|
|
Title:
|
METHOD OF MANUFACTURING AN ISLOATION REGION OF A SEMICONDUCTOR DEVICE WITH ADVANCED PLANARIZATION
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|
|
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|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08832747
|
Filing Dt:
|
04/04/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE DEVICE USING A DUAL LAYER, SELF-ALIGNED SILICIDE TO ENHANCE CONTACT PERFORMANCE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08837119
|
Filing Dt:
|
04/14/1997
|
|
Title:
|
COMMUNICATION SYSTEM WHICH IN A FIRST MODE SUPPORTS CONCURRENT MEMORY ACESSES OF A PARTIONED MEMORY ARRAY AND IN A SECOND MODE SUPPORTS NON- CONCURRENT MEMORY ACCESSES TO THE ENTIRE MEMORY ARRAY
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|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08837120
|
Filing Dt:
|
04/14/1997
|
|
Title:
|
COMPUTER SYSTEM FOR CONCURRENT DATA TRANSFERRING BETWEEN GRAPHIC CONTROLLER AND UNIFIED SYSTEM MEMORY AND BETWEEN CPU AND EXPANSION BUS DEVICE
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Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08837526
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Filing Dt:
|
04/21/1997
|
|
Title:
|
METHOD OF MAKING ASYMMETRICAL TRANSISTOR WITH LIGHTLY AND HEAVILY DOPED DRAIN REGIONS AND ULTRA-HEAVILY DOPED SOURCE REGION USING TWO SOURCE/DRAIN IMPLANT STEPS
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|
Patent #:
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|
Issue Dt:
|
06/27/2000
|
Application #:
|
08837579
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Filing Dt:
|
04/21/1997
|
|
Title:
|
ION IMPLANTATION INTO A GATE ELECTRODE LAYER USING AN IMPLANT PROFILE DISPLACEMENT LAYER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08837581
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Filing Dt:
|
04/21/1997
|
|
Title:
|
COMPOSITE GATE ELECTRODE INCORPORATING DOPANT DIFFUSION-RETARDING BARRIER LAYER ADJACENT TO UNDERLYING GATE DIELECTRIC
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|
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|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08837936
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Filing Dt:
|
04/11/1997
|
|
Title:
|
METHOD OF CONTROLLING DOPANT CONCENTRATIONS USING TRANSIENT-ENHANCED DIFFUSION PRIOR TO GATE FORMATION IN A DEVICE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08837937
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Filing Dt:
|
04/11/1997
|
|
Title:
|
METHOD OF IMPLAMENTING SILICON THROUGH A POLYSILICON GATE FOR PUNCHTHROUGH CONTROL OF A SEMICONDUCTOR DEVICE
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Patent #:
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|
Issue Dt:
|
08/08/2000
|
Application #:
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08842989
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Filing Dt:
|
04/25/1997
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Title:
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NETWORK ROUTER WITH PARTITIONED MEMORY FOR OPTIMIZED DATA STORAGE AND RETRIEVAL
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Patent #:
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|
Issue Dt:
|
05/09/2000
|
Application #:
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08844924
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Filing Dt:
|
04/21/1997
|
|
Title:
|
METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS
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|
Patent #:
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|
Issue Dt:
|
11/02/1999
|
Application #:
|
08844925
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Filing Dt:
|
04/21/1997
|
|
Title:
|
METHOD OF MAKING ENHANCEMENT-MODE AND DEPLETION-MODE IGFETS WITH DIFFERENT GATE THICKNESSES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/1999
|
Application #:
|
08845591
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Filing Dt:
|
04/25/1997
|
|
Title:
|
A LOW-PROFILE HEAT TRANSFER APPARATUS FOR A SURFACE-MOUNTED SEMICONDUCTOR DEVICE EMPLOYING A BALL GRID ARRAY (BGA) DEVICE PACKAGE
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|
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|
Patent #:
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|
Issue Dt:
|
04/20/1999
|
Application #:
|
08845640
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Filing Dt:
|
05/01/1997
|
|
Title:
|
SYSTEM AND METHOD FOR ENCODING INSTRUCTION FIELDS WITHIN DATA PACKETS
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/02/1999
|
Application #:
|
08845978
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Filing Dt:
|
04/30/1997
|
|
Title:
|
METHOD OF OPERATING A HIGH PERFORMANCE SUPERSCALAR MICROPROCESSOR INCLUDING A COMMON REORDER BUFFER AND COMMON REGISTER FILE FOR BOTH INTEGER AND FLOATING POINT OPERATIONS
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|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08846001
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Filing Dt:
|
04/25/1997
|
|
Title:
|
HEAT TRANSFER APPARATUS WHICH ACCOMMODATES ELEVATIONAL DISPARITY ACROSS AN UPPER SURFACE OF A SURFACE-MOUNTED SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
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08847752
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Filing Dt:
|
04/21/1997
|
|
Title:
|
METHOD OF MAKING AN IGFET WITH SELECTIVELY DOPED MULTILEVEL POLYSILICON GATE
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|
Patent #:
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|
Issue Dt:
|
11/30/1999
|
Application #:
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08850253
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Filing Dt:
|
05/02/1997
|
|
Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING A SPACER METALLIZATION TECHNIQUE
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|
Patent #:
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|
Issue Dt:
|
06/02/1998
|
Application #:
|
08850290
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Filing Dt:
|
05/05/1997
|
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Title:
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DATA MEMORY UNIT AND METHOD FOR STORING DATA INTO A LOCKABLE CACHE IN ONE CLOCK CYCLE BY PREVIEWING THE TAG ARRAY
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|
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|
Patent #:
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|
Issue Dt:
|
04/18/2000
|
Application #:
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08850854
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Filing Dt:
|
05/02/1997
|
|
Title:
|
METHOD OF USING A HARD MASK TO GROW DIELECTRICS WITH VARYING CHARACTERISTICS
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|
Patent #:
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|
Issue Dt:
|
04/28/1998
|
Application #:
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08851411
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Filing Dt:
|
05/05/1997
|
|
Title:
|
APPARATUS AND METHOD FOR ANALYZING SPEECH SIGNALS TO DETERMINE PARAMETERS EXPRESSIVE OF CHARACTERISTICS OF THE SPEECH SIGNALS
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Patent #:
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|
Issue Dt:
|
12/21/1999
|
Application #:
|
08852317
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Filing Dt:
|
05/07/1997
|
|
Title:
|
APPARATUS FOR THE NON-CONTACT MANIPULATION OF A SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
07/25/2000
|
Application #:
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08852431
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Filing Dt:
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05/07/1997
|
|
Title:
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VIRTUAL SERIAL DATA TRANSFER MECHANISM
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|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
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08852689
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Filing Dt:
|
05/07/1997
|
|
Title:
|
COMPUTER COMMUNICATION NETWORK HAVING A PACKET PROCESSOR WITH AN EXECUTION UNIT WHICH IS VARIABLY CONFIGURED FROM A PROGRAMMABLE STATE MACHINE AND LOGIC
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Patent #:
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|
Issue Dt:
|
09/07/1999
|
Application #:
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08852691
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Filing Dt:
|
05/07/1997
|
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Title:
|
APPARATUS FOR SELECTIVELY EXPOSING A SEMICONDUCTOR TOPOGRAPHY TO AN ELECTRIC FIELD
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Patent #:
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|
Issue Dt:
|
12/01/1998
|
Application #:
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08855099
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Filing Dt:
|
05/13/1997
|
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Title:
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PREFETCH BUFFER FOR STORING INSTRUCTIONS PRIOR TO PLACING THE INSTRUCTIONS IN AN INSTRUCTION CACHE
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Patent #:
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|
Issue Dt:
|
12/07/1999
|
Application #:
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08856545
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Filing Dt:
|
05/15/1997
|
|
Title:
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FORMATION OF OXYNITRIDE AND POLYSILICON LAYERS IN A SINGLE REACTION CHAMBER
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Patent #:
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|
Issue Dt:
|
09/01/1998
|
Application #:
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08858583
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Filing Dt:
|
05/19/1997
|
|
Title:
|
LOAD/STORE UNIT IMPLEMENTING NON-BLOCKING LOADS FOR A SUPERSCALAR MICROPROCESSOR AND METHOD OF SELECTING LOADS IN A NON-BLOCKING FASHION FROM A LOAD/STORE BUFFER
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Patent #:
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|
Issue Dt:
|
02/06/2001
|
Application #:
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08861553
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Filing Dt:
|
05/22/1997
|
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Title:
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METHOD FOR POST TRANSISTOR ISOLATION
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|
Patent #:
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|
Issue Dt:
|
03/23/1999
|
Application #:
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08865883
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Filing Dt:
|
05/30/1997
|
|
Title:
|
REDUCTION OF DOPANT DIFFUSION BY THE CO-IMPLANTATION OF IMPURITIES INTO THE TRANSISTOR GATE CONDUCTOR
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|
Patent #:
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|
Issue Dt:
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03/28/2000
|
Application #:
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08865909
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Filing Dt:
|
05/30/1997
|
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Title:
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CACHE WITH FINELY GRANULAR LOCKED-DOWN REGIONS
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|
Patent #:
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|
Issue Dt:
|
07/20/1999
|
Application #:
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08866373
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Filing Dt:
|
05/30/1997
|
|
Title:
|
INTEGRATED PROCESSOR SYSTEM ADAPTED FOR PORTABLE PERSONAL INFORMATION DEVICES
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|
Patent #:
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|
Issue Dt:
|
10/26/1999
|
Application #:
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08869466
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Filing Dt:
|
06/05/1997
|
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Title:
|
HIGH QUALITY ISOLATION FOR HIGH DENSITY AND HIGH PERFORMANCE INTEGRATED CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
07/27/1999
|
Application #:
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08871468
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Filing Dt:
|
06/09/1997
|
|
Title:
|
TRANSISTOR WITH BURIED INSULATIVE LAYER BENEATH THE CHANNEL REGION
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|
Patent #:
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|
Issue Dt:
|
05/01/2001
|
Application #:
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08871469
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Filing Dt:
|
06/09/1997
|
|
Title:
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NITROGEN LINER BENEATH TRANSISTOR SOURCE/DRAIN REGIONS TO RETARD DOPANT DIFFUSION
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|
Patent #:
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|
Issue Dt:
|
06/06/2000
|
Application #:
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08873113
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Filing Dt:
|
06/11/1997
|
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Title:
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INSTRUCTION FETCH UNIT CONFIGURED TO PROVIDE SEQUENTIAL WAY PREDICTION FOR SEQUENTIAL INSTRUCTION FETCHES
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Patent #:
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|
Issue Dt:
|
04/27/1999
|
Application #:
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08873115
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Filing Dt:
|
06/11/1997
|
|
Title:
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METHOD AND APPARATUS FOR FIVE BIT PREDECODING VARIABLE LENGTH INSTRUCTIONS FOR SCANNING OF A NUMBER OF RISC OPERATIONS
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Patent #:
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|
Issue Dt:
|
02/16/1999
|
Application #:
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08873339
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Filing Dt:
|
06/11/1997
|
|
Title:
|
INSTRUCTION ALIGNMENT UNIT EMPLOYING DUAL INSTRUCTION QUEUES FOR HIGH FREQUENCY INSTRUCTION DISPATCH
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|
Patent #:
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|
Issue Dt:
|
08/03/1999
|
Application #:
|
08873360
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Filing Dt:
|
06/12/1997
|
|
Title:
|
APPARATUS AND METHOD FOR DETECTING MICROBRANCHES EARLY
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|
Patent #:
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|
Issue Dt:
|
04/27/1999
|
Application #:
|
08874025
|
Filing Dt:
|
06/12/1997
|
|
Title:
|
APPARATUS AND METHOD FOR PREDICTING AN END OF LOOP FOR STRING INSTRUCTIONS
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|
Patent #:
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|
Issue Dt:
|
12/29/1998
|
Application #:
|
08874031
|
Filing Dt:
|
06/12/1997
|
|
Title:
|
FLEXIBLE RESOURCE ACCESS IN A MICROPROCESSOR
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|
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|
Patent #:
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|
Issue Dt:
|
07/04/2000
|
Application #:
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08874791
|
Filing Dt:
|
06/13/1997
|
|
Title:
|
METHOD OF ADJUSTING CURRENTS ON A SEMICONDUCTOR DEVICE HAVING TRANSISTORS OF VARYING DENSITY
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|
Patent #:
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|
Issue Dt:
|
03/16/1999
|
Application #:
|
08878228
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Filing Dt:
|
06/18/1997
|
|
Title:
|
METHOD FOR CONCURRENTLY DISPATCHING MICROCODE AND DIRECTLY-DECODED INSTRUCTIONS IN A MICROPROCESSOR
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|
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|
Patent #:
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|
Issue Dt:
|
09/29/1998
|
Application #:
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08878682
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Filing Dt:
|
06/19/1997
|
|
Title:
|
HIGH DENSITY DYNAMIC BUS ROUTING SCHEME
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|
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|
Patent #:
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|
Issue Dt:
|
12/05/2000
|
Application #:
|
08878787
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Filing Dt:
|
06/19/1997
|
|
Title:
|
AUTOMATED MATERIAL HANDLING SYSTEM FOR A MANUFACTURING FACILITY DIVIDED INTO SEPARATE FABRICATION AREAS
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|
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|
Patent #:
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|
Issue Dt:
|
07/20/1999
|
Application #:
|
08878788
|
Filing Dt:
|
06/19/1997
|
|
Title:
|
AUTOMATED WAFER TRANSFER SYSTEM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
05/09/2000
|
Application #:
|
08879202
|
Filing Dt:
|
06/19/1997
|
|
Title:
|
TIME MULTIPLEXED SCHEME FOR DEADLOCK RESOLUTION IN DISTRIBUTED ARBITRATION
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|
|
|
Patent #:
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|
Issue Dt:
|
07/06/1999
|
Application #:
|
08879508
|
Filing Dt:
|
06/20/1997
|
|
Title:
|
ASYMMETRICAL TRANSISTOR HAVING A GATE DIELECTRIC WHICH IS SUBSTANTIALLY RESISTANT TO HOT CARRIER INJECTION
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/30/1999
|
Application #:
|
08879574
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Filing Dt:
|
06/20/1997
|
|
Title:
|
SOURCE DRAIN JUNCTION AREAS SELF ALIGNED BETWEEN A SIDEWALL SPACER AND AN ETCHED LATERAL SIDEWALL
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|
Patent #:
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|
Issue Dt:
|
01/04/2000
|
Application #:
|
08879588
|
Filing Dt:
|
06/20/1997
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR INCLUDING A DECODED INSTRUCTION CACHE CONFIGURED TO RECEIVE PARTIALLY DECODED INSTRUCTIONS
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|
Patent #:
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|
Issue Dt:
|
11/19/2002
|
Application #:
|
08879620
|
Filing Dt:
|
06/20/1997
|
|
Title:
|
ASYMMETRICAL TRANSISTOR HAVING A BARRIER-INCORPORATED GATE OXIDE AND A GRADED IMPLANT ONLY IN THE DRAIN-SIDE JUNCTION AREA
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/01/2000
|
Application #:
|
08882424
|
Filing Dt:
|
06/25/1997
|
|
Title:
|
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING NITROGEN-BEARING GATE ELECTRODE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
10/16/2001
|
Application #:
|
08882604
|
Filing Dt:
|
06/25/1997
|
|
Title:
|
INFORMATION PACKET RECEPTION INDICATOR FOR REDUCING THE UTILIZATION OF A HOST SYSTEM PROCESSOR UNIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/27/2001
|
Application #:
|
08884126
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
FORMING RETROGRADE CHANNEL PROFILE AND SHALLOW LLDD/-D EXTENSIONS USING NITROGEN IMPLANTS
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|
|
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|
Patent #:
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|
Issue Dt:
|
07/28/1998
|
Application #:
|
08884316
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
METHOD AND APPARATUS FOR PATTERN RECOGNITION OF WAFER TEST BINS
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08884434
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Filing Dt:
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06/27/1997
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Title:
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CACHE INCLUDING A PREFETCH WAY FOR STORING PREFETCH CACHE LINES AND CONFIGURED TO MOVE A PREFETCHED CACHE LINE TO A NON-PREFETCH WAY UPON ACCESS TO THE PREFETCHED CACHE LINE
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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08884435
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Filing Dt:
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06/27/1997
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Title:
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FULLY ASSOCIATE CACHE EMPLOYING LRU GROUPS FOR CACHE REPLACEMENT AND MECHANISM FOR SELECTING AN LRU GROUP
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08884658
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Filing Dt:
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06/27/1997
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Title:
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ARRANGEMENT FOR REGULATING PACKET FLOW RATE IN HALF-DUPLEX NETWORKS
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08884818
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Filing Dt:
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06/30/1997
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Title:
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SUPERSCALAR MICROPROCESSOR INCLUDING A HIGH PERFORMANCE INTSTRUCTION ALIGNMENT UNIT
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08885677
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Filing Dt:
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06/30/1997
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Title:
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DISTRIBUTED VOLTAGE CONVERTER APPARATUS AND METHOD FOR HIGH POWER MICROPROCESSOR WITH ARRAY CONNECTIONS
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08886131
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Filing Dt:
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06/30/1997
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Title:
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REVERSE CMOS METHOD FOR DUAL ISOLATION SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08886421
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Filing Dt:
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07/01/1997
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Title:
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MICROPROCESSOR AND METHOD OF USING A SEGMENT OVERRIDE PREFIX INSTRUCTION FIELD TO EXPAND THE REGISTER FILE
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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08888651
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Filing Dt:
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07/07/1997
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Title:
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ACTIVE ISOLATION SYSTEM AND METHOD FOR ALLOWING LOCAL AND REMOTE DATA TRANSFERS ACROSS A COMMON DATA LINK
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08888654
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Filing Dt:
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07/07/1997
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Title:
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BANDWIDTH SHARING FOR REMOTE AND LOCAL DATA TRANSFERS USING MULTICARRIER MODULATION OVER COMMON TRANSMISSION MEDIUM
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Patent #:
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Issue Dt:
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04/13/1999
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Application #:
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08888822
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Filing Dt:
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07/07/1997
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Title:
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A METHOD FOR FORMING A HIGHLY PLANARIZED INTERLEVEL DIELECTRIC STRUCTURE
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08888870
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Filing Dt:
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07/07/1997
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Title:
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DEVICE AND METHOD FOR ISOLATING VOICE AND DATA SIGNALS ON A COMMON CARRIER
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08890104
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Filing Dt:
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07/09/1997
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Title:
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SHORT CHANNEL TRANSISTOR HAVING RESISTIVE GATE EXTENSIONS
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08890388
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Filing Dt:
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07/09/1997
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Title:
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ADAPTIVELY CONTROLLED, SELF-ALIGNED, SHORT CHANNEL DEVICE AND METHOD FOR MANUFACTURING SAME
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Patent #:
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Issue Dt:
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01/19/1999
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Application #:
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08890905
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Filing Dt:
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07/10/1997
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Title:
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LOW RC INTERCONNECTION
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08893744
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Filing Dt:
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07/11/1997
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Title:
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METHOD AND APPARATUS FOR UPPER LEVEL SUBSTRATE ISOLATION INTEGRATED WITH BULK SILICON
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08895800
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Filing Dt:
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07/17/1997
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Title:
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INSTRUCTION REDEFINITION USING MODEL SPECIFIC REGISTERS
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08895802
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Filing Dt:
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07/17/1997
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Title:
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WAVEFORM PLAYBACK DEVICE FOR ACTIVE NOISE CANCELLATION
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Patent #:
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Issue Dt:
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12/22/1998
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Application #:
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08896680
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Filing Dt:
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07/18/1997
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Title:
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METHOD OF MAKING TRANSISTOR HAVING A GATE DIELECTRIC WHICH IS SUBSTANTIALLY RESISTANT TO DRAIN-SIDE HOT CARRIER INJECTION
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08897265
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Filing Dt:
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07/18/1997
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Title:
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ELIMINATION OF RADIUS OF CURVATURE EFFECTS ON P-N JUNCTION AVALANCHE BREAKDOWN USING SLOTS
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08898089
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Filing Dt:
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07/23/1997
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Title:
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PULSE ELECTROPLATING COPPER OR COPPER ALLOYS
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08898974
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Filing Dt:
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07/23/1997
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Title:
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METHOD FOR FABRICATING A METALLIZATION STACK STRUTURE TO IMPROVE ELECTROMIGRATION RESISTANCE AND KEEP LOW RESISTIVITY OF ULSI INTERCONNECTS
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08904504
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Filing Dt:
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07/31/1997
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Title:
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TRANSACTION CHECKING SYSTEM FOR VERIFYING BUS BRIDGES IN MULTI-MASTER BUS SYSTEMS
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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08905306
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Filing Dt:
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08/01/1997
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Title:
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THIN FILM RESISTOR AND FABRICATION METHOD THEREOF
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08905482
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Filing Dt:
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08/01/1997
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Title:
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INTEGRATED CIRCUIT INCLUDING A GRADED GRAIN STRUCTURE FOR ENHANCED TRANSISTOR FORMATION AND FABRICATION METHOD THEREOF
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08905974
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Filing Dt:
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08/05/1997
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Title:
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SUBSTRACTIVE DUAL DAMASCENE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08906328
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Filing Dt:
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08/05/1997
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Title:
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ISOCHRONOUS BUFFERS FOR MMX-EQUIPPED MICROPROCESSORS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08907295
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Filing Dt:
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08/06/1997
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Title:
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RAPID THERMAL ANNEAL SYSTEM AND METHOD INCLUDING IMPROVED TEMPERATURE SENSING AND MONITORING
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08907310
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Filing Dt:
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08/06/1997
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Title:
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SEMICONDUCTOR PROCESS COMPENSATION UTILIZING NON-UNIFORM ION IMPLANTATION METHODOLOGY
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08907452
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Filing Dt:
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08/08/1997
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Title:
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SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INSULATOR
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08908593
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Filing Dt:
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08/08/1997
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Title:
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APPARATUS AND METHOD IN A NETWORK SWITCH FOR DYNAMICALLY ALLOCATING BANDWIDTH IN ETHERNET WORKGROUP SWITCHES
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08909463
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Filing Dt:
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08/11/1997
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Title:
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INTEGRATED CIRCUIT PACKAGE VERIFICATION
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08911744
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Filing Dt:
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08/15/1997
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Title:
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METHODS OF MAKING AND USING A CHEMICAL-MECHANICAL POLISHING SLURRY THAT REDUCES WAFER DEFECTS
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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08914234
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Filing Dt:
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08/19/1997
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Title:
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APPARATUS AND METHOD FOR GENERATING A PAUSE FRAME IN A BUFFERED DISTRIBUTOR BASED ON LENGTHS OF DATA PACKETS DISTRIBUTED ACCORDING TO A ROUND ROBIN REPEATER ARBITRATION
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08914262
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Filing Dt:
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08/19/1997
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Title:
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CHIP TEMPERATURE MONITOR USING DELAY LINES
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08914511
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Filing Dt:
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08/19/1997
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Title:
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APPARATUS AND METHOD FOR AUTOMATICALLY ACCESSING A DYNAMIC RAM FOR SYSTEM MANAGEMENT INTERRUPT HANDLING
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