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|
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Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
|
08915555
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
METHOD OF AND APPARATUS FOR TRANSFERRING AND INTERPRETING A DATA PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08915556
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
COMMUNICATION PROCESSING METHOD USING A BUFFER ARRAY AS A VIRTUALLY CIRCULAR BUFFER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08915631
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
COMPUTER ARCHITECTURE USING PACKET SWITCHES FOR INTERNAL DATA TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
08915691
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
METHOD FOR CHECKING DATA ERRORS IN DATA COMMUNICATION SYSTEMS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
08915695
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
METHOD OF COMMUNICATION FOR A COMPUTER USING PACKET SWITCHES FOR INTERNAL DATA TRANSFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
08915738
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
MULTIPLE PROCESSORS IN A ROW FOR PROTOCOL ACCELERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08915766
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
PC WIRELESS COMMUNICATIONS UTILIZING AN EMBEDDED ANTENNA COMPRISING A PLURALITY OF RADIATING AND RECEIVING ELEMENTS RESPONSIVE TO STEERING CIRCUITRY TO FORM A DIRECT ANTENNA BEAM
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|
|
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|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08915892
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
SYSTEM AND METHOD FOR TRANSMITTING DATA UPON AND ADDRESS PORTION OF A COMPUTER SYSTEM BUS DURING PERIODS OF MAXIMUM UTILIZATION OF A DATA PORTION OF THE BUS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08918202
|
Filing Dt:
|
08/25/1997
|
|
Title:
|
METHOD OF MAKING AN ASYMMETRICAL IGFET AND PROVIDING A FIELD DIELECTRIC BETWEEN ACTIVE REGIONS OF A SEMICONDUCTOR SUBSTRATE
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|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2002
|
Application #:
|
08919101
|
Filing Dt:
|
08/28/1997
|
|
Title:
|
APPARATUS AND METHOD FOR SELECTIVELY SUPPLYING DATA PACKETS BETWEEN MEDIA DOMAINS IN A NETWORK REPEATER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08920649
|
Filing Dt:
|
08/15/1997
|
|
Title:
|
PLURAL OPERAND BUSES OF INTERMEDIATE WIDTHS COUPLING TO NARROWER WIDTH INTEGER AND WIDER WIDTH FLOATING POINT SUPERSCALAR PROCESSING CORE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08921003
|
Filing Dt:
|
08/29/1997
|
|
Title:
|
ANNEALING OF SILICON OXYNITRIDE AND SILICON NITRIDE FILMS TO ELIMINATE HIGH TEMPERATURE CHARGE LOSS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08923181
|
Filing Dt:
|
09/04/1997
|
|
Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING IMPLANTATION OF EXCESS ATOMS AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08923184
|
Filing Dt:
|
09/04/1997
|
|
Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING BARRIER ATOMS INCORPORATED AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08923492
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
MEASUREMENT SYSTEM FOR DETECTING CHEMICAL SPECIES WITHIN A SEMICONDUCTOR PROCESSING DEVICE CHAMBER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08924569
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
METHODS AND ARRANGEMENTS FOR DETERMINING AN ENDPOINT FOR AN IN-SITU LOCAL INTERCONNECT ETCHING PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08926729
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
COMPUTER SYSTEM HAVING A MULTIMEDIA BUS AND COMPRISING A CENTRALIZED I/O PROCESSOR WHICH PERFORMS INTELLIGENT BYTE SLICING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08927337
|
Filing Dt:
|
09/11/1997
|
|
Title:
|
CONTEXT-DEPENDENT MEMORY-MAPPED REGISTERS FOR TRANSPARENT EXPANSION OF A REGISTER FILE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08927905
|
Filing Dt:
|
09/10/1997
|
|
Title:
|
SYSTEM AND METHOD FOR TRANSFERRING PERIODIC DATA STREAMS ON A MULTIMEDIA BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08928607
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
SELF ALIGNED METHOD FOR DIFFERENTIAL OXIDATION RATE AT SHALLOW TRENCH ISOLATION EDGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08928619
|
Filing Dt:
|
09/12/1997
|
|
Title:
|
RESISTANCE TO GATE DIELECTRIC BREAKDOWN AT THE EDGES OF SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08929197
|
Filing Dt:
|
09/08/1997
|
|
Title:
|
TRANSISTOR FABRICATION EMPLOYING FORMATION OF SILICIDE ACROSS SOURCE AND DRAIN REGIONS PRIOR TO FORMATION OF THE GATE CONDUCTOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08929865
|
Filing Dt:
|
09/15/1997
|
|
Title:
|
METHOD OF MANUFACTURING AN ISOLATION REGION IN A SEMICONDUCTOR DEVICE USING A FLOWABLE OXIDE-GENERATING MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08934261
|
Filing Dt:
|
09/19/1997
|
|
Title:
|
SERIAL BUS FOR TRANSMITTING INTERRUPT INFORMATION IN A MULTIPROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/1998
|
Application #:
|
08934509
|
Filing Dt:
|
09/19/1997
|
|
Title:
|
HIGH PERFORMANCE ASYMMETRICAL MOSFET STRUCTURE AND METHOD OF MAKING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
08936276
|
Filing Dt:
|
09/24/1997
|
|
Title:
|
CREATION OF AN ETCH HARDMASK BY SPIN-ON TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08937069
|
Filing Dt:
|
09/24/1997
|
|
Title:
|
METHOD FOR FORMING ASUMMETRICAL P-CHANNEL TRANSISTOR HAVING NITRIDED OXIDE PATTERNED TO SELECTIVELY FORM A SIDEWALL SPACER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08937634
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PATTERNING TO ENHANCE PERFORMANCE OF A METAL LAYER OF A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
08939017
|
Filing Dt:
|
09/26/1997
|
|
Title:
|
INTEGRATED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08939066
|
Filing Dt:
|
09/29/1997
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A LOW PERMITTIVITY DIELECTRIC LAYER AND CONTAMINATION DUE TO EXPOSURE TO WATER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08940247
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING AN INTERCONNECT LAYOUT TO REDUCE DELAYS IN LOGIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
08942998
|
Filing Dt:
|
10/02/1997
|
|
Title:
|
MULTIPLE SPACER FORMATION/REMOVAL TECHNIQUE FOR FORMING A GRADED JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08943469
|
Filing Dt:
|
10/03/1997
|
|
Title:
|
HIGH PERFORMANCE SUPRESCALAR ALIGNMENT UNIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08944377
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
METHOD OF INTEGRATING LDD IMPLANTATION FOR CMOS DEVICE FABRICATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
08946041
|
Filing Dt:
|
10/06/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A GROUP OF HIGH PERFORMANCE TRANSISTORS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08947225
|
Filing Dt:
|
10/08/1997
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR WHICH DELAYS UPDATE OF BRANCH PREDICTION INFORMATION IN RESPONSE TO BRANCH MISPREDICTION UNTIL A SUBSEQUENT IDLE CLOCK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08947521
|
Filing Dt:
|
10/02/1997
|
|
Title:
|
MASK GENERATION TECHNIQUE FOR PRODUCING AN INTEGRATED CIRCUIT WITH OPTIMAL POLYSILICON INTERCONNECT LAYOUT FOR ACHIEVING GLOBAL PLANARIZATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08948639
|
Filing Dt:
|
10/10/1997
|
|
Title:
|
COMPUTER SYSTEM AND METHOD FOR TRANSFERRING COMMANDS AND DATA TO A DEDICATED MULTIMEDIA ENGINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08948679
|
Filing Dt:
|
10/10/1997
|
|
Title:
|
MICROPROCESSOR INCLUDING AN EFFICIENT IMPLEMENTATION OF EXTREME VALUE INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08949889
|
Filing Dt:
|
10/14/1997
|
|
Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING A TRANSISTOR GATE COUPLED TO A LOCALIZED SUBSTRATE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
08949897
|
Filing Dt:
|
10/14/1997
|
|
Title:
|
TRACE CACHE FOR A MICROPROCESSOR-BASED DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
08950513
|
Filing Dt:
|
10/22/1997
|
|
Title:
|
DATA TRANSFER WITH HIGHLY GRANULAR CACHEABILITY CONTROL BETWEEN MEMORY AND A SCRATCHPAD AREA
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
08950717
|
Filing Dt:
|
10/15/1997
|
|
Title:
|
METHOD FOR MAKING TRANSISTOR HAVING REDUCED SERIES RESISTANCE AND METHOD FOR PRODUCING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08955287
|
Filing Dt:
|
10/21/1997
|
|
Title:
|
FLOATING POINT NAN COMPARISON
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
08955327
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
PC PARALLEL PORT STRUCTURE PARTITIONED BETWEEN TWO INTEGRATED CIRCUITS INTERCONNECTED BY A SERIAL BUS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08957085
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
MULTI-CHIP SUPERSCALAR MICROPROCESSOR MODULE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08957090
|
Filing Dt:
|
10/24/1997
|
|
Title:
|
SEMICONDUCTOR FABRICATION EMPLOYING SELF-ALIGNED SIDEWALL SPACERS LATERALLY ADJACENT TO A TRANSISTOR GATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
08957900
|
Filing Dt:
|
10/27/1997
|
|
Title:
|
INCREASING GENERAL REGISTERS IN X86 PROCESSORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08959105
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
MULTI-STEP POLYSILICON DEPOSITION PROCESS FOR BORON PENETRATION INHIBITION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08959106
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
METHOD OF MAKING AN INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/27/2001
|
Application #:
|
08959587
|
Filing Dt:
|
10/29/1997
|
|
Title:
|
HIGH DENSITY TRENCH FILL DUE TO NEW SPACER FILL METHOD INCLUDING ISOTROPICALLY ETCHING SILICON NITRIDE SPACERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08960189
|
Filing Dt:
|
10/29/1997
|
|
Title:
|
PAIRING FLOATING POINT EXCHANGE INSTRUCTION WITH ANOTHER FLOATING POINT INSTRUCTION TO REDUCE DISPATCH LATENCY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
08961023
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
APPARATUS AND METHOD FOR DETECTING A PRESCRIBED PATTERN IN A DATA STREAM BY SELECTIVELY SKIPPING GROUPS OF NONRELEVANT DATA BYTES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08961190
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
APPARATUS AND METHOD FOR SELECTIVELY CONTROLLING CLOCKING AND RESETTING OF A NETWORK INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08961432
|
Filing Dt:
|
10/30/1997
|
|
Title:
|
APPARATUS AND METHOD IN A NETWORK INTERFACE FOR ENABLING POWER UP OF A HOST COMPUTER USING MAGIC PACKET AND ON-NOW POWER UP MANAGEMENT SCHEMES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08961853
|
Filing Dt:
|
10/31/1997
|
|
Title:
|
METHOD OF MANUFACTURING A POLYSILICON GATE HAVING A DIMENSION BELOW THE PHOTOLITHOGRAPHY LIMITATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08966138
|
Filing Dt:
|
11/07/1997
|
|
Title:
|
METHOD FOR MONITORING AND ANALYZING MANUFACTURING PROCESSES USING STATISTICAL SIMULATION WITH SINGLE STEP FEEDBACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08966288
|
Filing Dt:
|
11/07/1997
|
|
Title:
|
SELF-ALIGNED SILICIDE GATE TECHNOLOGY FOR ADVANCED SUBMICRON MOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08966306
|
Filing Dt:
|
11/07/1997
|
|
Title:
|
FORMATION OF LOW RESISTIVITY TITANIUM SILICIDE GATES IN SEMICONDUCTOR INTEGRATED CIRCUITS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/06/2001
|
Application #:
|
08967889
|
Filing Dt:
|
11/12/1997
|
|
Title:
|
METHOD OF MAKING TRENCH ISOLATION STRUCTURES WITH OXIDIZED SILICON REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08967950
|
Filing Dt:
|
11/12/1997
|
|
Title:
|
FLOATING POINT STACK AND EXCHANGE INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08974970
|
Filing Dt:
|
11/20/1997
|
|
Title:
|
HARDWARE-BASED SYSTEM FOR ENABLING DATA TRANSFERS BETWEEN A CPU AND CHIP SET LOGIC OF A COMPUTER SYSTEM ON BOTH EDGES OF BUS CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
08975027
|
Filing Dt:
|
11/20/1997
|
|
Title:
|
SYSTEM AND METHOD OF CONTROLLING ACCESS TO PRIVILEGE
PARTITIONED ADDRESS SPACE FOR A MODEL SPECIFIC REGISTER FILE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
08976026
|
Filing Dt:
|
11/21/1997
|
|
Title:
|
POINT OF USE MIXING FOR LI/PLUG TUNGSTEN POLISHING SLURRY TO IMPROVE EXISTING SLURRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08977795
|
Filing Dt:
|
11/25/1997
|
|
Title:
|
ION IMPLANTATION PROCESS TO IMPROVE THE GATE OXIDE QUALITY AT THE EDGE OF A SHALLOW TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08979599
|
Filing Dt:
|
11/26/1997
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Title:
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METHOD OF SCALING DIELECTRIC THICKNESS IN A SEMICONDUCTOR PROCESS WITH ION IMPLANTATION
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08979876
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Filing Dt:
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11/26/1997
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Title:
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CONTROL OF JUNCTION DEPTH AND CHANNEL LENGHT USING GENERATED INTERSTITIAL GRADIENTS TO OPPOSE DOPANT DIFFUSION
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08980554
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Filing Dt:
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12/01/1997
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Title:
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EXTREME ULTRAVIOLET LITHOGRAPHY MASK BLANK AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08980883
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Filing Dt:
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11/26/1997
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Title:
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USE OF BOROPHOSPHOROUS TETRAETHYL ORTHOSICLICATE (BPTEOUS) TO IMPROVE ISOLATION IN A TRANSISTOR ARRAY
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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08980888
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Filing Dt:
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12/01/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING INORGANIC VAPOR SURFACE TREATMENT FOR PHOTORESIST ADHESION PROMOTION
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08980916
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Filing Dt:
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12/01/1997
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Title:
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PROCESS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING COBALT NIOBATE GATE ELECTRODE STRUCTURE
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08982198
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Filing Dt:
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12/01/1997
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE GATE ELECTRODE STRUCTURE
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08982230
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FABRICATING DISHING FREE SHALLOW ISOLATION TRENCHES
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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08982720
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Filing Dt:
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12/02/1997
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Title:
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DATA TRANSACTION TYPING FOR IMPROVED CACHING AND PREFETCHING CHARACTERISTICS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08984229
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Filing Dt:
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12/03/1997
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Title:
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VIA WITH BARRIER LAYER FOR IMPEDING DIFFUSION OF CONDUCTIVE MATERIAL FROM VIA INTO INSULATOR
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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08984352
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Filing Dt:
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12/03/1997
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Title:
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METHOD FOR FILLING HIGH ASPECT RATIO OPENINGS OF AN INTEGRATED CIRCUIT TO MINIMIZE ELECTROMIGRATION FAILURE
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08984547
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Filing Dt:
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12/03/1997
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Title:
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INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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08985467
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Filing Dt:
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12/05/1997
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Title:
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DISPOSITION TOOL FOR FACTORY PROCESS CONTROL
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08985470
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Filing Dt:
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12/05/1997
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Title:
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AUTOMATIC RECIPE ADJUST AND DOWNLOAD BASED ON PROCESS CONTROL WINDOW
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08985566
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Filing Dt:
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12/05/1997
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Title:
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DYNAMIC PROCESS WINDOW CONTROL USING SIMULATED WET DATA FROM CURRENT AND PREVIOUS LAYER DATA
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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08985915
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Filing Dt:
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12/05/1997
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Title:
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ON-CHIP TRANSFORMERS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08986086
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Filing Dt:
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12/05/1997
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Title:
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OPTIMIZATION OF LOGIC GATES WITH CRISS-CROSS IMPLANTS TO FORM ASYMMETIC CHANNEL REGIONS
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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08986087
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Filing Dt:
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12/05/1997
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Title:
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ELECTROPHORETIC COATING METHODOLOGY TO IMPROVE INTERNAL PACKAGE DELAMINATION AND WIRE BOND RELIABILITY
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08986098
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Filing Dt:
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12/05/1997
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Title:
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FORMING MINIMAL SIZE SPACES IN INTEGRATED CIRCUIT CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08986463
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Filing Dt:
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12/08/1997
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Title:
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METHOD FOR SILICON SURFACE CONTROL FOR SHALLOW JUNCTION FORMATION
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08987116
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Filing Dt:
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12/08/1997
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Title:
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METHOD OF FORMING AIR GAP SPACER FOR HIGH PERFORMANCE MOSFETS
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08987277
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Filing Dt:
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12/09/1997
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Title:
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STACKED MASK INTEGRATION TECHNIQUE FOR ADVANCED CMOS TRANSISTOR FORMATION
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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08987455
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Filing Dt:
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12/09/1997
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Title:
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SPACER FORMATION FOR PRECISE SALICIDE FORMATION
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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08988681
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Filing Dt:
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12/11/1997
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Title:
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BACKSIDE SILICON REMOVAL FOR FACE DOWN CHIP ANALYSIS
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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08989329
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Filing Dt:
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12/11/1997
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Title:
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COMPUTER SYSTEM WHICH PERFORMS INTELLIGENT BYTE SLICING ON A MULTI-BYTE WIDE BUS
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08989330
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Filing Dt:
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12/11/1997
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Title:
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INDEPENDENT USE OF BITS ON AN ON-CHIP BUS
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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08989741
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Filing Dt:
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12/12/1997
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Title:
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USE OF NITRIC OXIDE SURFACE ANNEAL TO PROVIDE REACTION BARRIER FOR DEPOSITION OF TANTALUM PENTOXIDE
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08989793
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Filing Dt:
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12/12/1997
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Title:
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APPARATUS AND METHOD FOR PREDICTING A FIRST MICROCODE INSTRUCTION OF A CACHE LINE AND USING PREDECODE INSTRUCTION DATA TO IDENTIFY INSTRUCTION BOUNDARIES AND TYPES
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08989794
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Filing Dt:
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12/12/1997
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Title:
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APPARATUS FOR EXTRACTING INSTRUCTION SPECIFIC BYTES FROM AN INSTRUCTION
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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08991107
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Filing Dt:
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12/16/1997
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Title:
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METHOD OF PREVENTING COMPUTER MALFUNCTION DURING A CHANGE OF POWER CONSUMPTION STATES VIA DYNAMIC ADJUSTMENT OF CORE VOLTAGE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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08991464
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Filing Dt:
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12/16/1997
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Title:
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TRENCH-GATED VERTICAL COMBINATION JFET AND MOSFET DEVICES
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08991808
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Filing Dt:
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12/16/1997
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Title:
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SILICON OXIDE INSULATOR (SOI) SEMICONDUCTOR HAVING SELECTIVELY LINKED BODY
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08991846
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Filing Dt:
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12/16/1997
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Title:
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WAY PREDICTION LOGIC FOR CACHE ARRAY
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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08991970
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Filing Dt:
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12/17/1997
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Title:
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OPERATING SYSTEM INCORPORATING DEBUG FEATURES TO ACCESS ON-CHIP TRACE MEMORY
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08992283
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Filing Dt:
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12/17/1997
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Title:
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REAL TIME INTERRUPT HANDLING FOR SUPERSCALAR PROCESSORS
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