|
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|
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Patent #:
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|
Issue Dt:
|
01/16/2001
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Application #:
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08992314
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Filing Dt:
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12/17/1997
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|
Title:
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COMBINED PARALLEL DEBUG AND TRACE PORT
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|
|
|
Patent #:
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|
Issue Dt:
|
12/28/1999
|
Application #:
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08992315
|
Filing Dt:
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12/17/1997
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|
Title:
|
TRACE SYNCHRONIZATION IN A PROCESSOR
|
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|
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Patent #:
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|
Issue Dt:
|
07/25/2000
|
Application #:
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08992361
|
Filing Dt:
|
12/17/1997
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|
Title:
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DEBUG INTERFACE INCLUDING A COMPACT TRACE RECORD STORAGE
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|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
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08992424
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Filing Dt:
|
12/18/1997
|
|
Title:
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APPARATUS AND METHOD FOR SELECTIVELY OUTPUTTING DATA USING A MAC LAYER INTERFACE OR A PCI BUS INTERFACE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
08/24/1999
|
Application #:
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08992430
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
BORDERLESS VIAS WITH HSQ GAP FILLED METAL PATTERNS HAVING HIGH ETCHING RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08992488
|
Filing Dt:
|
12/18/1997
|
|
Title:
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SIMPLIFIED SHALLOW TRENCH ISOLATION FORMATION WITH NO POLISH STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
08992490
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHALLOW TRENCH ISOLATION FORMATION WITH SIMPLIFIED REVERSE PLANARIZATION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08992492
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
INTERNAL RULES CHECKER DIAGNOSTIC MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08992735
|
Filing Dt:
|
12/17/1997
|
|
Title:
|
TRENCH ISOLATION STRUCTURE EMPLOYING PROTECTIVE SIDEWALL SPACERS UPON EXPOSED SURFACES OF THE ISOLATION TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
08992795
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
APPARATUS AND METHOD FOR GENERATING AN INDEX KEY FOR A NETWORK SWITCH ROUTING TABLE USING A PROGRAMMABLE HASH FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08992797
|
Filing Dt:
|
12/18/1997
|
|
Title:
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NETWORK SWITCH PORT CONFIGURED FOR GENERATING AN INDEX KEY FOR A NETWORK SWITCH ROUTING TABLE USING A PROGRAMMABLE HASH FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08992841
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
APPARATUS AND METHOD FOR GENERATING RATE CONTROL FRAMES IN A WORKGROUP SWITCH BASED ON TRAFFIC CONTRIBUTION FROM A NETWORK SWITCH PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
08992848
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND APPARATUS PROVIDING PROGRAMMABLE THRESHOLDS FOR HALF-DUPLEX FLOW CONTROL IN A NETWORK SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
08992921
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
INTEGRATED MULTIPORT SWITCH HAVING SHARED MEDIA ACCESS CONTROL CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
08992923
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
MULTIPORT DATA NETWORK SWITCH HAVING DIRECT MEDIA ACCESS CONTROL LINK TO EXTERNAL MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08992926
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND APPARATUS FOR MANAGING EXTERNAL PHYSICAL LAYER DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
08992927
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND APPARATUS FOR RECLAIMING BUFFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08992959
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD OF FORMING HIGH INTEGRITY VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08993029
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING DUAL GATE DIELECTRIC THICKNESS ALONG THE CHANNEL AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
08993046
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
VARIABLE 16 OR 32 BIT PCI INTERFACE WHICH SUPPORTS STEERING AND SWAPPING OF DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
08993048
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHARED ADDRESS TABLE WITH SOURCE AND DESTINATION TWO-PASS ALGORITHM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08993050
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
REDUCED CRACKING IN GAP FILLING DIELECTRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
08993056
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
APPARATUS AND METHOD IN A NETWORK INTERFACE DEVICE FOR STORING A DATA FRAME AND CORRESPONDING TRACKING INFORMATION IN A BUFFER MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08993060
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
OXIDE SPACERS AS SOLID SOURCES FOR GALLIUM DOPANT INTRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08993123
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
MULTI-TIERED INTERRUPT STRUCTURE WITH GLOBAL INTERRUPT ENABLEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
08993126
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
DUAL LAYER BOTTOM ANTI-REFLECTIVE COATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
08993127
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SYSTEM AND METHOD FOR PROGRAMMING LATE COLLISION SLOT TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2002
|
Application #:
|
08993147
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
QUEUING STRUCTURE AND METHOD FOR PRIORITIZATION OF FRAMES IN A NETWORK SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2000
|
Application #:
|
08993223
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A NITROGEN PUNCHTHROUGH REGION AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08993252
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING TAPERED SHALLOW TRENCH ISOLATION STRUCTURE PROFILE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08993383
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SEMICONDUCTOR ARRANGEMENT WITH LIGHTLY DOPED REGIONS UNDER A GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08993385
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND STRUCTURE FOR HIGH ASPECT GATE AND SHORT CHANNEL LENGTH INSULATED GATE FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08993390
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND STRUCTURE FOR AN ADVANCED ISOLATION SPACER SHELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
08993415
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
A METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING INTEGRATED ELECTRODE AND ISOLATION REGION FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
08993416
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING NITROGEN-BEARING OXIDE GATE INSULATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08993439
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
FEEDBACK LOOP FOR SELECTIVE CONDITIONING OF CHEMICAL MECHANICAL POLISHING PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08993455
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A GALLIUM AND NITROGEN CONTAINING BARRIER LAYER AND METHOD OF MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08993475
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHARING INSTRUCTION PRECODE INFORMATION IN A MULTIPROCESSOR SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08993569
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
APPARATUS AND METHOD FOR GENERATING A SERIAL DATA STREAM CARRYING DATA FOR MULTIPLE NETWORK SWITCH PORTS FOR USE BY A PHYSICAL TRANSCEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08993715
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
EXTERNAL RULES CHECKER INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08993755
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD OF FORMING SEMICONDUCTOR DEVICES USING GATE ELECTRODE LENGTH AND SPACER WIDTH FOR CONTROLLING DRIVE CURRENT STRENGTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08993827
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHALLOW TRENCH ISOLATION FORMATION WITH IMPROVED TRENCH EDGE OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
08993831
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND APPARATUS FOR SCALING NUMBER OF VIRTUAL LANS IN A SWITCH USING AN INDEXING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
08993832
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
MULTIPORT DATA SWITCH HAVING VARIABLE MAXIMUM PACKET LENGTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08993857
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHALLOW TRENCH ISOLATION WITH SPACERS FOR IMPROVED GATE OXIDE QUALITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08993868
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SILICON OXIME SPACER FOR PREVENTING OVER-ETCHING DURING LOCAL INTERCONNECT FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08993881
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
0
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08993883
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
TRENCH EDGE SPACER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08993887
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHODS FOR PREVENTING DELETERIOUS PUNCH-THROUGH DURING LOCAL INTERCONNECT FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
08993889
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
SHALLOW TRENCH ISOLATION FORMATION WITHOUT PLANARIZATION MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08993891
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
APPARATUS AND METHOD IN A NETWORK INTERFACE DEVICE FOR STORING TRACKING INFORMATION INDICATING STORED DATA STATUS BETWEEN CONTENDING MEMORY CONTROLLERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
08993918
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
RAPID THERMAL ANNEAL WITH A GASEOUS DOPANT SPECIES FOR FORMATION OF LIGHTLY DOPED REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08993925
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
FORMATION OF LIGHTLY DOPED REGIONS UNDER A GATE HAVING A REDUCED GATE OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08994143
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
TRENCH ISOLATION STRUCTURE PARTIALLY BOUND BETWEEN A PAIR OF LOW K DIELECTRIC STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08994182
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD FOR MAKING SEMICONDUCTOR DEVICE HAVING NITROGEN-RICH ACTIVE REGION-CHANNEL INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
08994200
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
PROCESS FOR BREAKING SILICIDE STRINGERS EXTENDING BETWEEN SILICIDE AREAS OF DIFFERENT ACTIVE REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08994253
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
TRENCH ISOLATION STRUCTURE HAVING LOW K DIELECTRIC SPACERS ARRANGED UPON AN OXIDE LINER INCORPORATED WITH NITROGEN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08994302
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A TRI-LAYER GATE INSULATING DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08994308
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
SUPPRESSION OF BORON SEGREGATION FOR SHALLOW SOURCE AND DRAIN JUNCTIONS IN SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08994356
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
APPARATUS AND METHOD TO IMPROVE ELECTROMIGRATION PERFORMANCE BY USE OF AMORPHOUS BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
08994502
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
OXIDE LINER FOR HIGH RELIABILITY WITH REDUCED ENCROACHMENT OF THE SOURCE/DRAIN REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
08994691
|
Filing Dt:
|
12/18/1997
|
|
Title:
|
METHOD AND APPARATUS FOR MANAGING LEARNING IN AN ADDRESS TABLE IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
08994702
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
APPARATUS AND METHOD FOR MONITORING THE PERFORMANCE OF A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08994710
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD FOR FABRICATION OF SHALLOW ISOLATION TRENCHES WITH SLOPED WALL PROFILES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08994807
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
SYSTEM FOR NON-SEQUENTIAL TRANSFER OF DATA PACKET PORTIONS WITH RESPECTIVE PORTION DESCRIPTIONS FROM A COMPUTER NETWORK PEREPHERAL DEVICE TO HOST MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08994960
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
DEFECT DIAGNOSIS USING SIMULATION FOR IC YIELD IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08995076
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING AN OXYGEN-RICH PUNCHTHROUGH REGION EXTENDING THROUGH THE LENGTH OF THE ACTIVE REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08999577
|
Filing Dt:
|
11/28/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING FLUORINE-ENHANCED TRANSISTOR WITH ELEVATED ACTIVE REGIONS AND FABRICATION THEREOF
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08999807
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Filing Dt:
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11/26/1997
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Title:
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DUCT PROCESSOR COOLING FOR PERSONAL COMPUTER
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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09002651
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Filing Dt:
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01/05/1998
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Title:
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SEMICONDUCTOR DEVICE WITH A GRADED PASSIVATION LAYER
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09002655
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Filing Dt:
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01/05/1998
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Title:
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RING OSCILLATOR TEST STRUCTURE
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09002656
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Filing Dt:
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01/05/1998
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Title:
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METHOD FOR MAKING ASYMMETRICAL GATE OXIDE THICKNESS IN CHANNEL MOSFET REGION
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09002725
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Filing Dt:
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01/05/1998
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Title:
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INTEGRATION OF HIGH K SPACERS FOR DUAL GATE OXIDE CHANNEL FABRICATION TECHNIQUE
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09002902
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Filing Dt:
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01/05/1998
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Title:
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EMBEDDING TWO DIFFERENT INSTRUCTION SETS WITHIN A SINGLE LONG INSTRUCTION WORD USING PREDECODE BITS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09002964
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Filing Dt:
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01/05/1998
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Title:
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HIGH PERFORMANCE MOSFET WITH MODULATED CHANNEL GATE THICKNESS
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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09003668
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Filing Dt:
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01/07/1998
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Title:
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"MANUFACTURING METHOD FOR WAFER SLICE STARTING MATERIAL TO OPTIMIZE EXTRINSIC GETTERING DURING SEMICONDUCTOR FABRICATION"
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09007138
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Filing Dt:
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01/14/1998
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Title:
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COMPUTER IMPLEMENTED METHOD AND PROGRAM FOR AUTOMATING FLIP-CHIP BUMP LAYOUT IN INTEGRATED CIRCUIT PACKAGE DESIGN
|
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|
|
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09008394
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Filing Dt:
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01/16/1998
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Title:
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WRITE-BUFFER FIFO ARCHITECTURE WITH RANDOM ACCESS SNOOPING CAPABILITY
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09009074
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Filing Dt:
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01/20/1998
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Title:
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SINGLE-PORT TRACE BUFFER ARCHITECTURE WITH OVERFLOW REDUCTION
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Patent #:
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Issue Dt:
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01/04/2000
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Application #:
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09009787
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Filing Dt:
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01/20/1998
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Title:
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SHORT CHANNEL LENGTH MOSFET TRANSISTOR
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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09012006
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Filing Dt:
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01/22/1998
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Title:
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SEMICONDUCTOR INTERCONNECT STRUCTURE WITH AIR GAP FOR REDUCING INTRALAYER CAPACITANCE IN METAL LAYERS IN DAMASCENE METALIZATION PROCESS
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09014192
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Filing Dt:
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01/27/1998
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Title:
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INTERLEVEL DIELECTRIC WITH AIR GAPS TO LESSEN CAPACITIVE COUPLING
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|
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09014455
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Filing Dt:
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01/28/1998
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Title:
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METHOD AND APPARATUS FOR SIMULTANEOUSLY PERFORMING ARITHMETIC ON TWO OR MORE PAIRS OF OPERANDS
|
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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09015087
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Filing Dt:
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01/29/1998
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Title:
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A METHOD FOR DETECTING UPDATES TO INSTRUCTIOND WHICH ARE WITHIN AN INSTUCTION PROCESSING PIPELINE OF A MICROPROCESSOR
|
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09017676
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Filing Dt:
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02/03/1998
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Title:
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SELF-ENCAPSULATED COPPER METALLIZATION
|
|
|
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09020175
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Filing Dt:
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02/06/1998
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Title:
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REDUCED BORON DIFFUSION BY USE OF A PRE-ANNEAL
|
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|
|
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09020673
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Filing Dt:
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02/09/1998
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Title:
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LEAD FRAME WITH STRIP-SHAPED DIE BONDING PAD
|
|
|
|
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09022129
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Filing Dt:
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02/11/1998
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Title:
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METHOD OF FORMING SEMICONDUCTOR DEVICES USING GATE ELECTRODE DIMENSIONS AND DOPANT CONCENTRATION FOR CONTROLLING DRIVE CURRENT STRENGTH
|
|
|
|
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09023836
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Filing Dt:
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02/13/1998
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Title:
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METHOD AND SYSTEM FOR PROVIDING A CONTACT ON A SEMICONDUCTOR DEVICE
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|
|
|
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09024293
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Filing Dt:
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02/17/1998
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Title:
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SYSTEM FOR PREVENTING A DMA CONTROLLER FROM EVALUATING ITS DRQ INPUT ONCE A DMA OPERATION HAS STARTED UNTIL THE DRQ INPUT HAS BEEN UPDATED
|
|
|
|
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09024475
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Filing Dt:
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02/17/1998
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|
Title:
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METHOD FOR FORMING AN INTERGRATED CIRCUIT HAVING IMPROVED POLYSILICON RESISTOR STRUCTURES
|
|
|
|
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Patent #:
|
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Issue Dt:
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08/15/2000
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Application #:
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09025233
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Filing Dt:
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02/18/1998
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Title:
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Converting Regoster Data From A First Format Type To A Second Format Type If A Second Type Instruction Consumes Data Produced By A First Type Instruction
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|
|
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Patent #:
|
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Issue Dt:
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11/02/1999
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Application #:
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09026285
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Filing Dt:
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02/19/1998
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Title:
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PROCESS FOR FORMING AN ISOLATION REGION WITH A TRENCH CAP
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|
|
|
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09027573
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Filing Dt:
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02/23/1998
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Title:
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INTEGRATED CIRCUIT EMPLOYING SIMULTANEOUSLY FORMED ISOLATION AND TRANSISTOR TRENCHES
|
|
|
|
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Patent #:
|
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Issue Dt:
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03/14/2000
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Application #:
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09028895
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Filing Dt:
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02/24/1998
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Title:
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TRENCH TRANSISTOR AND ISOLATION TRENCH
|
|
|
|
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Patent #:
|
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Issue Dt:
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03/13/2001
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Application #:
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09028896
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Filing Dt:
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02/24/1998
|
|
Title:
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TRENCH TRANSISTOR WITH INSULATIVE SPACERS
|
|
|
|
|
Patent #:
|
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Issue Dt:
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10/05/1999
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Application #:
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09030052
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Filing Dt:
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02/24/1998
|
|
Title:
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TRENCH TRANSISTOR WITH METAL SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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05/18/1999
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Application #:
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09031570
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Filing Dt:
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02/26/1998
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Title:
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ULTRA SHORT TRENCH TRANSISTORS AND PROCESS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
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Issue Dt:
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02/29/2000
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Application #:
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09034589
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Filing Dt:
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03/04/1998
|
|
Title:
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INTEGRATED CIRCUIT WHICH USES A RECESSED LOCAL CONDUCTOR FOR PRODUCING STAGGERED INTERCONNECT LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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08/28/2001
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Application #:
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09036127
|
Filing Dt:
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03/06/1998
|
|
Title:
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IMPROVED DAMASCENE METAL INTERCONNECTS USING HIGHLY DIRECTIONAL DEPOSITION OF BARRIER AND/OR SEED LAYERS INCLUDING (111) FILLING METAL
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