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07/17/2001
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03/09/1998
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08/29/2000
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03/10/1998
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03/07/2000
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03/10/1998
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02/15/2000
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03/10/1998
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08/22/2000
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03/11/1998
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02/08/2000
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03/16/1998
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08/08/2000
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03/17/1998
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08/15/2000
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03/17/1998
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09/28/1999
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03/17/1998
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01/09/2001
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03/25/1998
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03/14/2000
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03/27/1998
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12/28/1999
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03/30/1998
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10/19/1999
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03/30/1998
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05/08/2001
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03/30/1998
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06/20/2000
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03/31/1998
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10/19/1999
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04/07/1998
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10/02/2001
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04/06/1998
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03/07/2000
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04/06/1998
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11/07/2000
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04/07/1998
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12/09/2003
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04/07/1998
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07/10/2001
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04/07/1998
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MULTIPLE SPLIT GATE SEMICONDUCTOR DEVICE AND FABRICATION METHOD
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07/04/2000
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04/07/1998
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08/01/2000
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04/08/1998
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03/16/1999
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04/08/1998
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06/13/2000
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04/13/1998
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10/31/2000
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04/14/1998
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08/29/2000
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04/16/1998
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01/09/2001
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04/16/1998
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12/07/1999
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04/17/1998
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04/27/2004
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04/21/1998
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METHOD OF MAKING ENHANCED TRENCH OXIDE WITH LOW TEMPERATURE NITROGEN INTEGRATION
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11/30/1999
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04/20/1998
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INTERLEVEL DIELECTRIC WITH MULTIPLE AIR GAPS BETWEEN CONDUCTIVE LINES OF AN INTEGRATED CIRCUIT
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06/13/2000
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04/21/1998
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METHOD AND STRUCTURE FOR ISOLATING SEMICONDUCTOR DEVICES AFTER TRANSISTOR FORMATION
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05/09/2000
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04/23/1998
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PROCESSOR CONFIGURED TO SELECT A NEXT FETCH ADDRESS BY PARTIALLY DECODING A BYTEOF A CONTROL TRANSFER INSTRUCTION
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10/17/2000
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04/23/1998
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Control Transfer Indication In Predecode Which Identifies Control Transfer Instructions And An Alternate Feature Of An Instruction
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09/11/2001
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09065352
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04/23/1998
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07/04/2000
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09065508
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04/24/1998
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GRADED MOS TRANSISTOR JUNCTION FORMED BY ALIGNING A SEQUENCE OF IMPLANTS TO A SELECTIVELY REMOVABLE POLYSILICON SIDEWALL SPACE AND OXIDE THERMALLY GROWN THEREON
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12/26/2000
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04/23/1998
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12/07/1999
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04/28/1998
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MULTILEVEL INTERCONNECT STRUCTURE OF AN INTEGRATED CIRCUIT HAVING AIR GAPS AND PILLARS SEPARATING LEVELS OF INTERCONNECT
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08/14/2001
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04/28/1998
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08/29/2000
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04/29/1998
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FORMULATION OF HIGH PERFORMANCE TRANSISTORS USING GATE TRIM ETCH PROCESS
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07/25/2000
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04/29/1998
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11/23/1999
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04/30/1998
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TRANSISTOR WITH ULTRA SHORT LENGTH DEFINED PARTIALLY BY SIDEWALL OXIDATION OF A GATE CONDUCTOR OVERLYING THE CHANNEL LENGTH
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01/16/2001
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04/30/1998
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08/14/2001
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05/05/1998
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02/22/2000
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05/06/1998
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METHOD FOR PREDICTING PERFORMANCE OF MICROELECTRONIC DEVICE BASED ON ELECTRICAL PARAMETER TEST DATA USING COMPUTER MODULE
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08/12/2003
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05/07/1998
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08/22/2000
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05/08/1998
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08/08/2000
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05/08/1998
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04/17/2001
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05/12/1998
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08/07/2001
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05/12/1998
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04/04/2000
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05/15/1998
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01/23/2001
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05/18/1998
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02/27/2001
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05/18/1998
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06/06/2000
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05/18/1998
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04/25/2000
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05/19/1998
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06/20/2000
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05/20/1998
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07/04/2000
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05/26/1998
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03/20/2001
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05/29/1998
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06/13/2000
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06/01/1998
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05/07/2002
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06/01/1998
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01/30/2001
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06/01/1998
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04/03/2001
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06/01/1998
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05/09/2000
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06/02/1998
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COMPUTER SYSTEM WHICH PERFORMS INTELLIGENT BYTE SLICING/DATA PACKING ON A MULTI-BYTE WIDE BUS
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01/09/2001
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06/04/1998
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05/01/2001
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06/04/1998
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SEMICONDUCTOR DEVICE HAVING METAL GATE ELECTRODE AND TITANIUM OR TANTALUM NITRIDE GATE DIELECTRIC BARRIER LAYER AND PROCESS OF FABRICATION THEREOF
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06/29/1999
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09093423
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Filing Dt:
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06/08/1998
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Title:
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"REDUCED CHANNEL LENGTH FOR A HIGH PERFORMANCE CMOS TRANSISTOR"
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09093580
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Filing Dt:
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06/08/1998
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Title:
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SELF-ALIGNED SOI DEVICE WITH BODY CONTACT AND NISI2 GATE
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09094183
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Filing Dt:
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06/09/1998
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Title:
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"MEANS USED TO ALLOW DRIVER SOFTWARE TO SELECT MOST APPROPRIATE EXECUTION CONTEXT DYNAMICALLY"
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09098360
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Filing Dt:
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06/17/1998
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Title:
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A communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09098482
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Filing Dt:
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06/16/1998
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Title:
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BIPARTITE LOOK-UP TABLE WITH OUTPUT VALUES HAVING MINIMIZED ABSOLUTE ERROR
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09098642
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Filing Dt:
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06/17/1998
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Title:
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PERSONAL COMPUTER SYSTEM INCORPORATING AN ISOCHRONOUS MULTI-CHANNEL, MULTI-RATE DATA BUS
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09098655
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Filing Dt:
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06/17/1998
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Title:
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MULTI-CHANNEL, MULTI-RATE ISOCHRONOUS DATA BUS
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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09098704
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Filing Dt:
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06/17/1998
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Title:
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INCORPORATING SILICON ATOMS INTO A METAL OXIDE GATE DIELECTRIC USING GAS CLUSTER ION BEAM IMPLANTATION
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09099984
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Filing Dt:
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06/19/1998
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Title:
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SELECTING CACHE TO FETCH IN MULTI-LEVEL CACHE SYSTEM BASED ON FETCH ADDRESS SOURCE AND PRE-FETCHING ADDITIONAL DATA TO THE CACHE FOR FUTURE ACCESS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09100026
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Filing Dt:
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06/19/1998
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Title:
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APPARATUS AND METHOD OF DETERMINING A LINK STATUS BETWEEN NETWORK STATIONS CONNECTED TO A TELEPHONE LINE MEDIUM
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09102090
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Filing Dt:
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06/23/1998
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Title:
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ENERGY BASED PULSE POSITION DETECTOR FOR TELEPHONE WIRE NETWORKS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09103699
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Filing Dt:
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06/24/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING REDUCED OVERLAP CAPACITANCE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09104047
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Filing Dt:
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06/24/1998
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Title:
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A METHOD AND SYSTEM USING TAGGED INSTRUCTIONS TO ALLOW OUT-OF-PROGRAM-ORDER INSTRUCTION DECODING
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09105779
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Filing Dt:
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06/26/1998
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Title:
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MICROCONTROLLER ARCHITECTURE AND ASSOCIATED METHOD PROVIDING FOR TESTING OF AN ON-CHIP MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09105980
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Filing Dt:
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06/26/1998
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Title:
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SYSTEM AND METHOD FOR CONTROLLING A MULTI-ARM POLISHING TOOL
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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09106769
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Filing Dt:
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06/30/1998
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Title:
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ELEVATED SALICIDE TECHNOLOGY
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09108531
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Filing Dt:
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07/01/1998
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Title:
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TRACE ON/OFF USE WITH BREAKPOINT REGISTER
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09108783
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Filing Dt:
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07/02/1998
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Title:
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TANTALUM BARRIER METAL REMOVAL BY USING CF4/O2 PLASMA DRY ETCH
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09109113
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Filing Dt:
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07/02/1998
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Title:
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DUAL DAMASCENE PROCESS USING HIGH SELECTIVITY BOUNDARY LAYERS
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09109440
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Filing Dt:
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07/02/1998
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Title:
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MASTER ISOCHRONOUS CLOCK STRUCTURE HAVING A CLOCK CONTROLLER COUPLING TO A CPU AND TWO DATA BUSES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09109822
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Filing Dt:
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07/02/1998
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Title:
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DATA RATE SYNCHRONIZATION BY FRAME RATE ADJUSTMENT
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09109835
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Filing Dt:
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07/02/1998
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Title:
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SOFTWARE BASED CLOCK SYNCHRONIZATION
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09110518
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Filing Dt:
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07/06/1998
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Title:
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MICROPROCESSOR INCLUDING MULTIPLE REGISTER FILES MAPPED TO THE SAME LOGICAL STORAGE AND INHIBITING SYNCHRONIZATION BETWEEN THE REGISTER FILES RESPONSIVE TO INCLUSION OF AN INSTRUCTION IN AN INSTRUCTION SEQUENCE
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09110519
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Filing Dt:
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07/06/1998
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Title:
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PROCESSOR CONFIGURED TO SELECTIVELY CANCEL INSTRUCTIONS FROM ITS PIPELINE RESPONSIVE TO A PREDICTED-TAKEN SHORT FORWARD BRANCH INSTRUCTION
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09112146
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Filing Dt:
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07/09/1998
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Title:
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CONCURRENT EXECUTION OF MULTIPLE INSTRUCTIONS IN CYCLIC COUNTER BASED LOGIC COMPONENT OPERATION STAGES
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09112161
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Filing Dt:
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07/09/1998
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Title:
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METHOD OF FORMING RELIABLE COPPER INTERCONNECTS
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09112472
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Filing Dt:
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07/09/1998
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Title:
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COPPER INTERCONNECT WITH IMPROVED ELECTROMIGRATION RESISTANCE
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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09112529
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Filing Dt:
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07/08/1998
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Title:
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ULTRA THIN HIGH K SPACER MATERIAL FOR USE IN TRANSISTOR FABRICATION
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09113436
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Filing Dt:
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07/10/1998
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Title:
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METALORGANIC DECOMPOSITION DEPOSITION OF THIN CONDUCTIVE FILM ON INTEGRATED CIRCUITS USING REDUCING AMBIENT
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09115123
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Filing Dt:
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07/14/1998
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Title:
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Processor Configured To Generate Lookahead Results From Operand Collapse Unit And For Inhibiting Receipt/Execution Of The First Instruction Based On The Lookahead Result
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09116066
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Filing Dt:
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07/15/1998
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Title:
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FORMING A SELF-ALIGNED SILICIDE GATE CONDUCTOR TO A GREATER THICKNESS THAN JUNCTION SILICIDE STRUCTURES USING A DUAL-SALICIDATION PROCESS
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09116417
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Filing Dt:
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07/15/1998
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Title:
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TRANSISTOR HAVING A NITROGEN INCORPORATED EPITAXIALLY GROWN GATE DIELECTRIC AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09116631
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Filing Dt:
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07/16/1998
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Title:
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METHOD AND CIRCUIT FOR PRELOADING PREDICTION CIRCUITS IN MICROPROCESSORS
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Patent #:
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Issue Dt:
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01/11/2000
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Application #:
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09118389
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Filing Dt:
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07/17/1998
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Title:
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IMPROVED LDD TRANSISTOR USING NOVEL GATE TRIM TECHNIQUE
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09123177
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Filing Dt:
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07/27/1998
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Title:
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BURIED LOCAL INTERCONNECT
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