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08/08/2000
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09123657
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Filing Dt:
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07/28/1998
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Title:
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METHOD OF MAKING ULTRA THIN GATE OXIDE USING ALUMINUM OXIDE
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Issue Dt:
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08/29/2000
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09123673
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Filing Dt:
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07/28/1998
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Title:
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METHOD OF INTEGRATION OF NITROGEN BEARING HIGH K FILM
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Patent #:
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06/26/2001
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09124098
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Filing Dt:
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07/29/1998
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Title:
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PREFETCH INSTRUCTION MECHANISM FOR PROCESSOR
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01/02/2001
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09124604
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Filing Dt:
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07/29/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING GROWN OXIDE SPACERS AND METHOD OF MANUFACTURE THEREOF
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Issue Dt:
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05/08/2001
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09127094
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Filing Dt:
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07/31/1998
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Title:
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PROCESSOR CONFIGURED TO SELECTIVELY FREE PHYSICAL REGISTERS UPON RETIREMENT OF INSTRUCTIONS BASED ON WHETHER OR NOT THE PHYSICAL REGISTERS ARE STILL IN USE FOR OTHER LOGICAL REGISTERS
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Issue Dt:
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09/19/2000
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09127100
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Filing Dt:
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07/31/1998
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Title:
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PROCESSOR CONFIGURED TO MAP LOGICAL REGISTER NUMBERS TO PHYSICAL REGISTER NUMBERS USING VIRTUAL REGISTER NUMBERS
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Issue Dt:
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09/12/2000
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09127294
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Filing Dt:
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07/31/1998
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Title:
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MAP UNIT HAVING RAPID MISPREDICTION RECOVERY
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Patent #:
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06/12/2001
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09128235
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08/03/1998
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Title:
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TRENCH AND GATE DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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03/11/2003
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09129703
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08/05/1998
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Title:
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ADVANCED FRABRICATION TECHNIQUE TO FORM ULTRA THIN GATE DIELECTRIC USING A SACRIFICAL POLYSILICON SEED LAYER
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Patent #:
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Issue Dt:
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04/02/2002
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09130528
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08/04/1998
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Title:
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STATISTICAL PROCESS WINDOW DESIGN METHODOLOGY
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05/16/2000
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09131284
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Filing Dt:
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08/07/1998
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Title:
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DEVICE LEVEL IDENTIFICATION METHODOLOGY
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Patent #:
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05/09/2000
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09131919
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Filing Dt:
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08/10/1998
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Title:
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METHOD FOR MAKING MULTILAYERED COAXIAL INTERCONNECT STRUCTURE
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Patent #:
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01/09/2001
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09132282
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Filing Dt:
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08/11/1998
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Title:
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A SEMICONDUCTOR DEVICE HAVING AN INTERMETALLIC LAYER ON METAL INTERCONNECTS
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Patent #:
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05/01/2001
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09132980
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08/12/1998
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Title:
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MODIFYING A DESIGN LAYER OF AN INTEGRATED CIRCUIT USING OVERLYING AND UNDERLYING DESIGN LAYERS
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Issue Dt:
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01/09/2001
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09135493
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08/17/1998
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Title:
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MECHANISM TO DETERMINE ACTUAL CODE EXECUTION FLOW IN A COMPUTER
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09135826
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Filing Dt:
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08/18/1998
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Title:
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HIGH PERFORMANCE MOSFET AND METHOD OF FORMING THE SAME USING SALICIDATION AND JUNCTION IMPLANTATION PRIOR TO GATE FORMATION
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Patent #:
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Issue Dt:
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01/16/2001
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09137275
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08/20/1998
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Title:
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METHOD OF MAKING HIGH PERFORMANCE MOSFET WITH POLISHED GATE AND SOURCE/DRAIN FEATURE
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05/07/2002
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09137570
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08/21/1998
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Title:
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METHOD TO DYNAMICALY CHANGE MICROPROCESSOR TEST SOFTWARE TO REFLECT DIFFERENT SILICON REVISION LEVELS
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08/06/2002
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09137572
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08/21/1998
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Title:
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METHOD FOR UTILIZING VIRTUAL HARDWARE DESCRIPTIONS TO ALLOW FOR MULTI-PROCESSOR DEBUGGING IN ENVIRONMENTS USING VARYING PROCESSOR REVISION LEVELS
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01/16/2001
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09137583
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08/21/1998
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Title:
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METHOD AND APPARATUS FOR CONCURRENTLY EXECUTING MULTIPLICATION AND ITERATIVE OPERATIONS
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Issue Dt:
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04/03/2001
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09138886
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08/24/1998
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Title:
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MECHANISM FOR LOAD BLOCK ON STORE ADDRESS GENERATION
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Issue Dt:
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09/28/1999
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09138989
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08/24/1998
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Title:
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REDUCTION OF DOPANT DIFFUSION BY THE CO-IMPLANTATION OF IMPURITIES INTO THE TRANSISTOR GATE CONDUCTOR
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Issue Dt:
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09/19/2000
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09139056
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08/24/1998
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Title:
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SYMMETRICAL INSTRUCTIONS QUEUE FOR HIGH CLOCK FREQUENCY SCHEDULING
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Patent #:
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Issue Dt:
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04/03/2001
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09139178
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08/24/1998
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Title:
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UNIVERSAL DEPENDENCY VECTOR/QUEUE ENTRY
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Patent #:
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Issue Dt:
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07/31/2001
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09139870
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08/25/1998
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Title:
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ERROR REPORTING MECHANISM FOR AN AGP CHIPSET DRIVER USING A REGISTRY
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Patent #:
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Issue Dt:
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03/28/2000
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09140202
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Filing Dt:
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08/26/1998
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Title:
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SEMICONDUCTOR GATE CONDUCTOR WITH A SUBSTANTIALLY UNIFORM DOPING PROFILE HAVING MINIMAL SUSCEPTIBILITY TO DOPANT PENETRATION INTO THE UNDERLYING GATE DIELECTRIC
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Patent #:
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Issue Dt:
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10/03/2000
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09143105
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Filing Dt:
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08/28/1998
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Title:
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INTERCONNECT STRUCTURE WITH LOW K DIELECTRIC MATERIALS AND METHOD OF MAKING THE SAME WITH SINGLE AND DUAL DAMASCENE TECHNIQUES
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Issue Dt:
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12/12/2000
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09146163
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09/03/1998
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Title:
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NETWORK INTERFACE DEVICE ARCHITECTURE FOR STORING TRANSMIT AND RECEIVE DATA IN A RANDOM ACCESS BUFFER MEMORY ACROSS INDEPENDENT CLOCK DOMAINS
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Patent #:
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Issue Dt:
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11/28/2000
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09146168
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Filing Dt:
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09/03/1998
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Title:
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SELECTIVELY STORING STATUS INFORMATION ASSOCIATED WITH A DATA FRAME IN A HOLDING REGISTER BASED ON AN ASYNCHRONOUS DETERMING STOP
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Patent #:
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Issue Dt:
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11/07/2000
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09146251
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Filing Dt:
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09/03/1998
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Title:
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SYSTEM FOR TRANSFERRING FRAME DATA BY TRANSFERRING THE DESCRIPTOR INDEX DATA TO IDENTIFY A SPECIFIED AMOUNT OF DATA TO BE TRANSFERRED STORED IN THE HOST COMPUTER
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Issue Dt:
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08/22/2000
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09148095
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09/04/1998
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Title:
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METHOD OF MAKING HIGH PERFORMANCE TRANSISTORS USING CHANNEL MODULATED IMPLANT FOR ULTRA THIN OXIDE FORMATION
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Patent #:
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Issue Dt:
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10/23/2001
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09148193
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09/04/1998
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Title:
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BUMP SCRUB AFTER PLATING
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Patent #:
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Issue Dt:
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04/20/2004
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09148923
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09/04/1998
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SYSTEM-ON-A-CHIP WITH VARIABLE BANDWIDTH
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Issue Dt:
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03/07/2000
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09149208
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09/08/1998
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Title:
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SCALED INTERCONNECT ANODIZATION FOR HIGH FREQUENCY APPLICATIONS
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10/03/2000
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09149398
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09/08/1998
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Title:
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SEMICONDUCTOR DEVICE WITH A REDUCED WIDTH GATE DIELECTRIC AND METHOD OF MAKING SAME
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Issue Dt:
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02/20/2001
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09150874
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09/10/1998
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Title:
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METHOD OF TILTED IMPLANT FOR POCKET, HALO AND SOURCE/DRAIN EXTENSION IN ULSI DENSE STRUCTURES
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01/09/2001
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09151861
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09/11/1998
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Title:
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IMPLEMENTATION OF THE AGP REQUEST QUEUES USING FIFOS
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01/01/2002
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09152043
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09/11/1998
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Title:
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RISC86 INSTRUCTION SET
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Issue Dt:
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05/22/2001
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09152748
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09/14/1998
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Title:
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A NETWORK INTERFACE UNIT INCLUDING A MICROCONTROLLER HAVING MULTIPLE CONFIGURABLE LOGIC BLOCKS WITH A TEST/PROGRAM BUS FOR PERFORMING A PLURALITY OF SELECTED FUNCTIONS
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08/13/2002
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09153753
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09/15/1998
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Title:
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SEMICONDUCTOR FABRICATION EMPLOYING BARRIER ATOMS INCORPORATED AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
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Issue Dt:
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01/11/2000
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09153770
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Filing Dt:
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09/15/1998
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Title:
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SUPERSCALAR MICROPROCESSOR CONFIGURED TO PREDICT RETURN ADDRESSES FROM A RETURN STACK STORAGE
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01/13/2004
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09153807
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09/15/1998
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IMPROVING THE ELECTROMIGRATION CHARACTERISTICS OF PATTERNED METAL FEATURES IN SEMICONDUCTOR DEVICES
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Issue Dt:
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02/20/2001
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09157626
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09/21/1998
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USING MULTIPLE DECODERS AND A REORDER QUEUE TO DECODE INSTRUCTIONS OUT OF ORDER
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Issue Dt:
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10/01/2002
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09157648
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09/21/1998
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Title:
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USING SEPARATE CACHES FOR VARIABLE AND GENERATED FIXED-LENGTH INSTRUCTIONS
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06/26/2001
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09157719
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09/21/1998
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Title:
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FORCING REGULARITY INTO A CISC INSTRUCTION SET BY PADDING INSTRUCTIONS
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Issue Dt:
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10/31/2000
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09158465
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09/22/1998
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Title:
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SYSTEM FOR STORE TO LOAD FORWARDING OF INDIVIDUAL BYTES FROM SEPARATE STORE BUFFER ENTRIES TO FORM A SINGLE LOAD WORD
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04/11/2000
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09160830
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09/25/1998
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Title:
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SIGNAL CARRYING MEANS INCLUDING A CARRIER SUBSTRATE AND WIRE BONDS FOR CARRYING SIGNALS BETWEEN THE CACHE AND LOGIC CIRCUITRY OF A MICROPROCESSOR
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12/18/2001
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09161062
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09/25/1998
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Title:
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METHOD TO IMPROVE CHIP SCALE PACKAGE ELECTROSTATIC DISCHARGE PERFORMANCE AND SUPPRESS MARKING ARTIFACTS
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Issue Dt:
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08/07/2001
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Application #:
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09161878
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09/28/1998
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EFFICIENT TOOL UTILIZATION USING PREVIOUS SCAN DATA
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08/14/2001
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09162116
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09/28/1998
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Title:
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SIMPLIFIED GRADED LDD TRANSISTOR USING CONTROLLED POLYSILICON GATE PROFILE
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Issue Dt:
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09/11/2001
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09162426
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09/28/1998
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Title:
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METHOD FOR FABRICATING GRADED LDD TRANSISTOR USING CONTROLLED POLYSILICON GATE PROFILE
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Patent #:
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Issue Dt:
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01/30/2001
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09162917
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09/29/1998
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Title:
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METHOD FOR FORMING POLYSILICONGERMANIUM GATE IN CMOS TRANSISTOR AND DEVICE MADE THEREBY
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Issue Dt:
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01/16/2001
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09163795
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Filing Dt:
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09/30/1998
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Title:
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AN ADVANCED ISOLATION STRUCTURE FOR HIGH DENSITY SEMICONDUCTOR DEVICES
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Issue Dt:
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05/01/2001
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09163840
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09/30/1998
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Title:
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NON-UNIFORM GATE/DIELECTRIC FIELD EFFECT TRANSISTOR
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03/06/2001
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09164823
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10/01/1998
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METHOD FOR PROVIDING COOPERATIVE RUN-TO-RUN CONTROL FOR MULTI-PRODUCT AND MULTI-PROCESS SEMICONDUCTOR FABRICATION
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01/15/2002
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09165609
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10/02/1998
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Title:
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USING PADDED INSTRUCTIONS IN A BLOCK-ORIENTED CACHE
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Issue Dt:
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08/22/2000
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09165783
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10/02/1998
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METHOD TO MANUFACTURE MULTIPLE DAMASCENE BY UTILIZING ETCH SELECTIVITY
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Issue Dt:
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12/26/2000
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09165950
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10/02/1998
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INFORMATION PACKET RECEPTION INDICATOR FOR REDUCING THE UTILIZATION OF A HOST SYSTEM PROCESSOR UNIT
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12/05/2000
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09166440
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10/05/1998
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CIRCUIT AND METHOD FOR REDUCING DATA DEPENDENCIES BETWEEN INSTRUCTIONS
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Issue Dt:
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08/28/2001
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09167622
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10/06/1998
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DEVICE AND METHOD FOR ETCHING NITRIDE SPACERS FORMED UPON AN INTEGRATED CIRCUIT GATE CONDUCTOR
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Issue Dt:
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10/05/1999
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09168761
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10/08/1998
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REDUCED BIRD'S BEAK FIELD OXIDATION PROCESS USING NITROGEN IMPLANTED INTO ACTIVE REGION
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Issue Dt:
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09/12/2000
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09169281
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10/08/1998
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Title:
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METHOD FOR IMPLANTING SEMICONDUCTOR CONDUCTIVE LAYERS
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Patent #:
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Issue Dt:
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01/11/2005
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09170221
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10/13/1998
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Title:
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APPARATUS AND METHOD FOR SECURE MEDIA INDEPENDENT INTERFACE COMMUNICATIONS BY CORRUPTING TRANSMIT DATA ON SELECTED REPEATER PORT
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Issue Dt:
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11/28/2000
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09170619
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10/13/1998
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Title:
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METHOD OF FABRICATING ULTRA SHALLOW JUNCTION CMOS TRANSISTORS WITH NITRIDE DISPOSABLE SPACER
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11/07/2000
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09172088
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10/14/1998
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Title:
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SHALLOW TRENCH ISOLATION FORMATION WITH SPACER-ASSISTED ION IMPLANTATION
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Issue Dt:
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05/08/2001
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09172982
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10/14/1998
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Title:
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METHOD OF MAKING DUAL DAMASCENE CONDUCTIVE INTERCONNECTIONS AND INTEGRATED CIRCUIT DEVICE COMPRISING SAME
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09173015
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Filing Dt:
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10/15/1998
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Title:
|
INTEGRATION OF ISOLATION WITH EPITAXIAL GROWTH REGIONS FOR ENHANCED DEVICE FORMATION
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09173233
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Filing Dt:
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10/15/1998
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Title:
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TRANSISTOR HAVING A METAL SILICIDE SELF-ALIGNED TO THE GATE
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09174037
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Filing Dt:
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10/16/1998
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Title:
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MECHANISM FOR MINIMIZING OVERHEAD USAGE OF A HOST SYSTEM BY POLLING FOR SUBSEQUENT INTERRUPTS AFTER SERVICE OF A PRIOR INTERRUPT
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09174900
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Filing Dt:
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10/19/1998
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Title:
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METHOD AND SYSTEM FOR DATA TRANSMISSION IN ACCELERATED GRAPHICS PORT SYSTEMS
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Patent #:
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Issue Dt:
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09/28/1999
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Application #:
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09175193
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Filing Dt:
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10/20/1998
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Title:
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AIR GAP SPACER FORMATION FOR HIGH PERFORMANCE MOSFETS
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09175652
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Filing Dt:
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10/20/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING SILICIDE LAYERS FORMED USING A COLLIMATED METAL LAYER
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09175709
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Filing Dt:
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10/20/1998
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Title:
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MECHANISM FOR SYNCHRONIZING SERVICE OF INTERRUPTS BY A PLURALITY OF DATA PROCESSORS
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09175800
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Filing Dt:
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10/20/1998
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Title:
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SEMICONDUCTOR FABRICATION EMPLOYING SELF-ALIGNED SIDEWALL SPACERS LATERALLY ADJACENT TO A TRANSISTOR GATE
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09175930
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Filing Dt:
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10/20/1998
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Title:
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CONTROLLED GAS SUPPLY LINE APPARATUS AND PROCESS FOR INFILM AND ONFILM DEFECT REDUCTION
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09176891
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Filing Dt:
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10/22/1998
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Title:
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SLURRY FOR CHEMICAL MECHANICAL POLISHING OF COPPER
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09177043
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Filing Dt:
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10/22/1998
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON GATE LAYER
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09178080
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Filing Dt:
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10/22/1998
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Title:
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METHOD OF MAKING AIR GAP ISOLATION BY MAKING A LATERAL EPI BRIDGE FOR LOW K ISOLATION ADVANCED CMOS FABRICATION
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09178225
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Filing Dt:
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10/23/1998
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Title:
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TRANSISTOR WITH AN ULTRA SHORT CHANNEL LENGTH DEFINED BY A LATERALLY DIFFUSED NITROGEN IMPLANT
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09179410
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Filing Dt:
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10/27/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING A LOW DIELECTRIC CONSTANT MATERIAL
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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09179620
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Filing Dt:
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10/27/1998
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Title:
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INSTRUCTION ALIGNMENT UNIT EMPLOYING DUAL INSTRUCTION QUEUES FOR HIGH FREQUENCY INSTRUCTION DISPATCH
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09181559
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Filing Dt:
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10/29/1998
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Title:
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PHYSICAL LAYER TRANSCEIVER ARCHITECTURE FOR A HOME NETWORK STATION CONNECTED TO A TELEPHONE LINE MEDIUM
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|
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09182524
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CALIBRATING A HOME NETWORKING STATION RECEIVING NETWORK SIGNALS ON A TELEPHONE LINE MEDIUM
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09182669
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR AUTOMATICALLY SELECTING A NETWORK PORT FOR A HOME NETWORK STATION
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09182942
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Filing Dt:
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10/29/1998
|
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Title:
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SCAN TOOL RECIPE SERVER
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Patent #:
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Issue Dt:
|
12/21/1999
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Application #:
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09182973
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Filing Dt:
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10/29/1998
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Title:
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HIGH PERFORMANCE SUPERSCALAR ALIGNMENT UNIT
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09182987
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF SELECTED HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE MEDIUM
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|
|
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Patent #:
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|
Issue Dt:
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07/25/2000
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Application #:
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09182988
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Filing Dt:
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10/30/1998
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Title:
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APPARATUS AND METHOD FOR CONTROLLING TRANSMISSION PARAMETERS OF HOME NETWORK STATIONS TRANSMITTING ON A TELEPHONE LINE MEDIUM
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|
|
|
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Patent #:
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|
Issue Dt:
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05/09/2000
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Application #:
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09183019
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Filing Dt:
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10/30/1998
|
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Title:
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SEMICONDUCTOR DEVICE HAVING FLUORINE BEARING SIDEWALL SPACERS AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09183356
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Filing Dt:
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10/30/1998
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Title:
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CRITICAL DIMENSION EQUALIZATION ACROSS THE FIELD BY SECOND BLANKET EXPOSURE AT LOW DOSE OVER BLEACHABLE RESIST
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|
|
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Patent #:
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|
Issue Dt:
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01/11/2000
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Application #:
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09183522
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Filing Dt:
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10/30/1998
|
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Title:
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FABRICATION OF CHROME/PHASE GRATING PHASE SHIFT MASK BY INTERFEROMETRIC LITHOGRAPHY
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|
|
|
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09183616
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Filing Dt:
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10/30/1998
|
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Title:
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METHOD OF FORMING SEMICONDUCTOR DEVICES USING GATE ELECTRODE LENGTH AND SPACER WIDTH FOR CONTROLLING DRIVE CURRENT STRENGTH
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|
|
|
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Patent #:
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|
Issue Dt:
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05/08/2001
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Application #:
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09184009
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Filing Dt:
|
11/02/1998
|
|
Title:
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STORAGE-ANNEALING PLATED CU INTERCONNECTS
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|
|
|
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Patent #:
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Issue Dt:
|
10/30/2001
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Application #:
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09184277
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Filing Dt:
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10/31/1998
|
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Title:
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UART SUPPORT FOR ADDRESS BIT ON SEVEN BIT FRAMES
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
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09185981
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Filing Dt:
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11/04/1998
|
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Title:
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SYSTEM FOR UNIFORMLY HEATING PHOTORESIST
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/25/2000
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Application #:
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09186053
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Filing Dt:
|
11/03/1998
|
|
Title:
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METHOD TO SELECTIVELY ELECTROPLATE CONDUCTIVE MATERIAL INTO TRENCHES
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|
|
|
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Patent #:
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|
Issue Dt:
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11/21/2000
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Application #:
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09186065
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Filing Dt:
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11/05/1998
|
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Title:
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SHALLOW JUNCTION FORMATION BY OUT-DIFFUSION FROM A DOPED DIELECTRIC LAYER THROUGH A SALICIDE LAYER
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|
|
|
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Patent #:
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|
Issue Dt:
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07/29/2003
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Application #:
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09186078
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Filing Dt:
|
11/05/1998
|
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Title:
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SHALLOW TRENCH ISOLATION FORMATION WITH ION IMPLANTATION
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/02/2001
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Application #:
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09187169
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Filing Dt:
|
11/06/1998
|
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Title:
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ELECTRON BEAN CURING OF LOW-K DIELECTRICS IN INTEGRATED CIRCUITS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09187171
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Filing Dt:
|
11/06/1998
|
|
Title:
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MULTIPLE THRESHOLD VOLTAGE TRANSISTOR IMPLEMENTED BY A DAMASCENE PROCESS
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