Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 011794/0096 | |
| Pages: | 8 |
| | Recorded: | 05/11/2001 | | |
| Conveyance: | SECURITY AGREEMENT |
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Total properties:
7
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09770345
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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Flexible network interfaces and flexible data clocking
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09770937
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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Buffer management for communication systems
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09771020
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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Computation of checksums and other functions with the aid of software instructions
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09771397
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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DIGITAL TO ANALOG CONVERTER (DAC) HAVING AN ADJUSTABLE DYNAMIC RANGE
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09772111
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Filing Dt:
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01/25/2001
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Title:
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Automatic configuration of delay parameters in a dynamic memory controller
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09772112
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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SYSTEM OF CONNECTING MULTIPLE PROCESSORS IN CASCADE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09772113
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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AUTOMATIC CONFIGURATION OF DELAY PARAMETERS FOR MEMORY CONTROLLERS OF SLAVE PROCESSORS
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Assignee
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| SUITE 2310 |
| 2010 NORTH FIRST STREET |
| SAN JOSE, CALIFORNIA 95131 |
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Correspondence name and address
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GREENE RADOVSKY MALONEY & SHARE LLP
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RUSSELL D. POLLOCK
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FOUR EMBARCADERO CENTER, SUITE 4000
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SAN FRANCISCO, CA 94111
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