Total properties:
935
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Patent #:
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Issue Dt:
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04/28/1998
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Application #:
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08600588
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Filing Dt:
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02/13/1996
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Title:
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METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08604181
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Filing Dt:
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02/21/1996
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Title:
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YIMULTANEOUS PLACEMENT AND ROUTING (SPAR) METHOD FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08607365
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Filing Dt:
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02/27/1996
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Title:
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OPTICAL PROXIMITY CORRECTION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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01/06/1998
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Application #:
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08607398
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Filing Dt:
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02/27/1996
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Title:
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PERFORMING OPTICAL PROXIMITY CORRECTION WITH THE AID OF DESIGN RULE CHECKERS
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08608609
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Filing Dt:
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02/29/1996
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Title:
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METHOD FOR METAL DELAY TESTING IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08609359
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Filing Dt:
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03/01/1996
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIP USING SIMULATED ANNEALING WITH "CHESSBOARD" AND "JIGGLE" OPTIMIZATION
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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08609397
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Filing Dt:
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03/01/1996
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Title:
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PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIP USING "CHESSBOARD" AND "JIGGLE" OPTIMIZATION
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08611325
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Filing Dt:
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03/08/1996
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Title:
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TEST SHELLS FOR PROTECTING PROPRIETARY INFORMATION IN ASIC CORES
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08613040
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Filing Dt:
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03/08/1996
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Title:
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HIGH DENSITY GATE ARRAY BASE CELL ARCHITECTURE
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Patent #:
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Issue Dt:
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06/10/1997
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Application #:
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08616070
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Filing Dt:
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03/14/1996
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Title:
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PROTECTING PROPRIETARY ASIC DESIGN INFORMATION USING BOUNDARY SCAN ON SELECTIVE INPUTS AND OUTPUTS
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08626773
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Filing Dt:
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04/02/1996
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Title:
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HARDWARE SYSTEM VERIFICATION ENVIRONMENT TOOL
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08627823
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Filing Dt:
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05/10/1996
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Title:
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METHOD FOR CREATING AND USING DESIGN SHELLS FOR INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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08630257
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Filing Dt:
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04/10/1996
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Title:
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AUTOMATED DESIGN METHOD AND SYSTEM FOR SYNTHESIZING DIGITAL MULTIPLIERS
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08636349
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Filing Dt:
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04/23/1996
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Title:
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SIMULTANEOUS PLACEMENT AND ROUTING (SPAR) METHOD FOR INTEGRATED CIRCUIT PHYSICAL DESIGN AUTOMATION SYSTEM
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Patent #:
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Issue Dt:
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04/29/1997
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Application #:
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08637026
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Filing Dt:
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04/24/1996
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Title:
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INCREASING TESTABILITY BY CLOCK TRANSFORMATION
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08641444
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Filing Dt:
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04/30/1996
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Title:
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MEMORY HAVING DIRECT STRAP CONNECTION TO POWER SUPPLY
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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08650248
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Filing Dt:
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05/22/1996
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Title:
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CLOCK SKEW INSENSITIVE SCAN CHAIN REORDERING
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08655438
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Filing Dt:
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05/29/1996
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Title:
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DOMINO SCAN ARCHITECTURE AND DOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS
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Patent #:
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Issue Dt:
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11/25/1997
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Application #:
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08661186
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Filing Dt:
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06/10/1996
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Title:
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GENERIC GATE LEVEL MODEL FOR CHARACTERIZATION OF GLITCH POWER IN LOGIC CELLS
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08661888
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Filing Dt:
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06/11/1996
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Title:
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SIMULATION BASED EXTRACTOR OF EXPECTED WAVEFORMS FOR GATE-LEVEL POWER ANAYSIS TOOL
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08661889
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Filing Dt:
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06/11/1996
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Title:
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PARAMETRIZED WAVEFORM PROCESSOR FOR GATE-LEVEL POWER ANALYSIS TOOL
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08664020
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Filing Dt:
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06/12/1996
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Title:
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GENERIC INTERACTIVE DEVICE MODEL WRAPPER
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Patent #:
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Issue Dt:
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03/24/1998
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Application #:
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08664146
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Filing Dt:
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06/14/1996
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Title:
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METHOD OF ASSEMBLING BALL BUMP GRID ARRAY SEMICONDUCTOR PACKAGES
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Patent #:
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Issue Dt:
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07/22/1997
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Application #:
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08665016
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Filing Dt:
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06/11/1996
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Title:
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METHOD OF MAKING AN INTEGRATED CIRCUIT CHIP HAVING AN ARRY OF LOGIC GATES
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08668064
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Filing Dt:
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06/19/1996
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Title:
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GATE NETLIST TO REGISTER TRANSFER LEVEL CONVERSION TOOL
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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08671651
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH MEDIAN CONTROL AND INCREASE IN RESOLUTION
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08671656
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH UNIVERSAL AFFINITY DRIVEN DISCRETE PLACEMENT OPTIMIZATION
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Patent #:
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Issue Dt:
|
07/04/2000
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Application #:
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08671659
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH SINUSOIDAL OPTIMIZATION
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08671699
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH FAST PROCEDURE FOR FINDING A LEVELIZING CUT POINT
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|
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Patent #:
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Issue Dt:
|
09/15/1998
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Application #:
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08672235
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH CELL PLACEMENT CRYSTALLIZATION
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08672333
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH MINIMIZING MAXIMAL CUT DRIVEN AFFINITY SYSTEM
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08672334
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH COARSE OVERFLOW REMOVER
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Patent #:
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Issue Dt:
|
04/06/1999
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Application #:
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08672335
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH ITERATIVE ONE DIMENSIONAL PREPLACEMENT OPTIMIZATION
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Patent #:
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Issue Dt:
|
10/26/1999
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Application #:
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08672423
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH OPTIMIZATION OF CELL NEIGHBORHOOD SYSTEM
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08672534
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Filing Dt:
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06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH DENSITY DRIVEN CAPACITY PENALTY SYSTEM
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Patent #:
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Issue Dt:
|
02/16/1999
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Application #:
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08672535
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM
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Patent #:
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Issue Dt:
|
02/09/1999
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Application #:
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08672652
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH DISPERSION-DRIVEN LEVELIZING SYSTEM
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Patent #:
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Issue Dt:
|
11/03/1998
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Application #:
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08672725
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH WIRE LENGTH DRIVEN AFFINITY SYSTEM
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Patent #:
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|
Issue Dt:
|
10/05/1999
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Application #:
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08672936
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH FUNCTIONAL SIEVE OPTIMIZATION TECHNIQUE
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|
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Patent #:
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Issue Dt:
|
02/15/2000
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Application #:
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08672937
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Filing Dt:
|
06/28/1996
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Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH OVERLAP REMOVER WITH MINIMAL NOISE
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|
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Patent #:
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|
Issue Dt:
|
09/22/1998
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Application #:
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08674605
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Filing Dt:
|
06/28/1996
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|
Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM WITH NEIGHBORHOOD SYSTEM DRIVEN OPTIMIZATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/10/1998
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Application #:
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08679949
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Filing Dt:
|
07/15/1996
|
|
Title:
|
OPTICALLY TRANSMISSIVE PREFORMED PLANAR STRUCTURES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/22/1998
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Application #:
|
08683287
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Filing Dt:
|
07/18/1996
|
|
Title:
|
INTEGRATED CIRCUIT DESIGN DECOMPOSITION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08683396
|
Filing Dt:
|
07/18/1996
|
|
Title:
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SYSTEM SIMULATION FOR TESTING INTEGRATED CIRCUIT MODELS
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|
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Patent #:
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|
Issue Dt:
|
01/12/1999
|
Application #:
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08690942
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Filing Dt:
|
08/01/1996
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|
Title:
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METHOD AND APPARATUS FOR COMPUTING MINIMUM WIRELENGTH POSITION (MWP) FOR CELL IN CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
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08694881
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Filing Dt:
|
08/09/1996
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|
Title:
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BUILT IN SHELF TEST METHOD AND APPARATUS FOR BOOTH MULTIPLIERS
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|
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Patent #:
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|
Issue Dt:
|
06/17/1997
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Application #:
|
08696141
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Filing Dt:
|
08/13/1996
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|
Title:
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METHOD AND APPARATUS FOR INTERIM IN-SITU TESTING OF AN ELECTRONIC SYSTEM WITH AN INCHOATE ASIC
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/23/1999
|
Application #:
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08719508
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Filing Dt:
|
09/25/1996
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|
Title:
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PROTECTION OF PROPRIETARY CIRCUIT DESIGNS DURING GATE LEVEL STATIC TIMING ANALYSIS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/28/1998
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Application #:
|
08720219
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Filing Dt:
|
09/26/1996
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|
Title:
|
SEMICONDUCTOR PACKAGING TECHNIQUE YIELDING INCREASED INNER LEAD COUNT FOR A GIVEN DIE-RECEIVING AREA
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/02/2000
|
Application #:
|
08720235
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Filing Dt:
|
09/26/1996
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|
Title:
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TECHNIQUE FOR EFFECTIVELY ROUTING CONDUCTION PATHS IN CIRCUIT LAYOUTS
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|
|
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Patent #:
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|
Issue Dt:
|
08/11/1998
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Application #:
|
08724025
|
Filing Dt:
|
09/17/1996
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|
Title:
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CELL PLACEMENT ALTERATION APPARATUS FOR INTEGRATED CIRCUIT CHIP PHYSI CAL DESIGN AUTOMATION SYSTEM
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/19/1998
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Application #:
|
08735249
|
Filing Dt:
|
10/29/1996
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING A PLACEMENT OF CELLS USING ENERGETIC PLACEMENT WITH ALTERNATING CONTRACTION AND EXPANSION OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08735450
|
Filing Dt:
|
10/15/1996
|
|
Title:
|
METHOD FOR LOW VELOCITY MEASUREMENT OF FLUID FLOW
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/09/1999
|
Application #:
|
08745526
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Filing Dt:
|
11/12/1996
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|
Title:
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VIRTUAL MONITOR DEBUGGING METHOD AND APPARATUS
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/25/1999
|
Application #:
|
08754142
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Filing Dt:
|
11/22/1996
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|
Title:
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COMPUTER SYSTEM AND METHOD FOR PERFORMING DESIGN AUTOMATION IN A DISTRIBUTED COMPUTING ENVIRONMENT
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/09/1999
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Application #:
|
08760641
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Filing Dt:
|
12/04/1996
|
|
Title:
|
INTEGRATED CIRCUIT LAYOUT ROUTING USING MULTIPROCESSING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/16/1999
|
Application #:
|
08766650
|
Filing Dt:
|
12/13/1996
|
|
Title:
|
COMPUTER SYSTEM AND METHOD FOR BUILDING A HARDWARE DESCRIPTION LANGUAGE REPRESENTATION OF CONTROL LOGIC FOR A COMPLEX DIGITAL SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08771004
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
METHOD FOR DETECTING BUS SHORTS IN SEMICONDUCTOR DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08772309
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
PHOTOMASK INSPECTION METHOD AND INSPECTION TAPE THEREFOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08772400
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
INTERMEDIATE TEST FILE CONVERSION AND COMPARISION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08773469
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
METHOD FOR CAPTURING ASIC I/O PIN DATA FOR TESTER COMPATIBILITY ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08774281
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Filing Dt:
|
12/20/1996
|
|
Title:
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METHOD FOR ESTIMATING ROUTABILITY AND CONGESTION IN A CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08779628
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Filing Dt:
|
01/07/1997
|
|
Title:
|
FLIP-FLOP FOR SCAN TEST CHAIN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08782585
|
Filing Dt:
|
01/13/1997
|
|
Title:
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INTEGRATED CIRCUIT DEVICE HAVING A SWITCHED ROUTING NETWORK
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|
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Patent #:
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Issue Dt:
|
11/30/1999
|
Application #:
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08789353
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Filing Dt:
|
01/27/1997
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|
Title:
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METHOD AND APPARATUS FOR EFFICIENT DESIGN AND ANALYSIS OF INTEGRATED CIRCUITS USING MULTIPLE TIME SCALES
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|
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Patent #:
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Issue Dt:
|
05/23/2000
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Application #:
|
08798598
|
Filing Dt:
|
02/11/1997
|
|
Title:
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ADVANCED MODULAR CELL PLACEMENT SYSTEM
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|
|
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Patent #:
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Issue Dt:
|
01/12/1999
|
Application #:
|
08798648
|
Filing Dt:
|
02/11/1997
|
|
Title:
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EFFICIENT MULTIPROCESSING FOR CELL PLACEMENT OF INTEGRATED CIRCUITS
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|
|
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Patent #:
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Issue Dt:
|
04/27/1999
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Application #:
|
08798652
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Filing Dt:
|
02/11/1997
|
|
Title:
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INTEGRATED CIRCUIT FLOOR PLAN OPTIMIZATION SYSTEM
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|
|
|
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Patent #:
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Issue Dt:
|
02/23/1999
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Application #:
|
08798653
|
Filing Dt:
|
02/11/1997
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|
Title:
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INTEGRATED CIRCUIT CELL PLACEMENT PARALLELIZATION WITH MINIMAL NUMBER OF CONFLICTS
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08798880
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Filing Dt:
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02/11/1997
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Title:
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PARALLEL PROCESSOR IMPLEMENTATION OF NET ROUTING
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08813340
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Filing Dt:
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03/07/1997
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Title:
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METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT USING PREDEFINED AND PREVERIFIED CORE MODULES HAVING A PLURALITY OF MATCHED CLOCK INPUTS
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08818640
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Filing Dt:
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03/14/1997
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Title:
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YIELD IMPROVEMENT TECHNIQUES THROUGH LAYOUT OPTIMIZATION
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08819856
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Filing Dt:
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03/17/1997
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Title:
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METHOD AND APPARATUS FOR SCAN CHAIN WITH REDUCED DELAY PENALTY
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Patent #:
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Issue Dt:
|
11/02/1999
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Application #:
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08829520
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Filing Dt:
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03/28/1997
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Title:
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HIGH DENSITY GATE ARRAY CELL ARCHITECTURE WITH SHARING OF WELL TAPS BETWEEN CELLS
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Patent #:
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Issue Dt:
|
02/02/1999
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Application #:
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08832487
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Filing Dt:
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04/02/1997
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Title:
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EFFICIENT FREQUENCY DOMAIN ANALYSIS OF LARGE NONLINEAR ANALOG CIRCUITS USING COMPRESSED MATRIX STORAGE
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Patent #:
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Issue Dt:
|
07/07/1998
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Application #:
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08837570
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Filing Dt:
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04/21/1997
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Title:
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LOW PROFILE VARIABLE WIDTH INPUT/OUTPUT CELLS
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08839103
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Filing Dt:
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04/23/1997
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Title:
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GATE ARRAY LAYOUT TO ACCOMMODATE MULTI ANGLE ION IMPLANTATION
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08841298
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Filing Dt:
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04/29/1997
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Title:
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SYSTEMS AND METHODS FOR DETERMINING CHARACTERISTICS OF A SINGULAR CIRCUIT
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Patent #:
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Issue Dt:
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04/20/1999
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Application #:
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08843427
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Filing Dt:
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04/15/1997
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Title:
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FAULT SIMULATOR FOR DIGITAL CIRCUITRY
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08845963
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Filing Dt:
|
04/30/1997
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Title:
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SYSTEMS AND METHODS FOR TESTING AND MANUFACTURING LARGE-SCALE TRANSISTOR -BASED NONLINEAR CIRCUITS
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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08853155
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Filing Dt:
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05/08/1997
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Title:
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COMPARING AERIAL IMAGE TO SEM OF PHOTORESIST OR SUBSTRATE PATTERN FOR MASKING PROCESS CHARACTERIZATION
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Patent #:
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Issue Dt:
|
10/12/1999
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Application #:
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08853578
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Filing Dt:
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05/09/1997
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Title:
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APPARATUS FOR DEFINING PROPERTIES IN FINITE-STATE MACHINES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08862233
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Filing Dt:
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05/23/1997
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Title:
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METHOD FOR GENERATING FORMAT-INDEPENDENT ELECTRONIC CIRCUIT REPRESENTATIONS
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08862791
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Filing Dt:
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05/23/1997
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Title:
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METHOD OF CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP COMPRISING CHAOTIC PLACEMENT AND MOVING WINDOWS
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08863798
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Filing Dt:
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05/27/1997
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Title:
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METHOD FOR USING BUILT IN SELF TEST TO CHARACTERIZE INPUT-TO-OUTPUT DELAY TIME OF EMBEDDED CORES AND OTHER INTERGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08866755
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Filing Dt:
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05/30/1997
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Title:
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LOW POWER CIRCUITS THROUGH HAZARD PULSE SUPPRESSION
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08866937
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Filing Dt:
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05/31/1997
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Title:
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SIMULATION MODEL USING OBJECT-ORIENTED PROGRAMMING
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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08867351
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Filing Dt:
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06/02/1997
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Title:
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OPTIMIZED BUILT-IN SELF-TEST METHOD AND APPARATUS FOR RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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08871212
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Filing Dt:
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06/09/1997
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Title:
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SEPARABLE CELLS HAVING WIRING CHANNELS FOR ROUTING SIGNALS BETWEEN SURROUNDING CELLS
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08877117
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Filing Dt:
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06/17/1997
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Title:
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"TEST BENCH INTERFACE GENERATOR FOR TESTER COMPATIBLE SIMULATIONS"
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Patent #:
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Issue Dt:
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06/08/1999
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Application #:
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08890174
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Filing Dt:
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07/09/1997
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Title:
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SPECIFICATION AND DESIGN OF COMPLEX DIGITAL SYSTEMS
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Patent #:
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Issue Dt:
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06/30/1998
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Application #:
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08892827
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Filing Dt:
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07/15/1997
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Title:
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METHOD OF FABRICATING A LINEARLY CONTINUOUS INTEGRATED CIRCUIT GATE ARRAY
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08901250
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Filing Dt:
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07/28/1997
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Title:
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APPARATUS AND METHOD FOR HYBRID PIN CONTROL OF BOUNDARY SCAN APPLICATIONS
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08902997
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Filing Dt:
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07/30/1997
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Title:
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METHOD AND APPARATUS FOR CALIBRATING STATIC TIMING ANALYZER TO PATH DELAY MEASUREMENTS
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08904233
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Filing Dt:
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07/31/1997
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Title:
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APPARATUS AND METHOD FOR ANALYZING PASSIVE CIRCUITS USING REDUCED ORDER MODELING OF LARGE LINEAR SUBCIRCUITS
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08904488
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Filing Dt:
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08/01/1997
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Title:
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METHOD AND APPARATUS FOR DESIGNING INTERCONNECTIONS AND PASSIVE COMPONENTS IN INTEGRATED CIRCUITS AND EQUIVALENT STRUCTURES BY EFFICIENT PARAMETER EXTRACTION
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08905540
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Filing Dt:
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08/04/1997
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Title:
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FAST TRANSIENT CIRCUIT SIMULATION OF ELECTRONIC CIRCUITS INCLUDING A CRYSTAL
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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08906945
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Filing Dt:
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08/06/1997
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Title:
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METHOD AND APPARATUS FOR CONGESTION REMOVAL
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08906946
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Filing Dt:
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08/06/1997
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Title:
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METHOD AND APPARATUS FOR CONTINUOUS COLUMN DENSITY OPTIMIZATION
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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08906947
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Filing Dt:
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08/06/1997
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Title:
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METHOD AND APPARATUS FOR DETERMINING WIRE ROUTING
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