Total properties:
935
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7
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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10664137
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Filing Dt:
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09/17/2003
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Publication #:
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Pub Dt:
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03/24/2005
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Title:
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CUSTOM CLOCK INTERCONNECTS ON A STANDARDIZED SILICON PLATFORM
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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10664636
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Filing Dt:
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09/19/2003
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Title:
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USER INTERFACE SOFTWARE DEVELOPMENT TOOL AND METHOD FOR ENHANCING THE SEQUENCING OF
INSTRUCTIONS WITHIN A SUPERSCALAR MICROPROCESSOR PIPELINE BY DISPLAYING AND MANIPULATING INSTRUCTIONS IN THE PIPELINE
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10665927
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Filing Dt:
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09/17/2003
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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METHOD OF NOISE ANALYSIS AND CORRECTION OF NOISE VIOLATIONS FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10673721
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Filing Dt:
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09/29/2003
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Publication #:
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Pub Dt:
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04/14/2005
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Title:
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FUNCTIONALITY BASED PACKAGE DESIGN FOR INTEGRATED CIRCUIT BLOCKS
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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10683369
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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04/14/2005
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Title:
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INCREMENTAL DUMMY METAL INSERTIONS
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10684119
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Filing Dt:
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10/10/2003
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Publication #:
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Pub Dt:
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04/29/2004
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Title:
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IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10688460
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Filing Dt:
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10/17/2003
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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PROCESS AND APPARATUS FOR FAST ASSIGNMENT OF OBJECTS TO A RECTANGLE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10692110
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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Novel solution for low cost, speedy probe cards
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10693075
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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COMPARISON OF TWO HIERARCHICAL NETLIST TO GENERATE CHANGE ORDERS FOR UPDATING AN INTEGRATED CIRCUIT LAYOUT
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10694208
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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PROCESS AND APPARATUS FOR PLACEMENT OF CELLS IN AN IC DURING FLOORPLAN CREATION
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10696105
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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GATE REUSE METHODOLOGY FOR DIFFUSED CELL-BASED IP BLOCKS IN PLATFORM-BASED SILICON PRODUCTS
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10697357
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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METHOD OF PARTITIONING AN INTEGRATED CIRCUIT DESIGN FOR PHYSICAL DESIGN VERIFICATION
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10699276
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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MIXED LVR AND HVR RETICLE SET DESIGN FOR THE PROCESSING OF GATE ARRAYS, EMBEDDED ARRAYS AND RAPID CHIP PRODUCTS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10700790
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Filing Dt:
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11/03/2003
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Title:
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VDD OVER AND UNDERVOLTAGE MEASUREMENT TECHNIQUES USING MONITOR CELLS
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10704922
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHOD OF GENERATING A SCHEMATIC DRIVEN LAYOUT FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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10706127
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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METHODOLOGY FOR DEBUGGING RTL SIMULATIONS OF PROCESSOR BASED SYSTEM ON CHIP
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10713492
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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FLEXIBLE DESIGN FOR MEMORY USE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10718291
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
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Title:
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METHOD OF GENERATING A PHYSICAL NETLIST FOR A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10719393
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PROCESS AND APPARATUS FOR PLACEMENT OF MEGACELLS IN ICS DESIGN
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10719787
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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METHOD AND APPARATUS FOR FINDING OPTIMAL UNIFICATION SUBSTITUTION FOR FORMULAS IN TECHNOLOGY LIBRARY
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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10724851
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Filing Dt:
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12/01/2003
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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PROCESS AND APPARATUS FOR ABSTRACTING IC DESIGN FILES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10724996
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Filing Dt:
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12/01/2003
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Publication #:
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Pub Dt:
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06/02/2005
| | | | |
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Title:
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INTEGRATED CIRCUITS, AND DESIGN AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10725638
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Filing Dt:
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12/02/2003
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Publication #:
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Pub Dt:
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08/18/2005
| | | | |
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Title:
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CUSTOMIZABLE DEVELOPMENT AND DEMONSTRATION PLATFORM FOR STRUCTURED ASICS
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10728036
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Filing Dt:
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12/03/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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METHOD OF GENERATING AN EFFICIENT STUCK-AT FAULT AND TRANSITION DELAY FAULT TRUNCATED SCAN TEST PATTERN FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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10732395
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Filing Dt:
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12/09/2003
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Publication #:
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Pub Dt:
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06/09/2005
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Title:
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CELL-BASED METHOD FOR CREATING SLOTTED METAL IN SEMICONDUCTOR DESIGNS
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10739460
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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METHOD AND APPARATUS FOR OPTIMIZING FRAGMENTATION OF BOUNDARIES FOR OPTICAL PROXIMITY CORRECTION (OPC) PURPOSES
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10740284
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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SYSTEM AND METHOD FOR MAPPING LOGICAL COMPONENTS TO PHYSICAL LOCATIONS IN AN INTEGRATED CIRCUIT DESIGN ENVIRONMENT
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10740359
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Filing Dt:
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12/18/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
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Title:
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GRADIENT METHOD OF MASK EDGE CORRECTION
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10748068
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Filing Dt:
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12/29/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
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Title:
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SYSTEM AND METHOD FOR DEBUGGING SYSTEM-ON-CHIPS USING SINGLE OR N-CYCLE STEPPING
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10757752
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Filing Dt:
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01/14/2004
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
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Title:
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OPTIMIZED BOND OUT METHOD FOR FLIP CHIP WAFERS
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10767314
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Filing Dt:
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01/28/2004
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Title:
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METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT CORE MODULES
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10768558
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
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Title:
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METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10768588
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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02/10/2005
| | | | |
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Title:
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Method and apparatus for mapping platform-based design to multiple foundry processes
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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10769510
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
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09/23/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10793055
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Filing Dt:
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03/04/2004
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Publication #:
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Pub Dt:
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09/08/2005
| | | | |
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Title:
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CONDUCTOR STACK SHIFTING
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10794225
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Filing Dt:
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03/05/2004
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Publication #:
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Pub Dt:
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09/08/2005
| | | | |
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Title:
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FEATURE TARGETED INSPECTION
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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10794683
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Filing Dt:
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03/05/2004
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Publication #:
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Pub Dt:
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09/08/2005
| | | | |
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Title:
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OPC BASED ILLUMINATION OPTIMIZATION WITH MASK ERROR CONSTRAINTS
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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10800219
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Filing Dt:
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03/12/2004
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Publication #:
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Pub Dt:
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09/15/2005
| | | | |
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Title:
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METHOD AND APPARATUS FOR VERIFYING THE POST-OPTICAL PROXIMITY CORRECTED MASK WAFER IMAGE SENSITIVITY TO RETICLE MANUFACTURING ERRORS
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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10803516
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Filing Dt:
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03/17/2004
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Publication #:
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Pub Dt:
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09/22/2005
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Title:
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METHOD AND APPARATUS FOR PERFORMING LOGICAL TRANSFORMATIONS FOR GLOBAL ROUTING
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10809939
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Filing Dt:
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03/25/2004
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Publication #:
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Pub Dt:
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11/04/2004
| | | | |
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Title:
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BROKEN SYMMETRY FOR OPTIMIZATION OF RESOURCE FABRIC IN A SEA-OF-PLATFORM ARCHITECTURE
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10810294
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Filing Dt:
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03/26/2004
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
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Title:
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MACRO CELL FOR INTEGRATED CIRCUIT PHYSICAL LAYER INTERFACE
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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10817419
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Filing Dt:
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04/01/2004
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Publication #:
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Pub Dt:
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10/06/2005
| | | | |
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Title:
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SYSTEM AND METHOD FOR IMPLEMENTING MULTIPLE INSTANTIATED CONFIGURABLE PERIPHERALS IN A CIRCUIT DESIGN
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Patent #:
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|
Issue Dt:
|
02/27/2007
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Application #:
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10819254
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Filing Dt:
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04/06/2004
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
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Title:
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GENERIC METHOD AND APPARATUS FOR IMPLEMENTING SOURCE SYNCHRONOUS INTERFACE IN PLATFORM ASIC
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|
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Patent #:
|
|
Issue Dt:
|
09/05/2006
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Application #:
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10824509
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Filing Dt:
|
04/14/2004
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Publication #:
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Pub Dt:
|
10/20/2005
| | | | |
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Title:
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PROCESS AND APPARATUS FOR CHARACTERIZING INTELLECTUAL PROPERTY FOR INTEGRATION INTO AN IC PLATFORM ENVIRONMENT
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|
|
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Patent #:
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|
Issue Dt:
|
05/15/2007
|
Application #:
|
10828408
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Filing Dt:
|
04/19/2004
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|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
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Title:
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METHOD AND COMPUTER PROGRAM FOR VERIFYING AN INCREMENTAL CHANGE TO AN INTEGRATED CIRCUIT DESIGN
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10829408
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Filing Dt:
|
04/20/2004
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|
Publication #:
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Pub Dt:
|
10/07/2004
| | | | |
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Title:
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AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR
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|
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Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10830542
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Filing Dt:
|
04/23/2004
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|
Publication #:
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Pub Dt:
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10/27/2005
| | | | |
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Title:
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PROCESS AND APPARATUS FOR PLACING CELLS IN AN IC FLOORPLAN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10830739
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Filing Dt:
|
04/25/2004
|
|
Publication #:
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Pub Dt:
|
10/27/2005
| | | | |
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Title:
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PROCESS AND APPARATUS FOR MEMORY MAPPING
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/20/2009
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Application #:
|
10832226
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Filing Dt:
|
04/26/2004
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|
Publication #:
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Pub Dt:
|
10/27/2005
| | | | |
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Title:
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GATE-LEVEL NETLIST REDUCTION FOR SIMULATING TARGET MODULES OF A DESIGN
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Patent #:
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Issue Dt:
|
09/01/2009
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Application #:
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10840534
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Filing Dt:
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05/06/2004
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
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Title:
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ASSURING CORRECT DATA ENTRY TO GENERATE SHELLS FOR A SEMICONDUCTOR PLATFORM
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|
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Patent #:
|
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Issue Dt:
|
08/01/2006
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Application #:
|
10844664
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Filing Dt:
|
05/12/2004
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|
Publication #:
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Pub Dt:
|
11/17/2005
| | | | |
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Title:
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METHOD OF OPTIMIZING RTL CODE FOR MULTIPLEX STRUCTURES
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|
|
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Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
10847691
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Filing Dt:
|
05/18/2004
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|
Publication #:
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Pub Dt:
|
11/24/2005
| | | | |
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Title:
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METHOD FOR CREATING A JTAG TAP CONTROLLER IN A SLICE FOR USE DURING CUSTOM INSTANCE CREATION TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL
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|
|
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Patent #:
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Issue Dt:
|
03/06/2007
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Application #:
|
10847692
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Filing Dt:
|
05/18/2004
|
|
Publication #:
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|
Pub Dt:
|
11/24/2005
| | | | |
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Title:
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HANDLING OF UNUSED COREWARE WITH EMBEDDED BOUNDARY SCAN CHAINS TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL DURING CUSTOM INSTANCE CREATION
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10848994
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Filing Dt:
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05/18/2004
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Publication #:
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Pub Dt:
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11/24/2005
| | | | |
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Title:
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METHOD AND SYSTEM FOR UTILIZING AN ISOFOCAL CONTOUR TO PERFORM OPTICAL AND PROCESS CORRECTIONS
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Patent #:
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Issue Dt:
|
05/09/2006
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Application #:
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10852902
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Filing Dt:
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05/25/2004
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Publication #:
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Pub Dt:
|
12/01/2005
| | | | |
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Title:
|
BUILT-IN SELF TEST TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS FOR RAPIDCHIP AND ASIC DRIVERS
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Patent #:
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Issue Dt:
|
06/20/2006
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Application #:
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10859857
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Filing Dt:
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06/02/2004
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Publication #:
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Pub Dt:
|
12/08/2005
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Title:
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METHOD OF GENERATING MULTIPLE HARDWARE DESCRIPTION LANGUAGE CONFIGURATIONS FOR A PHASE LOCKED LOOP FROM A SINGLE GENETIC MODEL FOR INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
08/12/2008
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Application #:
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10859874
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Filing Dt:
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06/02/2004
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Publication #:
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Pub Dt:
|
12/08/2005
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Title:
|
METHOD AND COMPUTER PROGRAM FOR MANAGEMENT OF SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAIN CROSSING IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
05/29/2007
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Application #:
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10862049
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Filing Dt:
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06/04/2004
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Publication #:
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Pub Dt:
|
12/08/2005
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Title:
|
TEST STRUCTURES IN UNUSED AREAS OF SEMICONDUCTOR INTEGRATED CIRCUITS AND METHODS FOR DESIGNING THE SAME
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Patent #:
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Issue Dt:
|
01/23/2007
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Application #:
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10875128
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Filing Dt:
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06/23/2004
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Publication #:
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Pub Dt:
|
01/12/2006
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Title:
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YIELD DRIVEN MEMORY PLACEMENT SYSTEM
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Patent #:
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Issue Dt:
|
02/20/2007
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Application #:
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10879768
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Filing Dt:
|
06/28/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
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Title:
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DEVICE FOR ESTIMATING CELL DELAY FROM A TABLE WITH ADDED VOLTAGE SWING
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Patent #:
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Issue Dt:
|
03/18/2008
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Application #:
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10880216
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Filing Dt:
|
06/29/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
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Title:
|
SYMMETRIC SIGNAL DISTRIBUTION THROUGH ABUTMENT CONNECTION
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Patent #:
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Issue Dt:
|
10/03/2006
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Application #:
|
10887599
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Filing Dt:
|
07/09/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
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Title:
|
PLACEMENT OF A CLOCK SIGNAL SUPPLY NETWORK DURING DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
08/19/2008
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Application #:
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10894781
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Filing Dt:
|
07/20/2004
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Publication #:
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Pub Dt:
|
01/26/2006
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Title:
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METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
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Patent #:
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Issue Dt:
|
12/15/2009
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Application #:
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10897655
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Filing Dt:
|
07/22/2004
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Publication #:
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Pub Dt:
|
02/09/2006
| | | | |
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Title:
|
SPECIAL ENGINEERING CHANGE ORDER CELLS
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Patent #:
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Issue Dt:
|
05/08/2007
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Application #:
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10900224
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Filing Dt:
|
07/27/2004
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Publication #:
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Pub Dt:
|
10/20/2005
| | | | |
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Title:
|
METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
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Patent #:
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Issue Dt:
|
06/13/2006
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Application #:
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10901841
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Filing Dt:
|
07/28/2004
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Publication #:
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Pub Dt:
|
02/02/2006
| | | | |
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Title:
|
METHOD OF AUTOMATED REPAIR OF CROSSTALK VIOLATIONS AND TIMING VIOLATIONS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
02/12/2008
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Application #:
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10902987
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
|
02/02/2006
| | | | |
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Title:
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ENGINEERING CHANGE ORDER SCENARIO MANAGER
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Patent #:
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Issue Dt:
|
02/06/2007
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Application #:
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10903836
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Filing Dt:
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07/30/2004
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Publication #:
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Pub Dt:
|
02/02/2006
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Title:
|
ACCURATE DENSITY CALCULATION WITH DENSITY VIEWS IN LAYOUT DATABASES
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Patent #:
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Issue Dt:
|
09/30/2008
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Application #:
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10909603
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Filing Dt:
|
08/02/2004
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Publication #:
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Pub Dt:
|
02/02/2006
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Title:
|
DISABLING UNUSED IO RESOURCES IN PLATFORM-BASED INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
09/12/2006
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Application #:
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10914657
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Filing Dt:
|
08/09/2004
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Publication #:
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Pub Dt:
|
02/09/2006
| | | | |
|
Title:
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METHOD OF SIZING VIA ARRAYS AND INTERCONNECTS TO REDUCE ROUTING CONGESTION IN FLIP CHIP INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
01/23/2007
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Application #:
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10914921
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Filing Dt:
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08/10/2004
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Publication #:
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Pub Dt:
|
02/16/2006
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Title:
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METHOD AND APPARATUS FOR DETECTING NETS PHYSICALLY CHANGED AND ELECTRICALLY AFFECTED BY DESIGN ECO
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Patent #:
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Issue Dt:
|
09/12/2006
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Application #:
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10924531
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Filing Dt:
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08/23/2004
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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METHOD OF FINDING CRITICAL NETS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
09/19/2006
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Application #:
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10928799
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
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Title:
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PROCESS AND APPARATUS TO ASSIGN COORDINATES TO NODES OF LOGICAL TREES WITHOUT INCREASE OF WIRE LENGTHS
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Patent #:
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Issue Dt:
|
03/13/2007
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Application #:
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10929218
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
|
03/02/2006
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Title:
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SPECIAL TIE-HIGH/LOW CELLS FOR SINGLE METAL LAYER ROUTE CHANGES
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Patent #:
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Issue Dt:
|
05/02/2006
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Application #:
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10936016
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Filing Dt:
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09/07/2004
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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SYSTEM AND METHOD FOR PROVIDING SCALABILITY IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
03/20/2007
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Application #:
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10936202
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Filing Dt:
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09/08/2004
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Publication #:
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Pub Dt:
|
04/20/2006
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Title:
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COMPACT CUSTOM LAYOUT FOR RRAM COLUMN CONTROLLER
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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10937049
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Filing Dt:
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09/09/2004
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Publication #:
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Pub Dt:
|
03/09/2006
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Title:
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ACCURATE PIN-BASED MEMORY POWER MODEL USING ARC-BASED CHARACTERIZATION
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10946274
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Filing Dt:
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09/20/2004
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Publication #:
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Pub Dt:
|
03/23/2006
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Title:
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RECONFIGURING A RAM TO A ROM USING UPPER LAYERS OF METALLIZATION
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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10946422
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
|
03/23/2006
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Title:
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METHOD FOR CALCULATING FREQUENCY-DEPENDENT IMPEDANCE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
12/12/2006
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Application #:
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10947498
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
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03/23/2006
| | | | |
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Title:
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METHOD OF EARLY PHYSICAL DESIGN VALIDATION AND IDENTIFICATION OF TEXTED METAL SHORT CIRCUITS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10947618
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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METHOD OF FLOORPLANNING AND CELL PLACEMENT FOR INTEGRATED CIRCUIT CHIP ARCHITECTURE WITH INTERNAL I/O RING
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10952194
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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METHOD AND APPARATUS FOR USE OF HIDDEN DECOUPLING CAPACITORS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10952213
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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FOUR POINT MEASUREMENT TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS RAPIDCHIP AND ASIC DEVICES
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10953480
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Filing Dt:
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09/29/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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SEMICONDUCTOR DEVICE MANUFACTURING
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10954907
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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TECHNIQUE FOR MEASUREMENT OF PROGRAMMABLE TERMINATION RESISTOR NETWORKS ON RAPIDCHIP AND ASIC DEVICES
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10956860
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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NQL - NETLIST QUERY LANGUAGE
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10956862
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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NETLIST DATABASE
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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10971911
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Filing Dt:
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10/23/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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DEBUGGING SIMULATION OF A CIRCUIT CORE USING PATTERN RECORDER, PLAYER & CHECKER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10974450
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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Generalized BIST for multiport memories
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10975570
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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Method of automating place and route corrections for an integrated circuit design from physical design validation
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10975981
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD OF OPTIMIZING CRITICAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10976518
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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PROCESS FOR DESIGNING BASE PLATFORMS FOR IC DESIGN TO PERMIT RESOURCE RECOVERY AND FLEXIBLE MACRO PLACEMENT, BASE PLATFORM FOR ICS, AND PROCESS OF CREATING ICS
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10977386
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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METHOD OF AUTOMATING PLACE AND ROUTE CORRECTIONS FOR AN INTEGRATED CIRCUIT DESIGN FROM PHYSICAL DESIGN VALIDATION
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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10984115
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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METHOD OF ASSOCIATING TIMING VIOLATIONS WITH CRITICAL STRUCTURES IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10988081
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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METHOD AND SYSTEM OF GENERIC IMPLEMENTATION OF SHARING TEST PINS WITH I/O CELLS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10988087
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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07/14/2005
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Title:
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Process and apparatus for applying apodization to maskless optical direct write lithography processes
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Issue Dt:
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04/17/2007
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Application #:
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10990237
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11/16/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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MEMORY TILING ARCHITECTURE
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10990589
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Filing Dt:
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11/17/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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MEMORY GENERATION AND PLACEMENT
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10992031
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11/18/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE BY BALANCING SHALLOW TRENCH ISOLATION STRESS AND OPTICAL PROXIMITY EFFECTS
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Patent #:
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Issue Dt:
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12/05/2006
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Application #:
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10992941
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Filing Dt:
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11/19/2004
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
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