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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:059000/0116   Pages: 21
Recorded: 02/14/2022
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 5
1
Patent #:
Issue Dt:
03/08/2022
Application #:
16220399
Filing Dt:
12/14/2018
Publication #:
Pub Dt:
06/18/2020
Title:
DIGITAL LOGIC COMPATIBLE INPUTS IN COMPOUND SEMICONDUCTOR CIRCUITS
2
Patent #:
Issue Dt:
11/21/2023
Application #:
16683472
Filing Dt:
11/14/2019
Publication #:
Pub Dt:
05/20/2021
Title:
MINIMIZING IMPEDANCE VARIATION DURING PASSIVE PHASE SHIFTING
3
Patent #:
Issue Dt:
02/15/2022
Application #:
16724857
Filing Dt:
12/23/2019
Publication #:
Pub Dt:
12/31/2020
Title:
DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS
4
Patent #:
Issue Dt:
11/14/2023
Application #:
17566779
Filing Dt:
12/31/2021
Publication #:
Pub Dt:
06/23/2022
Title:
DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS
5
Patent #:
NONE
Issue Dt:
Application #:
17586860
Filing Dt:
01/28/2022
Publication #:
Pub Dt:
07/14/2022
Title:
DIGITAL LOGIC COMPATIBLE INPUTS IN COMPOUND SEMICONDUCTOR CIRCUITS
Assignor
1
Exec Dt:
03/29/2019
Newly Merged Entity Data
1
Exec Dt:
03/29/2019
Newly Merged Entity's New Name
1
1001 MURPHY RANCH ROAD
MILPITAS, CALIFORNIA 95035
Correspondence name and address
CHAO WEI CHUNG
400 GARDEN CITY PLAZA
SUITE 300
GARDEN CITY, NY 11530

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