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Reel/Frame:065284/0123   Pages: 18
Recorded: 10/18/2023
Attorney Dkt #:058438-14-0289
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 173
Page 2 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
07/08/2003
Application #:
10163661
Filing Dt:
06/04/2002
Title:
METHOD AND SYSTEM FOR FABRICATING A BIPOLAR TRANSISTOR AND RELATED STRUCTURE
2
Patent #:
Issue Dt:
06/13/2006
Application #:
10190297
Filing Dt:
07/05/2002
Title:
FABRICATION OF HIGH-DENSITY CAPACITORS FOR MIXED SIGNAL/RF CIRCUITS
3
Patent #:
Issue Dt:
01/04/2005
Application #:
10190459
Filing Dt:
07/05/2002
Title:
DAMASCENE TRENCH CAPACITOR FOR MIXED-SIGNAL/RF IC APPLICATIONS
4
Patent #:
Issue Dt:
07/22/2003
Application #:
10193056
Filing Dt:
07/10/2002
Publication #:
Pub Dt:
12/05/2002
Title:
METHOD FOR REDUCING CONTAMINATION PRIOR TO EPITAXIAL GROWTH AND RELATED STRUCTURE
5
Patent #:
Issue Dt:
08/10/2004
Application #:
10193638
Filing Dt:
07/10/2002
Publication #:
Pub Dt:
12/26/2002
Title:
A BIPOLAR TRANSISTOR WITH REDUCED EMITTER TO BASE CAPACITANCE
6
Patent #:
Issue Dt:
08/09/2005
Application #:
10199750
Filing Dt:
07/18/2002
Title:
ELECTROSTATIC DISCHARGE CLAMP
7
Patent #:
Issue Dt:
08/31/2004
Application #:
10218527
Filing Dt:
08/13/2002
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR AND RELATED STRUCTURE
8
Patent #:
Issue Dt:
12/14/2004
Application #:
10262714
Filing Dt:
10/02/2002
Title:
METHOD FOR FORMING CMOS TRANSISTOR SPACERS IN A BICMOS PROCESS AND RELATED STRUCTURE
9
Patent #:
Issue Dt:
07/20/2004
Application #:
10265334
Filing Dt:
10/04/2002
Title:
AN HBT HAVING A CONTROLLED EMITTER WINDOW OPENING
10
Patent #:
Issue Dt:
07/06/2004
Application #:
10272888
Filing Dt:
10/16/2002
Title:
TEMPERATURE INSENSITIVE RESISTOR IN AN IC CHIP
11
Patent #:
Issue Dt:
09/07/2004
Application #:
10289821
Filing Dt:
11/06/2002
Title:
INTERFACIAL OXIDE IN A TRANSISTOR
12
Patent #:
Issue Dt:
05/17/2005
Application #:
10290955
Filing Dt:
11/07/2002
Title:
REDUCING EXTRINSIC BASE RESISTANCE AND IMPROVING MANUFACTURABILITY IN AN NPN TRANSISTOR
13
Patent #:
Issue Dt:
03/15/2005
Application #:
10290975
Filing Dt:
11/07/2002
Publication #:
Pub Dt:
05/13/2004
Title:
HIGH GAIN BIPOLAR TRANSISTOR
14
Patent #:
Issue Dt:
12/14/2004
Application #:
10290976
Filing Dt:
11/07/2002
Title:
METHOD FOR REDUCING EXTRINSIC BASE RESISTANCE AND IMPROVING MANUFACTURABILITY IN AN NPN TRANSISTOR
15
Patent #:
Issue Dt:
04/06/2004
Application #:
10291116
Filing Dt:
11/08/2002
Title:
TRANSPARENT PHASE SHIFT MASK FOR FABRICATION OF SMALL FEATURE SIZES
16
Patent #:
Issue Dt:
01/06/2004
Application #:
10301885
Filing Dt:
11/21/2002
Title:
METHOD FOR ELIMINATING COLLECTOR-BASE BAND GAP IN AN HBT
17
Patent #:
Issue Dt:
01/20/2004
Application #:
10302308
Filing Dt:
11/22/2002
Title:
METHOD FOR FABRICATING A SELECTIVE EPITAXIAL HBT EMITTER
18
Patent #:
Issue Dt:
04/06/2004
Application #:
10308661
Filing Dt:
12/02/2002
Title:
METHOD FOR FABRICATING A SELF-ALIGNED EMITTER IN A BIPOLAR TRANSISTOR
19
Patent #:
Issue Dt:
08/24/2004
Application #:
10313508
Filing Dt:
12/06/2002
Title:
A METASTABLE BASE IN A HIGH-PERFORMANCE HBT
20
Patent #:
Issue Dt:
12/06/2005
Application #:
10313583
Filing Dt:
12/07/2002
Title:
Efficiently fabricated bipolar transistor
21
Patent #:
Issue Dt:
12/14/2004
Application #:
10313700
Filing Dt:
12/07/2002
Title:
SYSTEM FOR FABRICATING A BIPOLAR TRANSISTOR
22
Patent #:
Issue Dt:
04/27/2004
Application #:
10320334
Filing Dt:
12/16/2002
Title:
PROBE CARD AND PROBE NEEDLE FOR HIGH FREQUENCY TESTING
23
Patent #:
Issue Dt:
11/15/2005
Application #:
10321877
Filing Dt:
12/17/2002
Title:
POLYCRYSTALLINE SILICON EMITTER HAVING AN ACCURATELY CONTROLLED CRITICAL DIMENSION
24
Patent #:
Issue Dt:
06/08/2004
Application #:
10324341
Filing Dt:
12/19/2002
Publication #:
Pub Dt:
06/24/2004
Title:
BIFET VOLTAGE CONTROLLED OSCILLATOR
25
Patent #:
Issue Dt:
07/19/2005
Application #:
10356447
Filing Dt:
02/01/2003
Publication #:
Pub Dt:
08/05/2004
Title:
METHOD FOR PATTERNING DENSELY PACKED METAL SEGMENTS IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
26
Patent #:
Issue Dt:
11/16/2004
Application #:
10364550
Filing Dt:
02/10/2003
Title:
METHOD FOR CONTROLLING CRITICAL DIMENSION IN AN HBT EMITTER
27
Patent #:
Issue Dt:
07/20/2004
Application #:
10369027
Filing Dt:
02/19/2003
Title:
METHOD FOR CONTROLLING AN EMITTER WINDOW OPENING IN AN HBT AND RELATED STRUCTURE
28
Patent #:
Issue Dt:
03/21/2006
Application #:
10371307
Filing Dt:
02/20/2003
Title:
METHOD FOR FORMING DEEP TRENCH ISOLATION AND RELATED STRUCTURE
29
Patent #:
Issue Dt:
08/03/2004
Application #:
10371416
Filing Dt:
02/20/2003
Title:
METHOD FOR HARD MASK REMOVAL FOR DEEP TRENCH ISOLATION AND RELATED STRUCTURE
30
Patent #:
Issue Dt:
09/28/2004
Application #:
10371706
Filing Dt:
02/21/2003
Title:
METHOD FOR FABRICATING A BIPOLAR TRANSISTOR IN A BICMOS PROCESS AND RELATED STRUCTURE
31
Patent #:
Issue Dt:
11/02/2004
Application #:
10375727
Filing Dt:
02/26/2003
Title:
METHOD FOR IMPROVED ALIGNMENT TOLERANCE IN A BIPOLAR TRANSISTOR
32
Patent #:
Issue Dt:
01/20/2004
Application #:
10410937
Filing Dt:
04/09/2003
Title:
HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
33
Patent #:
Issue Dt:
08/23/2005
Application #:
10431073
Filing Dt:
05/06/2003
Title:
TRANSPARENT PHASE SHIFT MASK FOR FABRICATION OF SMALL FEATURE SIZES
34
Patent #:
Issue Dt:
06/20/2006
Application #:
10434961
Filing Dt:
05/09/2003
Title:
TECHNIQUE FOR REDUCING CONTAMINANTS IN FABRICATION OF SEMICONDUCTOR WAFERS
35
Patent #:
Issue Dt:
03/01/2005
Application #:
10437530
Filing Dt:
05/13/2003
Publication #:
Pub Dt:
11/18/2004
Title:
METHOD FOR FABRICATION OF SIGE LAYER HAVING SMALL POLY GRAINS AND RELATED STRUCTURE
36
Patent #:
Issue Dt:
09/28/2004
Application #:
10437723
Filing Dt:
05/13/2003
Title:
METHOD FOR FABRICATION OF EMITTER OF A TRANSISTOR AND RELATED STRUCTURE
37
Patent #:
Issue Dt:
12/27/2005
Application #:
10442449
Filing Dt:
05/21/2003
Publication #:
Pub Dt:
07/15/2004
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY AND RELATED STRUCTURE
38
Patent #:
Issue Dt:
10/26/2004
Application #:
10442489
Filing Dt:
05/21/2003
Publication #:
Pub Dt:
07/22/2004
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITH PLANARIZING LAYER AND RELATED STRUCTURE
39
Patent #:
Issue Dt:
05/17/2005
Application #:
10442492
Filing Dt:
05/21/2003
Publication #:
Pub Dt:
07/01/2004
Title:
SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS AND METHOD FOR FABRICATING SAME
40
Patent #:
Issue Dt:
03/15/2005
Application #:
10442501
Filing Dt:
05/21/2003
Title:
SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS AND METHOD FOR FABRICATING SAME
41
Patent #:
Issue Dt:
08/17/2004
Application #:
10447397
Filing Dt:
05/28/2003
Title:
HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
42
Patent #:
Issue Dt:
05/09/2006
Application #:
10712067
Filing Dt:
11/13/2003
Title:
METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
43
Patent #:
Issue Dt:
06/20/2006
Application #:
10758494
Filing Dt:
01/15/2004
Title:
CIRCUIT FOR DETECTING ARCING IN AN ETCH TOOL DURING WAFER PROCESSING
44
Patent #:
Issue Dt:
12/26/2006
Application #:
10826507
Filing Dt:
04/16/2004
Title:
COMPOSITE GROUND SHIELD FOR PASSIVE COMPONENTS IN A SEMICONDUCTOR DIE
45
Patent #:
Issue Dt:
02/07/2006
Application #:
10842943
Filing Dt:
05/10/2004
Title:
DEEP TRENCH ISOLATION REGION WITH REDUCED-SIZE CAVITIES IN OVERLYING FIELD OXIDE
46
Patent #:
Issue Dt:
07/18/2006
Application #:
10843190
Filing Dt:
05/10/2004
Title:
COMPOSITE SERIES RESISTOR HAVING REDUCED TEMPERATURE SENSITIVITY IN AN IC CHIP
47
Patent #:
Issue Dt:
07/18/2006
Application #:
10850187
Filing Dt:
05/19/2004
Title:
METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
48
Patent #:
Issue Dt:
04/25/2006
Application #:
10865153
Filing Dt:
06/09/2004
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS
49
Patent #:
Issue Dt:
06/20/2006
Application #:
10865634
Filing Dt:
06/10/2004
Title:
NPN TRANSISTOR HAVING REDUCED EXTRINISIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
50
Patent #:
Issue Dt:
05/09/2006
Application #:
10870900
Filing Dt:
06/17/2004
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR
51
Patent #:
Issue Dt:
07/18/2006
Application #:
10888406
Filing Dt:
07/10/2004
Title:
TRANSISTOR EMITTER HAVING ALTERNATING UNDOPED AND DOPED LAYERS
52
Patent #:
Issue Dt:
08/09/2011
Application #:
10892015
Filing Dt:
07/14/2004
Title:
BIPOLAR TRANSISTOR FABRICATED IN A BICMOS PROCESS
53
Patent #:
Issue Dt:
11/07/2006
Application #:
10915797
Filing Dt:
08/11/2004
Title:
SIGE LAYER HAVING SMALL POLY GRAINS
54
Patent #:
Issue Dt:
01/31/2006
Application #:
10936927
Filing Dt:
09/09/2004
Title:
CMOS TRANSISTOR SPACERS FORMED IN A BICMOS PROCESS
55
Patent #:
Issue Dt:
10/16/2007
Application #:
10952256
Filing Dt:
09/28/2004
Title:
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS
56
Patent #:
Issue Dt:
03/04/2008
Application #:
10970645
Filing Dt:
10/20/2004
Title:
METHOD FOR OPTO-ELECTRONIC INTEGRATION ON A SOI SUBSTRATE AND RELATED STRUCTURE
57
Patent #:
Issue Dt:
09/19/2006
Application #:
10995762
Filing Dt:
11/22/2004
Title:
SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL
58
Patent #:
Issue Dt:
06/20/2006
Application #:
10995769
Filing Dt:
11/22/2004
Title:
SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
59
Patent #:
Issue Dt:
11/20/2007
Application #:
10997534
Filing Dt:
11/23/2004
Title:
METHOD AND STRUCTURE FOR INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
60
Patent #:
Issue Dt:
09/11/2007
Application #:
10997638
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
METHOD FOR FABRICATING A MIM CAPACITOR HAVING INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
61
Patent #:
Issue Dt:
06/26/2007
Application #:
11003572
Filing Dt:
12/02/2004
Title:
NPN TRANSISTOR HAVING REDUCED EXTRINSIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
62
Patent #:
Issue Dt:
03/04/2008
Application #:
11018164
Filing Dt:
12/20/2004
Title:
SOI SUBSTRATE FOR INTEGRATION OF OPTO-ELECTRONICS WITH SIGE BICMOS
63
Patent #:
Issue Dt:
06/02/2009
Application #:
11084391
Filing Dt:
03/17/2005
Title:
INTEGRATION OF SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE
64
Patent #:
Issue Dt:
02/26/2008
Application #:
11086168
Filing Dt:
03/21/2005
Title:
METHOD FOR EFFECTIVE BICMOS PROCESS INTEGRATION
65
Patent #:
Issue Dt:
05/04/2010
Application #:
11112194
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/01/2009
Title:
DENSELY PACKED METAL SEGMENTS PATTERNED IN A SEMICONDUCTOR DIE
66
Patent #:
Issue Dt:
05/22/2007
Application #:
11121360
Filing Dt:
05/03/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD FOR FABRICATING A MIM CAPACITOR HIGH-K DIELECTRIC FOR INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
67
Patent #:
Issue Dt:
11/06/2007
Application #:
11146537
Filing Dt:
06/06/2005
Title:
SELECTIVE AND NON-SELECTIVE EPITAXY FOR BASE INTEGRATION IN A BICMOS PROCESS AND RELATED STRUCTURE
68
Patent #:
Issue Dt:
11/06/2007
Application #:
11175720
Filing Dt:
07/06/2005
Title:
FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
69
Patent #:
Issue Dt:
09/15/2015
Application #:
11198425
Filing Dt:
08/05/2005
Title:
Deep N wells in triple well structures
70
Patent #:
Issue Dt:
03/03/2009
Application #:
11525457
Filing Dt:
09/21/2006
Title:
INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
71
Patent #:
Issue Dt:
07/03/2012
Application #:
11542088
Filing Dt:
10/02/2006
Title:
STRUCTURE FOR ENCAPSULATING MICROELECTRONIC DEVICES
72
Patent #:
Issue Dt:
04/27/2010
Application #:
11641500
Filing Dt:
12/18/2006
Title:
METHOD FOR FABRICATING A FRONTSIDE THROUGH-WAFER VIA IN A PROCESSED WAFER AND RELATED STRUCTURE
73
Patent #:
Issue Dt:
09/15/2009
Application #:
11641925
Filing Dt:
12/18/2006
Title:
METHOD FOR FABRICATING A TOP CONDUCTIVE LAYER IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
Assignor
1
Exec Dt:
09/29/2023
Assignee
1
4321 JAMBOREE ROAD
NEWPORT BEACH, CALIFORNIA 92660
Correspondence name and address
MORGAN LEWIS & BOCKIUS LLP
1111 PENNSYLVANIA AVE., N.W.
WASHINGTON, DC 20004

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