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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10163661
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Filing Dt:
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06/04/2002
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Title:
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METHOD AND SYSTEM FOR FABRICATING A BIPOLAR TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10190297
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Filing Dt:
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07/05/2002
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Title:
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FABRICATION OF HIGH-DENSITY CAPACITORS FOR MIXED SIGNAL/RF CIRCUITS
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10190459
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Filing Dt:
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07/05/2002
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Title:
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DAMASCENE TRENCH CAPACITOR FOR MIXED-SIGNAL/RF IC APPLICATIONS
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10193056
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Filing Dt:
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07/10/2002
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR REDUCING CONTAMINATION PRIOR TO EPITAXIAL GROWTH AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10193638
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Filing Dt:
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07/10/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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A BIPOLAR TRANSISTOR WITH REDUCED EMITTER TO BASE CAPACITANCE
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10199750
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Filing Dt:
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07/18/2002
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Title:
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ELECTROSTATIC DISCHARGE CLAMP
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10218527
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Filing Dt:
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08/13/2002
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10262714
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Filing Dt:
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10/02/2002
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Title:
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METHOD FOR FORMING CMOS TRANSISTOR SPACERS IN A BICMOS PROCESS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10265334
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Filing Dt:
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10/04/2002
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Title:
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AN HBT HAVING A CONTROLLED EMITTER WINDOW OPENING
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10272888
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Filing Dt:
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10/16/2002
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Title:
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TEMPERATURE INSENSITIVE RESISTOR IN AN IC CHIP
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10289821
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Filing Dt:
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11/06/2002
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Title:
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INTERFACIAL OXIDE IN A TRANSISTOR
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10290955
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Filing Dt:
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11/07/2002
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Title:
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REDUCING EXTRINSIC BASE RESISTANCE AND IMPROVING MANUFACTURABILITY IN AN NPN TRANSISTOR
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10290975
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Filing Dt:
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11/07/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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HIGH GAIN BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10290976
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Filing Dt:
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11/07/2002
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Title:
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METHOD FOR REDUCING EXTRINSIC BASE RESISTANCE AND IMPROVING MANUFACTURABILITY IN AN NPN TRANSISTOR
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10291116
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Filing Dt:
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11/08/2002
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Title:
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TRANSPARENT PHASE SHIFT MASK FOR FABRICATION OF SMALL FEATURE SIZES
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10301885
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Filing Dt:
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11/21/2002
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Title:
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METHOD FOR ELIMINATING COLLECTOR-BASE BAND GAP IN AN HBT
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10302308
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Filing Dt:
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11/22/2002
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Title:
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METHOD FOR FABRICATING A SELECTIVE EPITAXIAL HBT EMITTER
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10308661
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Filing Dt:
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12/02/2002
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED EMITTER IN A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10313508
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Filing Dt:
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12/06/2002
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Title:
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A METASTABLE BASE IN A HIGH-PERFORMANCE HBT
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10313583
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Filing Dt:
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12/07/2002
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Title:
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Efficiently fabricated bipolar transistor
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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10313700
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Filing Dt:
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12/07/2002
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Title:
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SYSTEM FOR FABRICATING A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10320334
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Filing Dt:
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12/16/2002
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Title:
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PROBE CARD AND PROBE NEEDLE FOR HIGH FREQUENCY TESTING
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10321877
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Filing Dt:
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12/17/2002
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Title:
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POLYCRYSTALLINE SILICON EMITTER HAVING AN ACCURATELY CONTROLLED CRITICAL DIMENSION
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10324341
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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BIFET VOLTAGE CONTROLLED OSCILLATOR
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10356447
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Filing Dt:
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02/01/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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METHOD FOR PATTERNING DENSELY PACKED METAL SEGMENTS IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10364550
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Filing Dt:
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02/10/2003
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Title:
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METHOD FOR CONTROLLING CRITICAL DIMENSION IN AN HBT EMITTER
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10369027
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Filing Dt:
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02/19/2003
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Title:
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METHOD FOR CONTROLLING AN EMITTER WINDOW OPENING IN AN HBT AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10371307
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Filing Dt:
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02/20/2003
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Title:
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METHOD FOR FORMING DEEP TRENCH ISOLATION AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10371416
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Filing Dt:
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02/20/2003
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Title:
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METHOD FOR HARD MASK REMOVAL FOR DEEP TRENCH ISOLATION AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10371706
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Filing Dt:
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02/21/2003
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Title:
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METHOD FOR FABRICATING A BIPOLAR TRANSISTOR IN A BICMOS PROCESS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10375727
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Filing Dt:
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02/26/2003
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Title:
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METHOD FOR IMPROVED ALIGNMENT TOLERANCE IN A BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10410937
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Filing Dt:
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04/09/2003
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Title:
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HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10431073
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Filing Dt:
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05/06/2003
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Title:
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TRANSPARENT PHASE SHIFT MASK FOR FABRICATION OF SMALL FEATURE SIZES
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10434961
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Filing Dt:
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05/09/2003
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Title:
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TECHNIQUE FOR REDUCING CONTAMINANTS IN FABRICATION OF SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10437530
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Filing Dt:
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05/13/2003
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Publication #:
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Pub Dt:
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11/18/2004
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Title:
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METHOD FOR FABRICATION OF SIGE LAYER HAVING SMALL POLY GRAINS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10437723
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Filing Dt:
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05/13/2003
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Title:
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METHOD FOR FABRICATION OF EMITTER OF A TRANSISTOR AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10442449
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10442489
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITH PLANARIZING LAYER AND RELATED STRUCTURE
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Issue Dt:
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05/17/2005
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10442492
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS AND METHOD FOR FABRICATING SAME
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Issue Dt:
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03/15/2005
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Application #:
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10442501
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Filing Dt:
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05/21/2003
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS AND METHOD FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10447397
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Filing Dt:
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05/28/2003
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Title:
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HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
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Issue Dt:
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05/09/2006
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Application #:
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10712067
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11/13/2003
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Title:
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METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
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06/20/2006
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10758494
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01/15/2004
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Title:
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CIRCUIT FOR DETECTING ARCING IN AN ETCH TOOL DURING WAFER PROCESSING
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Patent #:
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12/26/2006
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10826507
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04/16/2004
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Title:
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COMPOSITE GROUND SHIELD FOR PASSIVE COMPONENTS IN A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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02/07/2006
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10842943
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05/10/2004
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Title:
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DEEP TRENCH ISOLATION REGION WITH REDUCED-SIZE CAVITIES IN OVERLYING FIELD OXIDE
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07/18/2006
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10843190
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05/10/2004
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Title:
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COMPOSITE SERIES RESISTOR HAVING REDUCED TEMPERATURE SENSITIVITY IN AN IC CHIP
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07/18/2006
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10850187
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Filing Dt:
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05/19/2004
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Title:
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METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
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04/25/2006
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Application #:
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10865153
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Filing Dt:
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06/09/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS
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06/20/2006
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10865634
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06/10/2004
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NPN TRANSISTOR HAVING REDUCED EXTRINISIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
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05/09/2006
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10870900
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06/17/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR
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07/18/2006
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10888406
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07/10/2004
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Title:
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TRANSISTOR EMITTER HAVING ALTERNATING UNDOPED AND DOPED LAYERS
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08/09/2011
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10892015
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07/14/2004
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Title:
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BIPOLAR TRANSISTOR FABRICATED IN A BICMOS PROCESS
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11/07/2006
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10915797
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08/11/2004
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Title:
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SIGE LAYER HAVING SMALL POLY GRAINS
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01/31/2006
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10936927
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09/09/2004
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Title:
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CMOS TRANSISTOR SPACERS FORMED IN A BICMOS PROCESS
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10/16/2007
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10952256
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09/28/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS
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03/04/2008
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10970645
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10/20/2004
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Title:
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METHOD FOR OPTO-ELECTRONIC INTEGRATION ON A SOI SUBSTRATE AND RELATED STRUCTURE
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09/19/2006
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10995762
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11/22/2004
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Title:
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SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL
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06/20/2006
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10995769
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11/22/2004
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
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11/20/2007
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10997534
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11/23/2004
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METHOD AND STRUCTURE FOR INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
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09/11/2007
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10997638
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11/23/2004
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05/25/2006
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Title:
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METHOD FOR FABRICATING A MIM CAPACITOR HAVING INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
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06/26/2007
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11003572
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12/02/2004
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NPN TRANSISTOR HAVING REDUCED EXTRINSIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
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03/04/2008
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11018164
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12/20/2004
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SOI SUBSTRATE FOR INTEGRATION OF OPTO-ELECTRONICS WITH SIGE BICMOS
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06/02/2009
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11084391
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03/17/2005
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INTEGRATION OF SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE
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02/26/2008
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11086168
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03/21/2005
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METHOD FOR EFFECTIVE BICMOS PROCESS INTEGRATION
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05/04/2010
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11112194
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04/22/2005
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10/01/2009
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Title:
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DENSELY PACKED METAL SEGMENTS PATTERNED IN A SEMICONDUCTOR DIE
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05/22/2007
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11121360
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05/03/2005
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11/09/2006
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METHOD FOR FABRICATING A MIM CAPACITOR HIGH-K DIELECTRIC FOR INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
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11/06/2007
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11146537
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06/06/2005
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Title:
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SELECTIVE AND NON-SELECTIVE EPITAXY FOR BASE INTEGRATION IN A BICMOS PROCESS AND RELATED STRUCTURE
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11/06/2007
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11175720
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07/06/2005
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Title:
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FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
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09/15/2015
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11198425
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08/05/2005
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Deep N wells in triple well structures
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03/03/2009
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11525457
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09/21/2006
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INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
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07/03/2012
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Filing Dt:
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10/02/2006
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Title:
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STRUCTURE FOR ENCAPSULATING MICROELECTRONIC DEVICES
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Patent #:
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Issue Dt:
|
04/27/2010
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Application #:
|
11641500
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Filing Dt:
|
12/18/2006
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Title:
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METHOD FOR FABRICATING A FRONTSIDE THROUGH-WAFER VIA IN A PROCESSED WAFER AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
|
09/15/2009
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Application #:
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11641925
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Filing Dt:
|
12/18/2006
|
Title:
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METHOD FOR FABRICATING A TOP CONDUCTIVE LAYER IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
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