|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10380538
|
Filing Dt:
|
08/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR TRANSMISSION-LINE TERMINATION BY SIGNAL CANCELLATION, AND APPLICATIONS THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10386148
|
Filing Dt:
|
03/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
TEMPERATURE-DEPENDENT REFRESH CYCLE FOR DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10393696
|
Filing Dt:
|
03/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
| | | | |
|
Title:
|
DRAM CELL CONSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
10396902
|
Filing Dt:
|
03/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
INTEGRATED CIRCUIT CHIP HAVING ANTI-MOISTURE-ABSORPTION FILM AT EDGE THEREOF AND METHOD OF FORMING ANTI-MOISTURE-ABSORPTION FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10410375
|
Filing Dt:
|
04/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10423423
|
Filing Dt:
|
04/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
SEMICONDUCTOR CIRCUIT CONSTRUCTIONS,CAPACITOR CONSTRUCTIONS, AND METHODS OF FORMING SEMICONDUCTOR CIRCUIT CONSTRUCTIONS AND CAPACITOR CONSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10426988
|
Filing Dt:
|
04/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
|
Title:
|
ETCHING METHOD IN A SEMICONDUCTOR PROCESSING AND ETCHING SYSTEM FOR PERFORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10430378
|
Filing Dt:
|
05/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10442898
|
Filing Dt:
|
05/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
CMOS IMAGE SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10444600
|
Filing Dt:
|
05/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ACCELERATING RETRIEVAL OF DATA FROM A MEMORY SYSTEM WITH CACHE BY REDUCING LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
10448763
|
Filing Dt:
|
05/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR EXTERNAL CONTROL OF ESD PROTECTION IN ELECTRONIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10449640
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
RECESSED GATE ELECTRODE MOS TRANSISTORS HAVING A SUBSTANTIALLY UNIFORM CHANNEL LENGTH ACROSS A WIDTH OF THE RECESSED GATE ELECTRODE AND METHODS OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10451544
|
Filing Dt:
|
06/24/2003
|
|
Title:
|
ADAPTER FOR MOUNTING A FACEPLATE OF A FIRST STYLE ON TO AN ELECTRICAL OUTLET CAVITY OF A SECOND STYLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10464508
|
Filing Dt:
|
06/19/2003
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE COMPRISING SILICON-RICH TASIN METAL GATE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10473980
|
Filing Dt:
|
10/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10490729
|
Filing Dt:
|
03/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
SENSOR SIGNAL OUTPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
10492085
|
Filing Dt:
|
11/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
OUTLET WITH ANALOG SIGNAL ADAPTER, A METHOD FOR USE THEREOF AND A NETWORK USING SAID OUTLET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
10492411
|
Filing Dt:
|
04/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
PRIVATE TELEPHONE NETWORK CONNECTED TO MORE THAN ONE PUBLIC NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10531074
|
Filing Dt:
|
04/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
|
Title:
|
SENSOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10608719
|
Filing Dt:
|
06/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
|
Title:
|
SYNCHRONOUS SRAM-COMPATIBLE MEMORY AND METHOD OF DRIVING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10614052
|
Filing Dt:
|
07/08/2003
|
|
Title:
|
NARROW FINS BY OXIDATION IN DOUBLE-GATE FINFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
10614558
|
Filing Dt:
|
07/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10617683
|
Filing Dt:
|
07/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10622672
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
RESET SCHEME FOR I/O PADS IN A SOURCE SYNCHRONOUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10623389
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2004
| | | | |
|
Title:
|
PINNED PHOTODIODE FOR A CMOS IMAGE SENSOR AND FABRICATING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10629989
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR SYNCHRONIZING MULTIPLE SYNCHRONIZER CONTROLLERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10630159
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
PROGRAMMABLE CLOCK SYNCHRONIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10630182
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
A CONTROLLER ARRANGEMENT FOR SYNCHRONIZER DATA TRANSFER BETWEEN A CORE CLOCK DOMAIN AND BUS CLOCK DOMAIN EACH HAVING ITS OWN INDIVIDUAL SYNCHRONIZING CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10630297
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR MAINTAINING A STABLE SYNCHRONIZATION STATE IN A PROGRAMMABLE CLOCK SYNCHRONIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10630298
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
PHASE DETECTOR FOR A PROGRAMMABLE CLOCK SYNCHRONIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10630317
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/11/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR COMPENSATING FOR SKEW BETWEEN A FIRST CLOCK SIGNAL AND A SECOND CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10630994
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
PERSISTENT VOLATILE MEMORY FAULT TRACKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10632885
|
Filing Dt:
|
08/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
DISTRIBUTED MULTIPLEXING CIRCUIT WITH BUILT-IN REPEATER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
10647664
|
Filing Dt:
|
08/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
START UP CIRCUIT FOR DELAY LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10651360
|
Filing Dt:
|
08/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
METHOD AND DEVICE FOR CIRCUIT CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10653234
|
Filing Dt:
|
09/03/2003
|
|
Title:
|
NARROW BODY RAISED SOURCE/DRAIN METAL GATE MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10653578
|
Filing Dt:
|
09/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
HIGH VOLTAGE SUPPLY CIRCUIT AND A METHOD OF SUPPLYING HIGH VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10653760
|
Filing Dt:
|
09/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD TO MITIGATE VOLTAGE FLUCTUATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10672816
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
Semiconductor Processing Methods
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10673597
|
Filing Dt:
|
09/29/2003
|
|
Title:
|
SLURRY-LESS POLISHING FOR REMOVAL OF EXCESS INTERCONNECT MATERIAL DURING FABRICATION OF A SILICON INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10694761
|
Filing Dt:
|
10/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
ERROR CORRECTION SCHEME FOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10700919
|
Filing Dt:
|
11/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR GENERATING A CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10724576
|
Filing Dt:
|
12/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
|
Title:
|
BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10730002
|
Filing Dt:
|
12/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
CLOCK LOGIC DOMINO CIRCUITS FOR HIGH-SPEED AND ENERGY EFFICIENT MICROPROCESSOR PIPELINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10731764
|
Filing Dt:
|
12/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
DEMONSTRATION CONTROL ADJUNCT DEVICE FOR PRINTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
10732687
|
Filing Dt:
|
12/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
OUTPUT BUFFER SLEW RATE CONTROL USING CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10739620
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2004
| | | | |
|
Title:
|
METHOD OF FABRICATING DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10744174
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR SIGNAL SYNCHRONIZATION BASED ON PLURAL CLOCK SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
10747307
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
CMOS IMAGE SENSOR HAVING IMPURITY DIFFUSION REGION SEPARATED FROM ISOLATION REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10747405
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
COLOR FILTER OF IMAGE SENSOR, IMAGE SENSOR, AND METHOD FOR MANUFACTURING THE IMAGE SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10749892
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH MODIFIED GLOBAL INPUT/OUTPUT SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
10768911
|
Filing Dt:
|
01/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DESIGN AND ROUTING IN TRANSPARENT OPTICAL NETWORKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10773247
|
Filing Dt:
|
02/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
NETWORKS FOR TELEPHONY AND DATA COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10777174
|
Filing Dt:
|
02/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
DRIVER CIRCUIT CONNECTED TO PULSE SHAPING CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10786401
|
Filing Dt:
|
02/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
TECHNIQUE FOR FORMING RECESSED SIDEWALL SPACERS FOR A POLYSILICON LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10793769
|
Filing Dt:
|
03/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
|
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLEGENT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10795986
|
Filing Dt:
|
03/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2004
| | | | |
|
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLEGENT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10798484
|
Filing Dt:
|
03/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
DUTY CYCLE CORRECTION CIRCUIT OF DELAY LOCKED LOOP AND DELAY LOCKED LOOP HAVING THE DUTY CYCLE CORRECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10799877
|
Filing Dt:
|
03/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10804182
|
Filing Dt:
|
03/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
|
Title:
|
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10819385
|
Filing Dt:
|
04/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
FLASH MEMORY DEVICE CAPABLE OF PREVENTING PROGRAM DISTURBANCE ACCORDING TO PARTIAL PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10827349
|
Filing Dt:
|
04/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10831815
|
Filing Dt:
|
04/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
PINNED PHOTODIODE FOR A CMOS IMAGE SENSOR AND FABRICATING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
10836267
|
Filing Dt:
|
05/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
MODULAR OUTLET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
10838319
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
|
Title:
|
OUTLET ADD-ON MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10840893
|
Filing Dt:
|
05/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
MANAGING POWER ON INTEGRATED CIRCUITS USING POWER ISLANDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10841785
|
Filing Dt:
|
05/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
FLASH MEMORY DEVICE WITH IMPROVED PROGRAMMING PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10847337
|
Filing Dt:
|
05/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/28/2004
| | | | |
|
Title:
|
MICROLITHOGRAPHIC MASK STRUCTURES AND METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10848913
|
Filing Dt:
|
05/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
DATA DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10853851
|
Filing Dt:
|
05/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
GAPPED-PLATE CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10855968
|
Filing Dt:
|
05/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10856783
|
Filing Dt:
|
06/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
TERNARY CAM CELL FOR REDUCED MATCHLINE CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10860947
|
Filing Dt:
|
06/04/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
DELAY STAGE INSENSITIVE TO OPERATING VOLTAGE AND DELAY CIRCUIT INCLUDING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10861157
|
Filing Dt:
|
06/04/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
|
Title:
|
INTERNAL POWER MANAGEMENT SCHEME FOR A MEMORY CHIP IN DEEP POWER DOWN MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10864173
|
Filing Dt:
|
06/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
METHOD OF REPAIRING A FAILED WORDLINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10875387
|
Filing Dt:
|
06/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
DATA OUTPUT CONTROL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10877037
|
Filing Dt:
|
06/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING ROW PATH CONTROL CIRCUIT AND OPERATING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10879133
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
METHOD FOR FORMING CONDUCTIVE LINE OF SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10879274
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
MEMORY APPARATUS HAVING MULTI-PORT ARCHITECTURE FOR SUPPORTING MULTI PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10879650
|
Filing Dt:
|
06/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
|
Title:
|
ON DIE TERMINATION MODE TRANSFER CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10879754
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10880381
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
WRITE CIRCUIT OF DOUBLE DATA RATE SYNCHRONOUS DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10880432
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
LINK AGGREGATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10883099
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
APPARATUS AND METHOD OF COMPENSATING FOR PHASE DELAY IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10883619
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
|
Title:
|
DATA PATH HAVING GROUNDED PRECHARGE OPERATION AND TEST COMPRESSION CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10885971
|
Filing Dt:
|
07/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING NO CRACKS IN ONE OR MORE LAYERS UNDERLYING A METAL LINE LAYER AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10889194
|
Filing Dt:
|
07/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
REDUNDANCY CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE HAVING A MULTIBLOCK STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10889203
|
Filing Dt:
|
07/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
10890199
|
Filing Dt:
|
07/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10898693
|
Filing Dt:
|
07/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
|
Title:
|
PHASE DETECTION IN A SYNC PULSE GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10912768
|
Filing Dt:
|
08/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
CONTENT ADDRESSABLE MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10914888
|
Filing Dt:
|
08/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
DIELECTRIC MATERIAL FORMING METHODS AND ENHANCED DIELECTRIC MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10917494
|
Filing Dt:
|
08/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10919370
|
Filing Dt:
|
08/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
INPUT SIGNAL RECEIVING DEVICE OF SEMICONDUCTOR MEMORY UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10919491
|
Filing Dt:
|
08/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
HIGH BANDWIDTH MEMORY INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10932771
|
Filing Dt:
|
09/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
REDUCING ASYMMETRICALLY DEPOSITED FILM INDUCED REGISTRATION ERROR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10933424
|
Filing Dt:
|
09/03/2004
|
|
Title:
|
END-OF-RANGE DEFECT MINIMIZATION IN SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10937519
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
PACKET ADDRESSING PROGRAMMABLE DUAL PORT MEMORY DEVICES AND RELATED METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10940231
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
TEMPERATURE-DEPENDENT DRAM SELF-REFRESH CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10940808
|
Filing Dt:
|
08/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
MULTI-LEVEL HIGH VOLTAGE GENERATOR
|
|
