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497
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08863833
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Filing Dt:
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05/27/1997
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Title:
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TEST CHIP CIRCUIT FOR ON-CHIP TIMING CHARACTERIZATION
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Patent #:
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Issue Dt:
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05/18/1999
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Application #:
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08867452
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Filing Dt:
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06/02/1997
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Title:
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MINIMAL CIRCUIT FOR DETECTING LOSS OF PRECISION IN FLOATING POINT NUMBERS
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Patent #:
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Issue Dt:
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07/27/1999
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Application #:
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08871128
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Filing Dt:
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06/09/1997
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Title:
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METHOD FOR STORING AND DECODING INSTRUCTIONS FOR A MICROPROCESSOR HAVING A PLURALITY OF FUNCTION UNITS
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08876730
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Filing Dt:
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06/16/1997
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Title:
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ELECTRONIC APPARATUS HAVING I/O BOARD WITH CABLE-FREE REDUNDANT ADAPTER CARDS THEREON
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Patent #:
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Issue Dt:
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09/14/1999
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Application #:
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08881183
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Filing Dt:
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06/24/1997
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Title:
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METHOD AND APPARATUS FOR EMULATING A PERIPHERAL DEVICE TO ALLOW DEVICE DRIVER DEVELOPMENT BEFORE AVAILABILITY OF THE PERIPHERAL DEVICE
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Patent #:
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Issue Dt:
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08/24/1999
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Application #:
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08881244
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Filing Dt:
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06/24/1997
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Title:
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OUT-OF-ORDER EXECUTION USING ENCODED DEPENDENCIES BETWEEN INSTRUCTIONS IN QUEUES TO DETERMINE STALL VALUES THAT CONTROL INSURANCE OF INSTRUCTIONS FROM THE QUEUES
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08902487
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Filing Dt:
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07/29/1997
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Title:
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MULTIPROBE INSTRUCTION CACHE WITH INSTRUCTION-BASED PROBE HINT GENERATION AND TRAINNG WHEREBY THE CACHE BANK OR WAY TO BE ACCESSED NEXT IS PREDICTED
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Patent #:
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Issue Dt:
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08/18/1998
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Application #:
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08911346
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Filing Dt:
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08/14/1997
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Title:
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QUICK ACCESS TO COMPUTER APPLICATIONS
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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08913933
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Filing Dt:
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09/25/1997
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Title:
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FAULT-TOLERANT PROCESSING METHOD
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Patent #:
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Issue Dt:
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09/28/1999
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Application #:
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08919630
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Filing Dt:
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08/28/1997
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Title:
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HARDWARE AND SOFTWARE FOR THE VISUALIZATION OF THREE-DIMENSIONAL DATA SETS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08920810
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Filing Dt:
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08/29/1997
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Title:
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METHOD FOR THE SECURE REMOTE FLASHING OF A BIOS MEMORY
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08921275
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Filing Dt:
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08/29/1997
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Title:
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VIRTUALLY RELIABLE SHARED MEMORY
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08924720
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Filing Dt:
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08/29/1997
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Title:
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ZERO DELAY REGENERATIVE CIRCUIT FOR NOISE SUPPRESSION ON A COMPUTER DATA BUS
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08930032
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Filing Dt:
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09/26/1997
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Title:
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FAULT-TOLERANT PROCESSING METHOD
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Patent #:
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|
Issue Dt:
|
03/30/1999
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Application #:
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08938951
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Filing Dt:
|
09/18/1997
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Title:
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FAST DETERMINATION O CARRY INPUTS FROM LOWER ORDER PRODUCT FOR RADIX-8 ODD/EVEN MULTIPLIER ARRAY
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08943085
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Filing Dt:
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10/02/1997
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Title:
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METHOD AND APPARATUS FOR CHECKING ASYNCHRONOUS HDL CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08950327
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Filing Dt:
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10/14/1997
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Title:
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REPLACEMENT OF ERRONEOUS FIRMWARE IN A REDUNDANT NON-VOLATILE MEMORY SYSTEM
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08953280
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Filing Dt:
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10/17/1997
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Title:
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RELATIVE LOGARITHMIC TIME STAMPS FOR REDUCED MEMORY MAP SIZE
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08957544
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Filing Dt:
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10/24/1997
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Title:
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TECHNIQUE FOR REDUCING LATENCY OF INTER-REFERENCE ORDERING USING COMMIT SIGNALS IN A MULTIPROCESSOR SYSTEM HAVING SHARED CACHES
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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08958291
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Filing Dt:
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10/27/1997
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Title:
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HARDWARE-ASSISTED FIRMWARE TRACING METHOD AND APPARATUS
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Patent #:
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|
Issue Dt:
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10/12/1999
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Application #:
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08971630
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Filing Dt:
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11/17/1997
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Title:
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APPARATUS AND METHOD FOR SERIALIZED SET PREDICTION
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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08977438
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Filing Dt:
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11/26/1997
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Title:
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APPARATUS FOR DETERMINING THE INSTANTANEOUS AVERAGE NUMBER OF INSTRUCTIONS PROCESSED
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08978932
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Filing Dt:
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11/26/1997
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Title:
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METHOD FOR DYNAMICALLY REMAPPING A VIRTUAL ADDRESS TO A PHYSICAL ADDRESS TO MAINTAIN AN EVEN DISTRITUTION OF CACHE PAGE ADDRESSES IN A VIRTUAL ADDRESS SPACE
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08978940
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Filing Dt:
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11/26/1997
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Title:
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MEMORY ALLOCATION TECHNIQUE FOR MAINTAINING AN EVEN DISTRIBUTION OF CACHE PAGE ADDRESSES WITHIN A DATA STRUCTURE
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08979738
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Filing Dt:
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11/26/1997
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Title:
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METHOD FOR RECLAIMING PHYSICAL PAGES OF MEMORY WHILE MAINTAINING AN EVEN DISTRIBUTION OF CACHE PAGE ADDRESSES WITHIN AN ADDRESS SPACE
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08986078
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Filing Dt:
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12/05/1997
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Title:
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VERSATILE PRINTED CIRCUIT BOARD FOR TESTING PROCESSING RELIABILITY
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08999099
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Filing Dt:
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12/29/1997
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Title:
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GENERATION OF REPRODUCIBLE RANDOM INITIAL STATES IN RTL SIMULATORS
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Patent #:
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|
Issue Dt:
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07/13/1999
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Application #:
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09018320
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Filing Dt:
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02/03/1998
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Title:
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METHOD AND APPARATUS FOR MAXIMIZING UTILIZATION OF AN INTERNAL PROCESSOR BUS IN THE CONTEXT OF EXTERNAL TRANSACTIONS RUNNING AT SPEEDS FRACTIONALLY GREATER THAN INTERNAL TRANSACTION TIMES
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Patent #:
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|
Issue Dt:
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12/07/1999
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Application #:
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09023665
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Filing Dt:
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02/10/1998
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Title:
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SCANNING MEMORY DEVICE AND ERROR CORRECTION METHOD
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Patent #:
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|
Issue Dt:
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08/15/2000
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Application #:
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09038364
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Filing Dt:
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03/10/1998
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Title:
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HIGH SPEED REGISTER FILE ORGANIZATION FOR A PIPELINED COMPUTER ARCHITECTURE
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Patent #:
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|
Issue Dt:
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01/25/2000
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Application #:
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09041905
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Filing Dt:
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03/13/1998
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Title:
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REDUCED-LATENCY FLOATING-POINT PIPELINE USING NORMALIZATION SHIFTS OF BOTH OPERANDS
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|
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Patent #:
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|
Issue Dt:
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05/10/2005
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Application #:
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09052358
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Filing Dt:
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03/30/1998
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Title:
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ANALYZING EFFECTIVENESS OF A COMPUTER CACHE BY ESTIMATING A HIT RATE BASED ON APPLYING A SUBSET OF REAL-TIME ADDRESSES TO A MODEL OF THE CACHE
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09062050
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Filing Dt:
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04/17/1998
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Title:
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MECHANISM FOR REMOVAL OF SURFACE MOUNT CONNECTORS USING HEAT CONDUCTION THROUGH PINS
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Patent #:
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|
Issue Dt:
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06/06/2000
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Application #:
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09070866
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Filing Dt:
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04/30/1998
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Title:
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METHOD FOR FLASHING ESCD AND VARIABLES INTO A ROM
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Patent #:
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|
Issue Dt:
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11/16/1999
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Application #:
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09073670
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Filing Dt:
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05/06/1998
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Title:
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A METHOD AND APPARATUS FOR IMPROVING READ/WRITE STABILITY OF A SINGLE-PORT SRAM CELL
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Patent #:
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|
Issue Dt:
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06/19/2001
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Application #:
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09089474
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Filing Dt:
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06/02/1998
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Title:
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ARBITER SYSTEM FOR CENTRAL PROCESSING UNIT HAVING DUAL DOMINOED ENCODERS FOR FOUR INSTRUCTION ISSUE PER MACHINE CYCLE
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09099304
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Filing Dt:
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06/18/1998
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Title:
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METHOD AND APPARATUS FOR DEVELOPING MULTIPROCESSOR CACHE CONTROL PROTOCOLS BY PRESENTING A CLEAN VICTIM SIGNAL TO AN EXTERNAL SYSTEM
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Patent #:
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|
Issue Dt:
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10/09/2001
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Application #:
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09104921
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Filing Dt:
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06/25/1998
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Title:
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ON CHIP CMOS VLSI REFERENCE VOLTAGE WITH FEEDBACK FOR HYSTERESIS NOISE MARGIN
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Patent #:
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|
Issue Dt:
|
09/12/2000
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Application #:
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09107662
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Filing Dt:
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06/30/1998
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Title:
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PCB MOUNTING ARRANGEMENT FOR TWO COMPONENTS REQUIRING HIGH-SPEED CONNECTIONS TO A THIRD COMPONENT
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|
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Patent #:
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|
Issue Dt:
|
09/18/2001
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Application #:
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09114753
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Filing Dt:
|
07/13/1998
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Title:
|
METHOD FOR DETERMINING A RANDOM PERMUTATION OF VARIABLES BY APPLYING A TEST FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
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Application #:
|
09138957
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Filing Dt:
|
08/24/1998
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Publication #:
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|
Pub Dt:
|
06/06/2002
| | | | |
Title:
|
METHOD FOR MAPPING INSTRUCTIONS USING A SET OF VALID AND INVALID LOGICAL TO PHYSICAL REGISTER ASSIGNMENTS INDICATED BY BITS OF A VALID VECTOR TOGETHER WITH A LOGICAL REGISTER LIST
|
|
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Patent #:
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|
Issue Dt:
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08/23/2005
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Application #:
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09164527
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Filing Dt:
|
09/30/1998
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Publication #:
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|
Pub Dt:
|
10/10/2002
| | | | |
Title:
|
LOWERING DISPLAY POWER CONSUMPTION BY DITHERING BRIGHTNESS
|
|
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Patent #:
|
|
Issue Dt:
|
11/13/2001
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Application #:
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09166410
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Filing Dt:
|
10/05/1998
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Title:
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METHOD AND APPARATUS FOR DYNAMIC SIGNAL MODIFICATION ON A PARALLEL BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
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Application #:
|
09182715
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Filing Dt:
|
10/29/1998
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Title:
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SYSTEM AND METHOD FOR TESTING A MICROPROCESSOR WITH AN ONBOARD TEST VECTOR GENERATOR
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|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
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Application #:
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09183311
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Filing Dt:
|
10/30/1998
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Title:
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DIGITAL CIRCUIT TO COUNT LIKE SIGNALS IN A DATA WORD
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Patent #:
|
|
Issue Dt:
|
12/28/1999
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Application #:
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09183734
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Filing Dt:
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10/30/1998
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Title:
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COMPUTER METHOD AND APPARATUS FOR ANALYZING PROGRAM INSTRUCTIONS EXECUTING IN A COMPUTER SYSTEM
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Patent #:
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|
Issue Dt:
|
06/18/2002
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Application #:
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09191679
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Filing Dt:
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11/13/1998
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Title:
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EMBEDDED RAM WITH SELF-TEST AND SELF-REPAIR WITH SPARE ROWS AND COLUMNS.
|
|
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Patent #:
|
|
Issue Dt:
|
05/01/2001
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Application #:
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09204817
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Filing Dt:
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12/02/1998
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Title:
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DIGITAL-TO-ANALOG CONVERTER HAVING SWITCHABLE CURRENT SOURCES AND RESISTOR STRING
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|
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Patent #:
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|
Issue Dt:
|
05/30/2000
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Application #:
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09207303
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Filing Dt:
|
12/08/1998
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Title:
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CMOS CIRCUIT TECHNIQUES FOR IMPROVED SWITCHING SPEED OF SINGLE ENDED AND DIFFERENTIAL DYNAMIC LOGIC
|
|
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Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
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09208169
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Filing Dt:
|
12/09/1998
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Title:
|
FAST DETERMINATION OF CARRY INPUTS FROM LOWER ORDER PRODUCT FOR RADIX-8 ODD/EVEN MULTIPLIER ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
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Application #:
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09209018
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Filing Dt:
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12/10/1998
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Title:
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SYSTEM AND METHOD FOR EFFICIENT VERIFICATION OF FUNCTIONAL EQUIVALENCE BETWEEN DESIGN MODELS
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|
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Patent #:
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|
Issue Dt:
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03/19/2002
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Application #:
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09231407
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Filing Dt:
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01/13/1999
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Title:
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SYSTEM FOR PROTECTING OUTPUT DRIVERS CONNECTED TO A POWERED-OFF LOAD
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09234021
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Filing Dt:
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01/19/1999
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Title:
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SPLIT REMAINDER DIVIDER
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09237425
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Filing Dt:
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01/26/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING NOR GATES AND NAND GATES
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Patent #:
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|
Issue Dt:
|
04/02/2002
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Application #:
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09241000
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Filing Dt:
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02/01/1999
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Title:
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PASS-GATE INPUTS THAT TEMPORARILY HOLD STATE ON A HIGH INPUT IMPEDANCE, STROBED CMOS DIFFERENTIAL SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09244872
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Filing Dt:
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02/05/1999
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Title:
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HARDWARE TEST COVERAGE USING INTER-CHIP EVENT FILTERING IN MULTI-CHIP SIMULATIONS
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Patent #:
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|
Issue Dt:
|
09/18/2001
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Application #:
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09249494
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Filing Dt:
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02/12/1999
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Title:
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METHOD FOR PROVIDING ACCESS PROTECTION FOR SCSI STORAGE DEVICES
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09252378
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Filing Dt:
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02/18/1999
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Title:
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EVALUATION OF THE DESIGN QUALITY OF NETWORK NODES
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|
|
Patent #:
|
|
Issue Dt:
|
03/05/2002
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Application #:
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09270691
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Filing Dt:
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03/17/1999
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Title:
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AUTOMATED SEMICONDUCTOR IDENTIFICATION SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
12/18/2001
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Application #:
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09273582
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Filing Dt:
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03/23/1999
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Title:
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TEST RESULTS CHECKING VIA PREDICTIVE-REACTIVE EMULATION
|
|
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Patent #:
|
|
Issue Dt:
|
06/19/2001
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Application #:
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09273631
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Filing Dt:
|
03/23/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING PASS FETS
|
|
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Patent #:
|
|
Issue Dt:
|
04/18/2006
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Application #:
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09273784
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Filing Dt:
|
03/22/1999
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Title:
|
METHOD AND APPARATUS FOR EVALUATING THE DESIGN QUALITY OF NETWORK NODES
|
|
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Patent #:
|
|
Issue Dt:
|
06/21/2005
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Application #:
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09273820
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Filing Dt:
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03/22/1999
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Title:
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SYSTEM AND METHOD FOR EXECUTING TESTS ON AN INTEGRATED CIRCUIT DESIGN
|
|
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
|
09274798
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Filing Dt:
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03/23/1999
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Title:
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METHOD AND APPARATUS FOR GENERATING A DATABASE WHICH IS USED FOR DETERMINING THE DESIGN QUALITY OF NETWORK NODES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
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Application #:
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09281501
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Filing Dt:
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03/30/1999
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Title:
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METHOD AND APPARATUS FOR ROUNDING FLOATING POINT RESULTS IN A DIGITAL PROCESSING SYSTEM
|
|
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Patent #:
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|
Issue Dt:
|
08/05/2003
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Application #:
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09282115
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Filing Dt:
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03/31/1999
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Title:
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DECREASING MEMORY RETURN LATENCY BY PREDICTING THE ORDER OF COMPLETION OF PARTIALLY READY RETURNS
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Patent #:
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Issue Dt:
|
03/05/2002
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Application #:
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09286185
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Filing Dt:
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04/05/1999
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Title:
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DAMASCENE PROCESS FOR MOSFET FABRICATION
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09290806
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Filing Dt:
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04/13/1999
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Title:
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METHOD AND APPARATUS FOR EVALUATING PROCESSORS FOR ARCHITECTURAL COMPLIANCE
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09291721
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Filing Dt:
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04/14/1999
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Title:
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METHOD AND APPARATUS FOR ESTIMATING ELMORE DELAYS WITHIN CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09292051
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Filing Dt:
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04/14/1999
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Title:
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METHOD AND APPARATUS FOR PERFORMING TIMING VERIFICATION OF A CIRCUIT
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|
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Patent #:
|
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Issue Dt:
|
12/04/2001
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Application #:
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09298265
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Filing Dt:
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04/22/1999
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Title:
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METHOD FOR ANALYZING MANUFACTURING TEST PATTERN COVERAGE OF CRITICAL DELAY CIRCUIT PATHS
|
|
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Patent #:
|
|
Issue Dt:
|
10/09/2001
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Application #:
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09299975
|
Filing Dt:
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04/27/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING NFETS THAT PULL UP TO VDD AND PFETS THAT PULL DOWN TO GROUND
|
|
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Patent #:
|
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Issue Dt:
|
04/09/2002
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Application #:
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09300016
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Filing Dt:
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04/27/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR NOMINAL-VOLTAGE POWER SUPPLY OR I/O WITH HIGH-VOLTAGE REFERENCE
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09300129
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Filing Dt:
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04/27/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH HIGH-VOLTAGE REFERENCE
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09300205
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Filing Dt:
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04/27/1999
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Title:
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SYSTEM AND METHOD FOR EVALUATING THE LOADING OF A CLOCK DRIVER
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09301830
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Filing Dt:
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04/29/1999
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Title:
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FASTER MULTIPLY/ACCUMULATOR
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09311255
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Filing Dt:
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05/13/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING FETS THAT ARE SUSCEPTIBLE TO BOOTSTRAPPING
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09311313
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Filing Dt:
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05/13/1999
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Title:
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METHOD AND APPARATUS FOR DETERMINING WHETHER AN ELEMENT IN AN INTEGRATED CIRCUIT IS A FEEDBACK ELEMENT
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09311314
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Filing Dt:
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05/13/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING THE OUTPUT OF A CLOCK DRIVER
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
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09318907
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Filing Dt:
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05/26/1999
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Title:
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SYSTEM AND METHOD FOR PROPAGATING CLOCK NODES IN A NETLIST OF CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09318988
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Filing Dt:
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05/26/1999
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Title:
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METHOD AND APPARATUS FOR DETERMINING THE STRENGTHS AND WEAKNESS OF PATHS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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09336046
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Filing Dt:
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06/18/1999
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Title:
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FORMING LINKED LISTS USING CONTENT ADDRESSABLE MEMORY
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09345079
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Filing Dt:
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06/30/1999
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Title:
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METHOD AND APPARATUS FOR PRIORITIZING THE ORDER IN WHICH CHECKS ARE PERFORMED ON A NODE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09349269
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Filing Dt:
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07/07/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH NOMINAL-VOLTAGE REFERENCE
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Patent #:
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Issue Dt:
|
10/23/2001
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Application #:
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09358317
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Filing Dt:
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07/21/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING MULTIPLEXERS IN A CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09358837
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Filing Dt:
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07/21/1999
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Title:
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SYSTEM AND METHOD FOR APPROXIMATING THE COUPLING VOLTAGE NOISE ON A NODE
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Patent #:
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Issue Dt:
|
09/09/2003
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Application #:
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09390199
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Filing Dt:
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09/07/1999
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Title:
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SUPERSCALAR PROCESSING SYSTEM AND METHOD FOR SELECTIVELY STALLING INSTRUCTIONS WITHIN AN ISSUE GROUP
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09404981
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Filing Dt:
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09/23/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH NOMINAL-OR HIGH-VOLTAGE REFERENCE
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|
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Patent #:
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Issue Dt:
|
12/04/2001
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Application #:
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09405935
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Filing Dt:
|
09/27/1999
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Title:
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HIGH-CURRENT POWER BUS SYSTEM
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|
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Patent #:
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Issue Dt:
|
03/23/2004
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Application #:
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09417582
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Filing Dt:
|
10/14/1999
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Title:
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DETECTING A COMPILER GROUPING ERROR FOR A COMPILED INSTRUCTION GROUP BASED ON ASSOCIATED REGISTERS
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|
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Patent #:
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Issue Dt:
|
11/18/2003
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Application #:
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09418286
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Filing Dt:
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10/14/1999
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Title:
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SYSTEM AND METHOD FOR DETECTING AN ERRONEOUS DATA HAZARD BETWEEN INSTRUCTIONS OF AN INSTRUCTION GROUP AND RESULTING FROM A COMPILER GROUPING ERROR
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09422813
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Filing Dt:
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10/21/1999
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Title:
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BIFURCATED CONTACT WITH A CONNECTING MEMBER THAT CAN ADD REDUNDANT CONTACT POINTS TO SINGLE POINT CONNECTORS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09447019
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Filing Dt:
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11/22/1999
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Title:
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METHOD TO COMPRESS A PIECEWISE LINEAR WAVEFORM SO COMPRESSION ERROR OCCURS ON ONLY ONE SIDE OF THE WAVEFORM
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Patent #:
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Issue Dt:
|
03/25/2003
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Application #:
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09448344
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Filing Dt:
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11/23/1999
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Title:
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METHOD AND APPARATUS FOR TESTING ERROR DETECTION
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Patent #:
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Issue Dt:
|
04/27/2004
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Application #:
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09451499
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Filing Dt:
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11/30/1999
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Title:
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SYSTEM AND METHOD FOR TRACKING AND PROCESSING PARALLEL COHERENT MEMORY ACCESSES
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|
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Patent #:
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Issue Dt:
|
03/09/2004
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Application #:
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09465175
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Filing Dt:
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12/17/1999
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Title:
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OUT OF SEQUENCE REMOVAL AND COMPACTION OF INSTRUCTION QUEUE BY DETERMINING INCLUSIVE INVALID INSTRUCTION COUNT BELOW A ROW AND MOVING INSTRUCTION AND VALIDITY INDICATOR FROM SELECTED ROW TO PRESENT ROW USING DIAGONAL VALUES
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Patent #:
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Issue Dt:
|
01/13/2004
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Application #:
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09466503
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Filing Dt:
|
12/17/1999
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Title:
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METHOD AND APPARATUS FOR GENERATING RANDOM CODE
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|
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Patent #:
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Issue Dt:
|
07/08/2003
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Application #:
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09484138
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Filing Dt:
|
01/18/2000
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Title:
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LOCAL STALL/HAZARD DETECT IN SUPERSCALAR, PIPELINED MICROPROCESSOR
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|
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Patent #:
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|
Issue Dt:
|
11/04/2003
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Application #:
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09490392
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Filing Dt:
|
01/24/2000
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Title:
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PROCESSING SYSTEM AND METHOD UTILIZING A SCOREBOARD TO DETECT DATA HAZARDS BETWEEN INSTRUCTIONS OF COMPUTER PROGRAMS
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|
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Patent #:
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|
Issue Dt:
|
09/16/2003
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Application #:
|
09490395
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Filing Dt:
|
01/24/2000
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Title:
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SYSTEM AND METHOD FOR PROVIDING PREDICATE DATA TO MULTIPLE PIPELINE STAGES
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