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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:026198/0139   Pages: 43
Recorded: 04/26/2011
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 497
Page 2 of 5
Pages: 1 2 3 4 5
1
Patent #:
Issue Dt:
07/28/1998
Application #:
08863833
Filing Dt:
05/27/1997
Title:
TEST CHIP CIRCUIT FOR ON-CHIP TIMING CHARACTERIZATION
2
Patent #:
Issue Dt:
05/18/1999
Application #:
08867452
Filing Dt:
06/02/1997
Title:
MINIMAL CIRCUIT FOR DETECTING LOSS OF PRECISION IN FLOATING POINT NUMBERS
3
Patent #:
Issue Dt:
07/27/1999
Application #:
08871128
Filing Dt:
06/09/1997
Title:
METHOD FOR STORING AND DECODING INSTRUCTIONS FOR A MICROPROCESSOR HAVING A PLURALITY OF FUNCTION UNITS
4
Patent #:
Issue Dt:
11/16/1999
Application #:
08876730
Filing Dt:
06/16/1997
Title:
ELECTRONIC APPARATUS HAVING I/O BOARD WITH CABLE-FREE REDUNDANT ADAPTER CARDS THEREON
5
Patent #:
Issue Dt:
09/14/1999
Application #:
08881183
Filing Dt:
06/24/1997
Title:
METHOD AND APPARATUS FOR EMULATING A PERIPHERAL DEVICE TO ALLOW DEVICE DRIVER DEVELOPMENT BEFORE AVAILABILITY OF THE PERIPHERAL DEVICE
6
Patent #:
Issue Dt:
08/24/1999
Application #:
08881244
Filing Dt:
06/24/1997
Title:
OUT-OF-ORDER EXECUTION USING ENCODED DEPENDENCIES BETWEEN INSTRUCTIONS IN QUEUES TO DETERMINE STALL VALUES THAT CONTROL INSURANCE OF INSTRUCTIONS FROM THE QUEUES
7
Patent #:
Issue Dt:
08/03/1999
Application #:
08902487
Filing Dt:
07/29/1997
Title:
MULTIPROBE INSTRUCTION CACHE WITH INSTRUCTION-BASED PROBE HINT GENERATION AND TRAINNG WHEREBY THE CACHE BANK OR WAY TO BE ACCESSED NEXT IS PREDICTED
8
Patent #:
Issue Dt:
08/18/1998
Application #:
08911346
Filing Dt:
08/14/1997
Title:
QUICK ACCESS TO COMPUTER APPLICATIONS
9
Patent #:
Issue Dt:
02/08/2000
Application #:
08913933
Filing Dt:
09/25/1997
Title:
FAULT-TOLERANT PROCESSING METHOD
10
Patent #:
Issue Dt:
09/28/1999
Application #:
08919630
Filing Dt:
08/28/1997
Title:
HARDWARE AND SOFTWARE FOR THE VISUALIZATION OF THREE-DIMENSIONAL DATA SETS
11
Patent #:
Issue Dt:
12/28/1999
Application #:
08920810
Filing Dt:
08/29/1997
Title:
METHOD FOR THE SECURE REMOTE FLASHING OF A BIOS MEMORY
12
Patent #:
Issue Dt:
11/23/1999
Application #:
08921275
Filing Dt:
08/29/1997
Title:
VIRTUALLY RELIABLE SHARED MEMORY
13
Patent #:
Issue Dt:
11/30/1999
Application #:
08924720
Filing Dt:
08/29/1997
Title:
ZERO DELAY REGENERATIVE CIRCUIT FOR NOISE SUPPRESSION ON A COMPUTER DATA BUS
14
Patent #:
Issue Dt:
03/07/2000
Application #:
08930032
Filing Dt:
09/26/1997
Title:
FAULT-TOLERANT PROCESSING METHOD
15
Patent #:
Issue Dt:
03/30/1999
Application #:
08938951
Filing Dt:
09/18/1997
Title:
FAST DETERMINATION O CARRY INPUTS FROM LOWER ORDER PRODUCT FOR RADIX-8 ODD/EVEN MULTIPLIER ARRAY
16
Patent #:
Issue Dt:
08/08/2000
Application #:
08943085
Filing Dt:
10/02/1997
Title:
METHOD AND APPARATUS FOR CHECKING ASYNCHRONOUS HDL CIRCUIT DESIGNS
17
Patent #:
Issue Dt:
12/28/1999
Application #:
08950327
Filing Dt:
10/14/1997
Title:
REPLACEMENT OF ERRONEOUS FIRMWARE IN A REDUNDANT NON-VOLATILE MEMORY SYSTEM
18
Patent #:
Issue Dt:
11/02/1999
Application #:
08953280
Filing Dt:
10/17/1997
Title:
RELATIVE LOGARITHMIC TIME STAMPS FOR REDUCED MEMORY MAP SIZE
19
Patent #:
Issue Dt:
04/25/2000
Application #:
08957544
Filing Dt:
10/24/1997
Title:
TECHNIQUE FOR REDUCING LATENCY OF INTER-REFERENCE ORDERING USING COMMIT SIGNALS IN A MULTIPROCESSOR SYSTEM HAVING SHARED CACHES
20
Patent #:
Issue Dt:
07/25/2000
Application #:
08958291
Filing Dt:
10/27/1997
Title:
HARDWARE-ASSISTED FIRMWARE TRACING METHOD AND APPARATUS
21
Patent #:
Issue Dt:
10/12/1999
Application #:
08971630
Filing Dt:
11/17/1997
Title:
APPARATUS AND METHOD FOR SERIALIZED SET PREDICTION
22
Patent #:
Issue Dt:
01/16/2001
Application #:
08977438
Filing Dt:
11/26/1997
Title:
APPARATUS FOR DETERMINING THE INSTANTANEOUS AVERAGE NUMBER OF INSTRUCTIONS PROCESSED
23
Patent #:
Issue Dt:
02/15/2000
Application #:
08978932
Filing Dt:
11/26/1997
Title:
METHOD FOR DYNAMICALLY REMAPPING A VIRTUAL ADDRESS TO A PHYSICAL ADDRESS TO MAINTAIN AN EVEN DISTRITUTION OF CACHE PAGE ADDRESSES IN A VIRTUAL ADDRESS SPACE
24
Patent #:
Issue Dt:
01/18/2000
Application #:
08978940
Filing Dt:
11/26/1997
Title:
MEMORY ALLOCATION TECHNIQUE FOR MAINTAINING AN EVEN DISTRIBUTION OF CACHE PAGE ADDRESSES WITHIN A DATA STRUCTURE
25
Patent #:
Issue Dt:
11/30/1999
Application #:
08979738
Filing Dt:
11/26/1997
Title:
METHOD FOR RECLAIMING PHYSICAL PAGES OF MEMORY WHILE MAINTAINING AN EVEN DISTRIBUTION OF CACHE PAGE ADDRESSES WITHIN AN ADDRESS SPACE
26
Patent #:
Issue Dt:
03/21/2000
Application #:
08986078
Filing Dt:
12/05/1997
Title:
VERSATILE PRINTED CIRCUIT BOARD FOR TESTING PROCESSING RELIABILITY
27
Patent #:
Issue Dt:
05/09/2000
Application #:
08999099
Filing Dt:
12/29/1997
Title:
GENERATION OF REPRODUCIBLE RANDOM INITIAL STATES IN RTL SIMULATORS
28
Patent #:
Issue Dt:
07/13/1999
Application #:
09018320
Filing Dt:
02/03/1998
Title:
METHOD AND APPARATUS FOR MAXIMIZING UTILIZATION OF AN INTERNAL PROCESSOR BUS IN THE CONTEXT OF EXTERNAL TRANSACTIONS RUNNING AT SPEEDS FRACTIONALLY GREATER THAN INTERNAL TRANSACTION TIMES
29
Patent #:
Issue Dt:
12/07/1999
Application #:
09023665
Filing Dt:
02/10/1998
Title:
SCANNING MEMORY DEVICE AND ERROR CORRECTION METHOD
30
Patent #:
Issue Dt:
08/15/2000
Application #:
09038364
Filing Dt:
03/10/1998
Title:
HIGH SPEED REGISTER FILE ORGANIZATION FOR A PIPELINED COMPUTER ARCHITECTURE
31
Patent #:
Issue Dt:
01/25/2000
Application #:
09041905
Filing Dt:
03/13/1998
Title:
REDUCED-LATENCY FLOATING-POINT PIPELINE USING NORMALIZATION SHIFTS OF BOTH OPERANDS
32
Patent #:
Issue Dt:
05/10/2005
Application #:
09052358
Filing Dt:
03/30/1998
Title:
ANALYZING EFFECTIVENESS OF A COMPUTER CACHE BY ESTIMATING A HIT RATE BASED ON APPLYING A SUBSET OF REAL-TIME ADDRESSES TO A MODEL OF THE CACHE
33
Patent #:
Issue Dt:
03/21/2000
Application #:
09062050
Filing Dt:
04/17/1998
Title:
MECHANISM FOR REMOVAL OF SURFACE MOUNT CONNECTORS USING HEAT CONDUCTION THROUGH PINS
34
Patent #:
Issue Dt:
06/06/2000
Application #:
09070866
Filing Dt:
04/30/1998
Title:
METHOD FOR FLASHING ESCD AND VARIABLES INTO A ROM
35
Patent #:
Issue Dt:
11/16/1999
Application #:
09073670
Filing Dt:
05/06/1998
Title:
A METHOD AND APPARATUS FOR IMPROVING READ/WRITE STABILITY OF A SINGLE-PORT SRAM CELL
36
Patent #:
Issue Dt:
06/19/2001
Application #:
09089474
Filing Dt:
06/02/1998
Title:
ARBITER SYSTEM FOR CENTRAL PROCESSING UNIT HAVING DUAL DOMINOED ENCODERS FOR FOUR INSTRUCTION ISSUE PER MACHINE CYCLE
37
Patent #:
Issue Dt:
05/28/2002
Application #:
09099304
Filing Dt:
06/18/1998
Title:
METHOD AND APPARATUS FOR DEVELOPING MULTIPROCESSOR CACHE CONTROL PROTOCOLS BY PRESENTING A CLEAN VICTIM SIGNAL TO AN EXTERNAL SYSTEM
38
Patent #:
Issue Dt:
10/09/2001
Application #:
09104921
Filing Dt:
06/25/1998
Title:
ON CHIP CMOS VLSI REFERENCE VOLTAGE WITH FEEDBACK FOR HYSTERESIS NOISE MARGIN
39
Patent #:
Issue Dt:
09/12/2000
Application #:
09107662
Filing Dt:
06/30/1998
Title:
PCB MOUNTING ARRANGEMENT FOR TWO COMPONENTS REQUIRING HIGH-SPEED CONNECTIONS TO A THIRD COMPONENT
40
Patent #:
Issue Dt:
09/18/2001
Application #:
09114753
Filing Dt:
07/13/1998
Title:
METHOD FOR DETERMINING A RANDOM PERMUTATION OF VARIABLES BY APPLYING A TEST FUNCTION
41
Patent #:
Issue Dt:
06/11/2002
Application #:
09138957
Filing Dt:
08/24/1998
Publication #:
Pub Dt:
06/06/2002
Title:
METHOD FOR MAPPING INSTRUCTIONS USING A SET OF VALID AND INVALID LOGICAL TO PHYSICAL REGISTER ASSIGNMENTS INDICATED BY BITS OF A VALID VECTOR TOGETHER WITH A LOGICAL REGISTER LIST
42
Patent #:
Issue Dt:
08/23/2005
Application #:
09164527
Filing Dt:
09/30/1998
Publication #:
Pub Dt:
10/10/2002
Title:
LOWERING DISPLAY POWER CONSUMPTION BY DITHERING BRIGHTNESS
43
Patent #:
Issue Dt:
11/13/2001
Application #:
09166410
Filing Dt:
10/05/1998
Title:
METHOD AND APPARATUS FOR DYNAMIC SIGNAL MODIFICATION ON A PARALLEL BUS
44
Patent #:
Issue Dt:
06/26/2001
Application #:
09182715
Filing Dt:
10/29/1998
Title:
SYSTEM AND METHOD FOR TESTING A MICROPROCESSOR WITH AN ONBOARD TEST VECTOR GENERATOR
45
Patent #:
Issue Dt:
03/21/2000
Application #:
09183311
Filing Dt:
10/30/1998
Title:
DIGITAL CIRCUIT TO COUNT LIKE SIGNALS IN A DATA WORD
46
Patent #:
Issue Dt:
12/28/1999
Application #:
09183734
Filing Dt:
10/30/1998
Title:
COMPUTER METHOD AND APPARATUS FOR ANALYZING PROGRAM INSTRUCTIONS EXECUTING IN A COMPUTER SYSTEM
47
Patent #:
Issue Dt:
06/18/2002
Application #:
09191679
Filing Dt:
11/13/1998
Title:
EMBEDDED RAM WITH SELF-TEST AND SELF-REPAIR WITH SPARE ROWS AND COLUMNS.
48
Patent #:
Issue Dt:
05/01/2001
Application #:
09204817
Filing Dt:
12/02/1998
Title:
DIGITAL-TO-ANALOG CONVERTER HAVING SWITCHABLE CURRENT SOURCES AND RESISTOR STRING
49
Patent #:
Issue Dt:
05/30/2000
Application #:
09207303
Filing Dt:
12/08/1998
Title:
CMOS CIRCUIT TECHNIQUES FOR IMPROVED SWITCHING SPEED OF SINGLE ENDED AND DIFFERENTIAL DYNAMIC LOGIC
50
Patent #:
Issue Dt:
10/10/2000
Application #:
09208169
Filing Dt:
12/09/1998
Title:
FAST DETERMINATION OF CARRY INPUTS FROM LOWER ORDER PRODUCT FOR RADIX-8 ODD/EVEN MULTIPLIER ARRAY
51
Patent #:
Issue Dt:
11/20/2001
Application #:
09209018
Filing Dt:
12/10/1998
Title:
SYSTEM AND METHOD FOR EFFICIENT VERIFICATION OF FUNCTIONAL EQUIVALENCE BETWEEN DESIGN MODELS
52
Patent #:
Issue Dt:
03/19/2002
Application #:
09231407
Filing Dt:
01/13/1999
Title:
SYSTEM FOR PROTECTING OUTPUT DRIVERS CONNECTED TO A POWERED-OFF LOAD
53
Patent #:
Issue Dt:
11/13/2001
Application #:
09234021
Filing Dt:
01/19/1999
Title:
SPLIT REMAINDER DIVIDER
54
Patent #:
Issue Dt:
06/20/2000
Application #:
09237425
Filing Dt:
01/26/1999
Title:
SYSTEM AND METHOD FOR DETECTING NOR GATES AND NAND GATES
55
Patent #:
Issue Dt:
04/02/2002
Application #:
09241000
Filing Dt:
02/01/1999
Title:
PASS-GATE INPUTS THAT TEMPORARILY HOLD STATE ON A HIGH INPUT IMPEDANCE, STROBED CMOS DIFFERENTIAL SENSE AMPLIFIER
56
Patent #:
Issue Dt:
10/02/2001
Application #:
09244872
Filing Dt:
02/05/1999
Title:
HARDWARE TEST COVERAGE USING INTER-CHIP EVENT FILTERING IN MULTI-CHIP SIMULATIONS
57
Patent #:
Issue Dt:
09/18/2001
Application #:
09249494
Filing Dt:
02/12/1999
Title:
METHOD FOR PROVIDING ACCESS PROTECTION FOR SCSI STORAGE DEVICES
58
Patent #:
Issue Dt:
08/14/2001
Application #:
09252378
Filing Dt:
02/18/1999
Title:
EVALUATION OF THE DESIGN QUALITY OF NETWORK NODES
59
Patent #:
Issue Dt:
03/05/2002
Application #:
09270691
Filing Dt:
03/17/1999
Title:
AUTOMATED SEMICONDUCTOR IDENTIFICATION SYSTEM
60
Patent #:
Issue Dt:
12/18/2001
Application #:
09273582
Filing Dt:
03/23/1999
Title:
TEST RESULTS CHECKING VIA PREDICTIVE-REACTIVE EMULATION
61
Patent #:
Issue Dt:
06/19/2001
Application #:
09273631
Filing Dt:
03/23/1999
Title:
SYSTEM AND METHOD FOR DETECTING PASS FETS
62
Patent #:
Issue Dt:
04/18/2006
Application #:
09273784
Filing Dt:
03/22/1999
Title:
METHOD AND APPARATUS FOR EVALUATING THE DESIGN QUALITY OF NETWORK NODES
63
Patent #:
Issue Dt:
06/21/2005
Application #:
09273820
Filing Dt:
03/22/1999
Title:
SYSTEM AND METHOD FOR EXECUTING TESTS ON AN INTEGRATED CIRCUIT DESIGN
64
Patent #:
Issue Dt:
08/21/2001
Application #:
09274798
Filing Dt:
03/23/1999
Title:
METHOD AND APPARATUS FOR GENERATING A DATABASE WHICH IS USED FOR DETERMINING THE DESIGN QUALITY OF NETWORK NODES
65
Patent #:
Issue Dt:
04/02/2002
Application #:
09281501
Filing Dt:
03/30/1999
Title:
METHOD AND APPARATUS FOR ROUNDING FLOATING POINT RESULTS IN A DIGITAL PROCESSING SYSTEM
66
Patent #:
Issue Dt:
08/05/2003
Application #:
09282115
Filing Dt:
03/31/1999
Title:
DECREASING MEMORY RETURN LATENCY BY PREDICTING THE ORDER OF COMPLETION OF PARTIALLY READY RETURNS
67
Patent #:
Issue Dt:
03/05/2002
Application #:
09286185
Filing Dt:
04/05/1999
Title:
DAMASCENE PROCESS FOR MOSFET FABRICATION
68
Patent #:
Issue Dt:
05/13/2003
Application #:
09290806
Filing Dt:
04/13/1999
Title:
METHOD AND APPARATUS FOR EVALUATING PROCESSORS FOR ARCHITECTURAL COMPLIANCE
69
Patent #:
Issue Dt:
08/12/2003
Application #:
09291721
Filing Dt:
04/14/1999
Title:
METHOD AND APPARATUS FOR ESTIMATING ELMORE DELAYS WITHIN CIRCUIT DESIGNS
70
Patent #:
Issue Dt:
12/02/2003
Application #:
09292051
Filing Dt:
04/14/1999
Title:
METHOD AND APPARATUS FOR PERFORMING TIMING VERIFICATION OF A CIRCUIT
71
Patent #:
Issue Dt:
12/04/2001
Application #:
09298265
Filing Dt:
04/22/1999
Title:
METHOD FOR ANALYZING MANUFACTURING TEST PATTERN COVERAGE OF CRITICAL DELAY CIRCUIT PATHS
72
Patent #:
Issue Dt:
10/09/2001
Application #:
09299975
Filing Dt:
04/27/1999
Title:
SYSTEM AND METHOD FOR DETECTING NFETS THAT PULL UP TO VDD AND PFETS THAT PULL DOWN TO GROUND
73
Patent #:
Issue Dt:
04/09/2002
Application #:
09300016
Filing Dt:
04/27/1999
Title:
ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR NOMINAL-VOLTAGE POWER SUPPLY OR I/O WITH HIGH-VOLTAGE REFERENCE
74
Patent #:
Issue Dt:
03/12/2002
Application #:
09300129
Filing Dt:
04/27/1999
Title:
ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH HIGH-VOLTAGE REFERENCE
75
Patent #:
Issue Dt:
10/30/2001
Application #:
09300205
Filing Dt:
04/27/1999
Title:
SYSTEM AND METHOD FOR EVALUATING THE LOADING OF A CLOCK DRIVER
76
Patent #:
Issue Dt:
04/30/2002
Application #:
09301830
Filing Dt:
04/29/1999
Title:
FASTER MULTIPLY/ACCUMULATOR
77
Patent #:
Issue Dt:
07/10/2001
Application #:
09311255
Filing Dt:
05/13/1999
Title:
SYSTEM AND METHOD FOR DETECTING FETS THAT ARE SUSCEPTIBLE TO BOOTSTRAPPING
78
Patent #:
Issue Dt:
01/24/2006
Application #:
09311313
Filing Dt:
05/13/1999
Title:
METHOD AND APPARATUS FOR DETERMINING WHETHER AN ELEMENT IN AN INTEGRATED CIRCUIT IS A FEEDBACK ELEMENT
79
Patent #:
Issue Dt:
09/25/2001
Application #:
09311314
Filing Dt:
05/13/1999
Title:
SYSTEM AND METHOD FOR DETECTING THE OUTPUT OF A CLOCK DRIVER
80
Patent #:
Issue Dt:
10/16/2001
Application #:
09318907
Filing Dt:
05/26/1999
Title:
SYSTEM AND METHOD FOR PROPAGATING CLOCK NODES IN A NETLIST OF CIRCUIT DESIGN
81
Patent #:
Issue Dt:
05/14/2002
Application #:
09318988
Filing Dt:
05/26/1999
Title:
METHOD AND APPARATUS FOR DETERMINING THE STRENGTHS AND WEAKNESS OF PATHS IN AN INTEGRATED CIRCUIT
82
Patent #:
Issue Dt:
11/16/2004
Application #:
09336046
Filing Dt:
06/18/1999
Title:
FORMING LINKED LISTS USING CONTENT ADDRESSABLE MEMORY
83
Patent #:
Issue Dt:
05/06/2003
Application #:
09345079
Filing Dt:
06/30/1999
Title:
METHOD AND APPARATUS FOR PRIORITIZING THE ORDER IN WHICH CHECKS ARE PERFORMED ON A NODE IN AN INTEGRATED CIRCUIT
84
Patent #:
Issue Dt:
07/31/2001
Application #:
09349269
Filing Dt:
07/07/1999
Title:
ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH NOMINAL-VOLTAGE REFERENCE
85
Patent #:
Issue Dt:
10/23/2001
Application #:
09358317
Filing Dt:
07/21/1999
Title:
SYSTEM AND METHOD FOR DETECTING MULTIPLEXERS IN A CIRCUIT DESIGN
86
Patent #:
Issue Dt:
12/04/2001
Application #:
09358837
Filing Dt:
07/21/1999
Title:
SYSTEM AND METHOD FOR APPROXIMATING THE COUPLING VOLTAGE NOISE ON A NODE
87
Patent #:
Issue Dt:
09/09/2003
Application #:
09390199
Filing Dt:
09/07/1999
Title:
SUPERSCALAR PROCESSING SYSTEM AND METHOD FOR SELECTIVELY STALLING INSTRUCTIONS WITHIN AN ISSUE GROUP
88
Patent #:
Issue Dt:
11/20/2001
Application #:
09404981
Filing Dt:
09/23/1999
Title:
ELECTROSTATIC DISCHARGE PROTECTION CLAMP FOR HIGH-VOLTAGE POWER SUPPLY OR I/O WITH NOMINAL-OR HIGH-VOLTAGE REFERENCE
89
Patent #:
Issue Dt:
12/04/2001
Application #:
09405935
Filing Dt:
09/27/1999
Title:
HIGH-CURRENT POWER BUS SYSTEM
90
Patent #:
Issue Dt:
03/23/2004
Application #:
09417582
Filing Dt:
10/14/1999
Title:
DETECTING A COMPILER GROUPING ERROR FOR A COMPILED INSTRUCTION GROUP BASED ON ASSOCIATED REGISTERS
91
Patent #:
Issue Dt:
11/18/2003
Application #:
09418286
Filing Dt:
10/14/1999
Title:
SYSTEM AND METHOD FOR DETECTING AN ERRONEOUS DATA HAZARD BETWEEN INSTRUCTIONS OF AN INSTRUCTION GROUP AND RESULTING FROM A COMPILER GROUPING ERROR
92
Patent #:
Issue Dt:
11/28/2000
Application #:
09422813
Filing Dt:
10/21/1999
Title:
BIFURCATED CONTACT WITH A CONNECTING MEMBER THAT CAN ADD REDUNDANT CONTACT POINTS TO SINGLE POINT CONNECTORS
93
Patent #:
Issue Dt:
11/25/2003
Application #:
09447019
Filing Dt:
11/22/1999
Title:
METHOD TO COMPRESS A PIECEWISE LINEAR WAVEFORM SO COMPRESSION ERROR OCCURS ON ONLY ONE SIDE OF THE WAVEFORM
94
Patent #:
Issue Dt:
03/25/2003
Application #:
09448344
Filing Dt:
11/23/1999
Title:
METHOD AND APPARATUS FOR TESTING ERROR DETECTION
95
Patent #:
Issue Dt:
04/27/2004
Application #:
09451499
Filing Dt:
11/30/1999
Title:
SYSTEM AND METHOD FOR TRACKING AND PROCESSING PARALLEL COHERENT MEMORY ACCESSES
96
Patent #:
Issue Dt:
03/09/2004
Application #:
09465175
Filing Dt:
12/17/1999
Title:
OUT OF SEQUENCE REMOVAL AND COMPACTION OF INSTRUCTION QUEUE BY DETERMINING INCLUSIVE INVALID INSTRUCTION COUNT BELOW A ROW AND MOVING INSTRUCTION AND VALIDITY INDICATOR FROM SELECTED ROW TO PRESENT ROW USING DIAGONAL VALUES
97
Patent #:
Issue Dt:
01/13/2004
Application #:
09466503
Filing Dt:
12/17/1999
Title:
METHOD AND APPARATUS FOR GENERATING RANDOM CODE
98
Patent #:
Issue Dt:
07/08/2003
Application #:
09484138
Filing Dt:
01/18/2000
Title:
LOCAL STALL/HAZARD DETECT IN SUPERSCALAR, PIPELINED MICROPROCESSOR
99
Patent #:
Issue Dt:
11/04/2003
Application #:
09490392
Filing Dt:
01/24/2000
Title:
PROCESSING SYSTEM AND METHOD UTILIZING A SCOREBOARD TO DETECT DATA HAZARDS BETWEEN INSTRUCTIONS OF COMPUTER PROGRAMS
100
Patent #:
Issue Dt:
09/16/2003
Application #:
09490395
Filing Dt:
01/24/2000
Title:
SYSTEM AND METHOD FOR PROVIDING PREDICATE DATA TO MULTIPLE PIPELINE STAGES
Assignors
1
Exec Dt:
10/19/2010
2
Exec Dt:
10/19/2010
Assignee
1
416 MAETAN-DONG
YEONGTONG-GU, SUWON-SI
GYEONGGI-DO, KOREA, REPUBLIC OF
Correspondence name and address
ROBERT N. CROUSE
MYERS BIGEL SIBLEY & SAJOVEC
P.O. BOX 37428
RALEIGH, NC 27627

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