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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09496365
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Filing Dt:
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02/02/2000
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Title:
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Method of aligning nanowires
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09496367
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Filing Dt:
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02/02/2000
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Title:
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METHOD AND APPARATUS FOR TESTING MICROARCHITECTURAL FEATURES BY USING TESTS WRITTEN IN MICROCODE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09497533
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Filing Dt:
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02/03/2000
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Title:
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IDENTIFYING EXECUTION READY INSTRUCTIONS AND ALLOCATING PORTS ASSOCIATED WITH EXECUTION RESOURCES IN AN OUT-OF-ORDER PROCESSOR
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09502366
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Filing Dt:
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02/18/2000
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Title:
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METHOD AND APPARATUS FOR VERIFYING THE FINE-GRAINED CORRECTNESS OF A BEHAVIORAL MODEL OF A CENTRAL PROCESSOR UNIT
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09504598
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Filing Dt:
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02/15/2000
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Title:
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Clock wave noise reducer
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09504984
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Filing Dt:
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02/15/2000
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Title:
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APPARATUS AND METHOD FOR INCREASING PERFORMANCE OF MULTIPLIERS UTILIZING REGULAR SUMMATION CIRCUITRY
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09506972
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Filing Dt:
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02/18/2000
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Title:
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APPARATUS AND METHOD FOR SHIFT REGISTER RATE CONTROL OF MICROPROCESSOR INSTRUCTION PREFETCHES
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09507033
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Filing Dt:
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02/18/2000
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Title:
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UNIFIED CACHE PORT CONSOLIDATION
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09507508
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Filing Dt:
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02/18/2000
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Title:
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METHOD TO REDUCE SKEW IN CLOCK SIGNAL DISTRIBUTION USING BALANCED WIRE WIDTHS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09507862
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Filing Dt:
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02/22/2000
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Title:
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Multi-bit comparator
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09510274
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Filing Dt:
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02/21/2000
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Title:
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LINEAR SUMMATION MULTIPLIER ARRAY IMPLEMENTATION FOR BOTH SIGNED AND UNSIGNED MULTIPLICATION
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09510371
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Filing Dt:
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02/22/2000
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Title:
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MANAGEMENT OF UNCOMMITTED REGISTER VALUES DURING RANDOM PROGRAM GENERATION
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09510974
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Filing Dt:
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02/21/2000
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Title:
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RESISTANCE AND CAPACITANCE ESTIMATION
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09514484
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Filing Dt:
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02/28/2000
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Title:
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THREE-DIMENSIONAL INTERCONNECT SYSTEM
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09516989
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Filing Dt:
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03/01/2000
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Title:
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Nanoscale patterning for the formation of extensive wires
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09517369
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Filing Dt:
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03/02/2000
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Title:
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Space-efficient multi-cycle barrel shifter circuit
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09539285
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Filing Dt:
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03/30/2000
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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Protective cover for a printed circuit board electrical connector
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09541253
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Filing Dt:
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04/03/2000
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Title:
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METHOD AND APPARATUS FOR PERMUTING CODE SEQUENCES AND INTIAL CONTEXT OF CODE SEQUENCES FOR IMPROVED ELECTRIC VERIFICATION
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09541423
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Filing Dt:
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04/03/2000
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Title:
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METHOD AND APPARATUS FOR IMPROVING ELECTRICAL VERIFICATION THROUGHPUT VIA COMPARISON OF OPERATING-POINT DIFFERENTIATED TEST RESULTS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09549233
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Filing Dt:
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04/13/2000
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Title:
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SYSTEM AND METHOD FOR PARALLEL TESTING OF IEEE 1149.1 COMPLIANT INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09553737
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Filing Dt:
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04/20/2000
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Title:
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Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09560191
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Filing Dt:
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04/28/2000
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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PROGRAMMABLE DELAY ELEMENTS FOR SOURCE SYNCHRONOUS LINK FUNCTION DESIGN VERIFICATION THROUGH SIMULATION
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09560192
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Filing Dt:
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04/28/2000
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Title:
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A SYSTEM AND METHOD FOR SELECTIVELY RECONFIGURING BYTES BETWEEN TWO PROCESSORS AND A MEMORY BASED ON A CONTROL SIGNAL SENT IN THE ADDRESS BUS
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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09561814
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Filing Dt:
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04/29/2000
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Title:
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DYNAMIC SYSTEM CONFIGURATION FOR FUNCTIONAL DESIGN VERIFICATION
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09562585
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Filing Dt:
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04/29/2000
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Title:
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BACK PRESSURE TEST FIXTURE TO ALLOW PROBING OF INTEGRATED CIRCUIT PACKAGE SIGNALS
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09562596
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Filing Dt:
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04/29/2000
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Title:
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Effective netlength calculation
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09563001
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Filing Dt:
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04/29/2000
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Title:
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MANIPULATION OF HARDWARE CONTROL STATUS REGISTERS VIA BOUNDARY SCAN
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09563006
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Filing Dt:
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04/29/2000
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Title:
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HIGH SPEED DEVICE EMULATION COMPUTER SYSTEM TESTER
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09565017
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Filing Dt:
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05/04/2000
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Title:
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SPECULATIVE PRE-FETCHING ADDITIONAL LINE ON CACHE MISS IF NO REQUEST PENDING IN OUT-OF-ORDER PROCESSOR
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09566765
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Filing Dt:
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05/08/2000
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Title:
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METHOD FOR PERFORMING ELECTRICAL RULES CHECKS ON DIGITAL CIRCUITS WITH MUTUALLY EXCLUSIVE SIGNALS
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09571467
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Filing Dt:
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05/16/2000
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Title:
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METHOD FOR FLASHING ESCD AND VARIABLES INTO A ROM
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09578968
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Filing Dt:
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05/25/2000
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Title:
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Characterization of sense amplifiers
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09586167
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Filing Dt:
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06/01/2000
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Title:
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METHOD FOR TRANSLATING CONDITIONAL EXPRESSIONS FROM A NON-VERILOG HARDWARE DESCRIPTION LANGUAGE TO VERILOG HARDWARE DESCRIPTION LANGUAGE WHILE PRESERVING STRUCTURE SUITABLE FOR LOGIC SYNTHESIS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09595036
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Filing Dt:
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06/15/2000
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Title:
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MOTHOD OF DETERMINING DC MARGIN OF A LATCH
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09614032
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Filing Dt:
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07/11/2000
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Title:
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AUTO-CONTACTOR SYSTEM AND METHOD FOR GENERATING VARIABLE SIZE CONTACTS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09615343
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Filing Dt:
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07/12/2000
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Title:
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METHOD FOR AUTOMATING VALIDATION OF INTEGRATED CIRCUIT TEST LOGIC
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09618405
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Filing Dt:
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07/18/2000
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Title:
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CLOCK SYNCHRONIZATION CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09624790
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Filing Dt:
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07/25/2000
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Title:
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METHOD FOR TRANSLATING CONDITIONAL EXPRESSIONS FROM A NON-VERILOG HARDWARE DESCRIPTION LANGUAGE TO VERILOG HARDWARE DESCRIPTION LANGUAGE WHILE PRESERVING STRUCTURE SUITABLE FOR LOGIC SYNTHESIS
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09625138
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Filing Dt:
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07/25/2000
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Title:
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DESIGN INFORMATION EXCHANGE SYSTEM
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09639613
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Filing Dt:
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08/15/2000
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Title:
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ELECTRICAL RULES CHECKER SYSTEM AND METHOD USING TRI-STATE LOGIC FOR ELECTRICAL RULE CHECKS
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09651948
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Filing Dt:
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08/31/2000
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Title:
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METHOD AND SYSTEM FOR ABSORBING DEFECTS IN HIGH PERFORMANCE MICROPROCESSOR WITH A LARGE N-WAY SET ASSOCIATIVE CACHE
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09652985
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Filing Dt:
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08/31/2000
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Title:
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COHERENT TRANSLATION LOOK-ASIDE BUFFER
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09657552
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Filing Dt:
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09/08/2000
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Title:
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CACHE MANAGEMENT SYSTEM USING HASHING
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09663307
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Filing Dt:
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09/15/2000
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Title:
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APPARATUS AND METHOD FOR FAST MEMORY FAULT ANALYSIS
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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09670855
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Filing Dt:
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09/26/2000
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Title:
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DETERMINISTIC TESTING OF EDGE-TRIGGERED LOGIC
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09672536
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Filing Dt:
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09/28/2000
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Title:
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SYSTEM AND METHOD FOR TESTING A MICROPROCESSOR WITH AN ONBOARD TEST VECTOR GENERATOR
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09723825
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Filing Dt:
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11/28/2000
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Title:
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METHOD FOR ENSURING MAXIMUM BANDWIDTH ON ACCESSES TO STRIDED VECTORS IN A BANK-INTERLEAVED CACHE
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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09727188
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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METHOD AND APPARATUS FOR GENERATING TRANSACTION-BASED STIMULUS FOR SIMULATION OF VLSI CIRCUITS USING EVENT COVERAGE ANALYSIS
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09755719
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Filing Dt:
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01/04/2001
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Publication #:
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Pub Dt:
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07/04/2002
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Title:
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APPARATUS AND METHOD FOR SPECULATIVE PREFETCHING AFTER DATA CACHE MISSES
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09769552
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Filing Dt:
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01/25/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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METHOD AND APPARATUS FOR ADAPTIVELY BYPASSING ONE OR MORE LEVELS OF A CACHE HIERARCHY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09782001
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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METHOD AND SYSTEM FOR ANALYZING A VLSI CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09782233
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Filing Dt:
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02/12/2001
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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METHOD AND SYSTEM FOR FINDING STATIC NAND AND NOR GATES WITHIN A CIRCUIT AND IDENTIFYING THE CONSTITUENT FETS FOR EACH GATE
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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09800939
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Filing Dt:
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03/07/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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Multi-section foldable memory device
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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09811299
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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ACCELEROMETER USING FIELD EMITTER TECHNOLOGY
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09812660
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SYSTEM AND METHOD OF DETERMINING THE NOISE SENSITIVITY CHARACTERIZATION FOR AN UNKNOWN CIRCUIT
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09815844
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Filing Dt:
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03/21/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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FABRICATING A MOLECULAR ELECTRONIC DEVICE HAVING A PROTECTIVE BARRIER LAYER
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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09815913
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Filing Dt:
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03/22/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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SCANNING PROBE BASED LITHOGRAPHIC ALIGNMENT
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09815922
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Filing Dt:
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03/22/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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PASSIVATION LAYER FOR MOLECULAR ELECTRONIC DEVICE FABRICATION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09824427
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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METHOD AND APPARATUS FOR PROGRAMMING A PASTE DISPENSING MACHINE
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09827768
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Filing Dt:
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04/07/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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MEMORY CONTROLLER WITH 1X/MX WRITE CAPABILITY
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09836061
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Filing Dt:
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04/16/2001
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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ELECTRONIC DEVICE SEALED UNDER VACUUM CONTAINING A GETTER AND METHOD OF OPERATION
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09845384
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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METHOD FOR CALCULATING THE P/N RATIO OF A STATIC GATE BASED ON INPUT VOLTAGES
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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09846047
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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SILICON-BASED DIELECTRIC TUNNELING EMITTER
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09846127
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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ANNEALED TUNNELING EMITTER
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09846135
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Filing Dt:
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04/30/2001
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Title:
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BISTABLE MOLECULAR MECHANICAL DEVICES WITH A MIDDLE ROTATING SEGMENT ACTIVATED BY AN ELECTRIC FIELD FOR ELECTRONIC SWITCHING, GATING, AND MEMORY APPLICATIONS
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09872809
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Filing Dt:
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05/31/2001
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Title:
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FAST COMPUTATION OF TRUTH TABLES
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09873874
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Filing Dt:
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06/04/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD AND APPARATUS FOR THE REAL TIME MANIPULATION OF A TEST VECTOR TO ACCESS THE MICROPROCESSOR STATE MACHINE INFORMATION USING THE INTEGRATED DEBUG TRIGGER
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09880158
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Filing Dt:
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06/12/2001
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD FOR FABRICATING TINY FIELD EMITTER TIPS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09880160
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Filing Dt:
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06/12/2001
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD FOR LOW-TEMPERATURE SHARPENING OF SILICON-BASED FIELD EMITTER TIPS
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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09881981
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Filing Dt:
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06/14/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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INTEGRATED FOCUSING EMITTER
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09882933
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Filing Dt:
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06/14/2001
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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FOCUSING LENS FOR ELECTRON EMITTER
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09886355
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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NANOSCALE PATTERNING FOR THE FORMATION OF EXTENSIVE WIRES
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09894143
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Filing Dt:
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06/29/2001
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Title:
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METHODS FOR REDUCING THE NUMBER OF INTERCONNECTS TO THE PIRM MEMORY MODULE
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09896472
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Filing Dt:
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06/29/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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ELECTRICALLY-COUPLED MECHANICAL BAND-PASS FILTER
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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09896480
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Filing Dt:
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06/29/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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APPARATUS AND FABRICATION PROCESS TO REDUCE CROSSTALK IN PIRM MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09900662
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Filing Dt:
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07/06/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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DATA STORAGE DEVICE INCLUDING NANOTUBE ELECTRON SOURCES
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09903927
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Filing Dt:
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07/12/2001
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Title:
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EDGE-TRIGGERED, SELF-RESETTING PULSE GENERATOR
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09909480
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Filing Dt:
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07/20/2001
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Title:
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AUTOMATED CREATION OF POWER DISTRIBUTION GRIDS FOR TILED CELL ARRAYS IN INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09910530
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Filing Dt:
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07/20/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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DATA STORAGE DEVICES WITH WAFER ALIGNMENT COMPENSATION
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09911974
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Filing Dt:
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07/24/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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OPTICALLY PROGRAMMABLE ADDRESS LOGIC FOR SOLID STATE DIODE-BASED MEMORY
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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09915531
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Filing Dt:
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07/27/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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SYSTEM AND METHOD FOR DETERMINING A PLURALITY OF CLOCK DELAY VALUES USING AN OPTIMIZATION ALGORITHM
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09916544
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Filing Dt:
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07/27/2001
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Title:
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METHOD OF AUTOMATICALLY FINDING AND FIXING MIN-TIME VIOLATIONS
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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09917650
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Filing Dt:
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07/31/2001
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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METHOD AND APPARATUS FOR USING AN EXCIMER LASER TO PATTERN ELECTRODEPOSITED PHOTORESIST
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09921847
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Filing Dt:
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08/03/2001
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Title:
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METHOD OF SIMULTANEOUSLY DISPLAYING SCHEMATIC AND TIMING DATA
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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09927204
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Filing Dt:
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08/10/2001
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Title:
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ENABLING VERIFICATION OF A MINIMAL LEVEL SENSITIVE TIMING ABSTRACTION MODEL
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09927220
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Filing Dt:
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08/10/2001
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Title:
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MODELING CIRCUIT ENVIRONMENTAL SENSITIVITY OF A MINIMAL LEVEL SENSITIVE TIMING ABSTRACTION MODEL
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09927856
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Filing Dt:
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08/10/2001
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Title:
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MINIMAL LEVEL SENSITIVE TIMING REPRESENTATIVE OF A CIRCUIT PATH
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09927857
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Filing Dt:
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08/10/2001
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Title:
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IMPROVED LOAD SENSITIVITY MODELING IN A MINIMAL LEVEL SENSITIVE TIMING ABSTRACTION MODEL
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09928161
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Filing Dt:
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08/10/2001
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Title:
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MINIMAL LEVEL SENSITIVE TIMING ABSTRACTION MODEL CAPABLE OF BEING USED IN GENERAL STATIC TIMING ANALYSIS TOOLS
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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09944516
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Filing Dt:
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08/31/2001
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Publication #:
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Pub Dt:
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04/11/2002
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Title:
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ANTI-STARVATION INTERRUPT PROTOCOL
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09947809
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Filing Dt:
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09/05/2001
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Title:
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APPARATUS AND METHOD FOR IMPLEMENTING A MULTIPLEXER
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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09968416
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Filing Dt:
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09/29/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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PROGRESSIVE CPU SLEEP STATE DUTY CYCLE TO LIMIT PEAK POWER OF MULTIPLE COMPUTERS ON SHARED POWER DISTRIBUTION UNIT
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09972052
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Filing Dt:
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10/09/2001
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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SYSTEM FOR IMPROVING CIRCUIT SIMULATIONS BY UTILIZING A SIMPLIFIED CIRCUIT MODEL BASED ON EFFECTIVE CAPACITANCE AND INDUCTANCE VALUES
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09972430
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Filing Dt:
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10/05/2001
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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ENHANCED ELECTRON FIELD EMITTER SPINDT TIP AND METHOD FOR FABRICATING ENHANCED SPINDT TIPS
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09976748
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Filing Dt:
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10/13/2001
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Title:
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FAULT-TOLERANT ADDRESS LOGIC FOR SOLID STATE MEMORY
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09976792
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Filing Dt:
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10/13/2001
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Title:
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FAULT-TOLERANT NEIGHBORHOOD-DISJOINT ADDRESS LOGIC FOR SOLID STATE MEMORY
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09988121
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Filing Dt:
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11/19/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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METHOD FOR EVALUATION OF SCALABLE SYMMETRIC MULTIPLE PROCESSOR CACHE COHERENCY PROTOCOLS AND ALGORITHMS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09990924
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Filing Dt:
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11/13/2001
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Title:
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METHOD OF GENERATING ADDRESS CONFIGURATIONS FOR SOLID STATE MEMORY
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09992907
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Filing Dt:
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11/14/2001
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Publication #:
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Pub Dt:
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03/14/2002
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Title:
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MULTIPURPOSE TEST CHIP INPUT/OUTPUT CIRCUIT
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09994151
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Filing Dt:
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11/26/2001
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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METHOD AND SYSTEM FOR IDENTIFYING FETS IMPLEMENTED IN A PREDEFINED LOGIC EQUATION
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