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Total properties:
56
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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11162622
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Filing Dt:
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09/16/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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INTEGRATED, INTEGRATED CIRCUIT SINGULATION SYSTEM
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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11689317
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Filing Dt:
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03/21/2007
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|
Publication #:
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|
Pub Dt:
|
09/25/2008
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDED STRIP PROTRUSION
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Patent #:
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Issue Dt:
|
01/20/2015
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Application #:
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11744062
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Filing Dt:
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05/03/2007
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|
Publication #:
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|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DEVICE CAVITY
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Patent #:
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Issue Dt:
|
02/17/2015
|
Application #:
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11768790
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Filing Dt:
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06/26/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG DIE
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Patent #:
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Issue Dt:
|
02/17/2015
|
Application #:
|
11936516
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Filing Dt:
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11/07/2007
|
|
Publication #:
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|
Pub Dt:
|
05/07/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ARRAY OF EXTERNAL INTERCONNECTS
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Patent #:
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Issue Dt:
|
02/03/2015
|
Application #:
|
11951958
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Filing Dt:
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12/06/2007
|
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM HOUSING A PLURALITY OF STACKED AND OFFSET INTEGRATED CIRCUITS AND METHOD OF MANUFACTURE THEREFOR
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Patent #:
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Issue Dt:
|
03/17/2015
|
Application #:
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12123995
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Filing Dt:
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05/20/2008
|
|
Publication #:
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|
Pub Dt:
|
11/27/2008
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RELIEF
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Patent #:
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Issue Dt:
|
03/24/2015
|
Application #:
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12273544
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Filing Dt:
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11/19/2008
|
|
Publication #:
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|
Pub Dt:
|
05/20/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT CARRIER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
03/24/2015
|
Application #:
|
12467094
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Filing Dt:
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05/15/2009
|
|
Publication #:
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|
Pub Dt:
|
11/26/2009
| | | | |
|
Title:
|
SEMICONDUCTOR WAFER AND METHOD OF FORMING SACRIFICIAL BUMP PAD FOR WAFER PROBING DURING WAFER SORT TEST
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Patent #:
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Issue Dt:
|
03/31/2015
|
Application #:
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12511012
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Filing Dt:
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07/28/2009
|
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Publication #:
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|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
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Patent #:
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Issue Dt:
|
04/14/2015
|
Application #:
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12719398
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Filing Dt:
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03/08/2010
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|
Publication #:
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|
Pub Dt:
|
06/24/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSED CONDUCTIVE VIAS IN SAW STREETS
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Patent #:
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Issue Dt:
|
02/10/2015
|
Application #:
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12724354
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Filing Dt:
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03/15/2010
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Publication #:
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|
Pub Dt:
|
09/15/2011
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP
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Patent #:
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Issue Dt:
|
03/17/2015
|
Application #:
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12731045
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Filing Dt:
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03/24/2010
|
|
Publication #:
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|
Pub Dt:
|
09/29/2011
| | | | |
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Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
05/12/2015
|
Application #:
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12775170
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Filing Dt:
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05/06/2010
|
|
Publication #:
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|
Pub Dt:
|
09/02/2010
| | | | |
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Title:
|
Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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12964117
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Filing Dt:
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12/09/2010
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|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSES IN SUBSTRATE FOR SAME SIZE OR DIFFERENT SIZED DIE WITH VERTICAL INTEGRATION
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Patent #:
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Issue Dt:
|
05/12/2015
|
Application #:
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12969467
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Filing Dt:
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12/15/2010
|
|
Publication #:
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|
Pub Dt:
|
04/14/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK
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Patent #:
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Issue Dt:
|
03/31/2015
|
Application #:
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13005666
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Filing Dt:
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01/13/2011
|
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Publication #:
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|
Pub Dt:
|
05/05/2011
| | | | |
|
Title:
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System and Method for Directional Grinding on Backside of a Semiconductor Wafer
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Patent #:
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Issue Dt:
|
02/17/2015
|
Application #:
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13023293
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Filing Dt:
|
02/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST
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|
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|
Patent #:
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|
Issue Dt:
|
05/12/2015
|
Application #:
|
13041869
|
Filing Dt:
|
03/07/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT AND METHOD FOR MANUFACTURE THEREOF
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|
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Patent #:
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Issue Dt:
|
05/19/2015
|
Application #:
|
13052816
|
Filing Dt:
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03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A FLIP CHIP AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
03/03/2015
|
Application #:
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13072603
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Filing Dt:
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03/25/2011
|
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Publication #:
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|
Pub Dt:
|
09/27/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13080469
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Filing Dt:
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04/05/2011
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Publication #:
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|
Pub Dt:
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07/28/2011
| | | | |
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Title:
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ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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05/12/2015
|
Application #:
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13090590
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Filing Dt:
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04/20/2011
|
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Publication #:
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Pub Dt:
|
09/01/2011
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE HAVING IPD STRUCTURE WITH SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
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Patent #:
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Issue Dt:
|
02/17/2015
|
Application #:
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13166809
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Filing Dt:
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06/23/2011
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Publication #:
|
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Pub Dt:
|
12/27/2012
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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04/14/2015
|
Application #:
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13167133
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Filing Dt:
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06/23/2011
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Publication #:
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Pub Dt:
|
12/27/2012
| | | | |
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Title:
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Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13167458
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Filing Dt:
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06/23/2011
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|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/03/2015
|
Application #:
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13167631
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Filing Dt:
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06/23/2011
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|
Publication #:
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|
Pub Dt:
|
12/27/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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13170116
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Filing Dt:
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06/27/2011
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
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Patent #:
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02/24/2015
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13181838
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07/13/2011
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Publication #:
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Pub Dt:
|
11/03/2011
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Title:
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Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof
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Patent #:
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03/31/2015
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13231839
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09/13/2011
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Pub Dt:
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03/29/2012
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Title:
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Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
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Patent #:
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02/24/2015
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13244273
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09/23/2011
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Publication #:
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Pub Dt:
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03/28/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
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04/14/2015
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13248312
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09/29/2011
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Pub Dt:
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09/06/2012
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Title:
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Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure
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01/27/2015
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13273537
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10/14/2011
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Pub Dt:
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02/09/2012
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Title:
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Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13284811
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Filing Dt:
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10/28/2011
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Publication #:
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Pub Dt:
|
02/16/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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02/10/2015
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Application #:
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13303019
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11/22/2011
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Publication #:
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Pub Dt:
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05/23/2013
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Title:
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYER OVER SUBSTRATE WITH VENTS TO CHANNEL BUMP MATERIAL AND REDUCE INTERCONNECT VOIDS
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02/24/2015
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13312730
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12/06/2011
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Publication #:
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Pub Dt:
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06/06/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
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03/31/2015
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Application #:
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13327651
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Filing Dt:
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12/15/2011
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PERIMETER ANTIWARPAGE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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02/03/2015
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13349510
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Filing Dt:
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01/12/2012
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
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01/27/2015
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13423262
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03/18/2012
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Pub Dt:
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07/12/2012
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Title:
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Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
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02/10/2015
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13456145
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04/25/2012
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Pub Dt:
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08/16/2012
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATION
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04/07/2015
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13463148
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05/03/2012
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Publication #:
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Pub Dt:
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08/30/2012
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Title:
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INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY
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04/07/2015
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13492687
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06/08/2012
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Pub Dt:
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10/04/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THERMALLY CONDUCTIVE LAYER BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE
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02/24/2015
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13528051
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06/20/2012
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Pub Dt:
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04/11/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF
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05/12/2015
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13563598
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07/31/2012
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Pub Dt:
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11/22/2012
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
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03/17/2015
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13571068
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08/09/2012
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11/29/2012
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Title:
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Semiconductor Device and Method of Forming RF Balun having Reduced Capacitive Coupling and High CMRR
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04/07/2015
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13590197
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08/21/2012
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12/13/2012
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Title:
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PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
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03/24/2015
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13740151
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01/11/2013
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Pub Dt:
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07/17/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
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Issue Dt:
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03/10/2015
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13742580
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01/16/2013
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Pub Dt:
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04/10/2014
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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05/12/2015
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Application #:
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13760187
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02/06/2013
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Pub Dt:
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06/13/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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03/31/2015
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13887180
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05/03/2013
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Pub Dt:
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09/19/2013
| | | | |
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Title:
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Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP
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02/24/2015
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13893616
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05/14/2013
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Pub Dt:
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09/26/2013
| | | | |
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Title:
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METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND
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02/10/2015
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|
13931295
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Filing Dt:
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06/28/2013
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Title:
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METHODS OF FORMING SOLDER BALLS IN SEMICONDUCTOR PACKAGES
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Patent #:
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Issue Dt:
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03/17/2015
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Application #:
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13931397
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Filing Dt:
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06/28/2013
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Publication #:
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Pub Dt:
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01/01/2015
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING LOW PROFILE 3D FAN-OUT PACKAGE
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13934797
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Filing Dt:
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07/03/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHED LEADFRAME AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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14018282
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Filing Dt:
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09/04/2013
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Publication #:
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Pub Dt:
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01/02/2014
| | | | |
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Title:
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SEMICONDUCTOR DEVICE HAVING BALANCED BAND-PASS FILTER IMPLEMENTED WITH LC RESONATORS
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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14043751
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Filing Dt:
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10/01/2013
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Publication #:
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Pub Dt:
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01/30/2014
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Title:
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Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP
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