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Total properties:
25
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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08872530
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Filing Dt:
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06/11/1997
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Title:
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SCHEDULING TECHNIQUES FOR DATA CELLS IN A DATA SWITCH
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08883147
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Filing Dt:
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06/27/1997
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Title:
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METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08924604
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Filing Dt:
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09/05/1997
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Title:
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A WRITEBACK CACHE CELL WITH A DUAL PORTED DIRTY BIT CELL AND METHOD FOR OPERATING SUCH A CACHE CELL
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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08959056
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Filing Dt:
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10/28/1997
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Title:
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ASYNCHRONOUS TRANSFER MODE SWITCHING ARCHITECTURES HAVING CONNECTION BUFFERS
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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08982822
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Filing Dt:
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12/02/1997
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Title:
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CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09059614
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Filing Dt:
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04/13/1998
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Title:
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METHOD AND APPARATUS FOR COMMUNICATING SIGNALS BETWEEN CIRCUITS OPERATING AT DIFFERENT FREQUENCIES
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09059615
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Filing Dt:
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04/13/1998
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Title:
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SYSTEM BUS ARBITRATOR FOR FACILITATING MULTIPLE TRANSACTIONS IN A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09060228
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Filing Dt:
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04/14/1998
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Title:
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ASYNCHRONOUS TRANSFER MODE TRAFFIC SHAPERS
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09062301
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Filing Dt:
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04/17/1998
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Title:
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METHOD AND APPARATUS FOR FORMING A VIRTUAL CIRCUIT
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09126680
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Filing Dt:
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07/30/1998
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Title:
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CIRCUIT, ARCHITECTURE AND METHOD FOR ANALYZING THE OPERATION OF A DIGITAL PROCESSING SYSTEM
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09235148
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Filing Dt:
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01/21/1999
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Title:
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FLOATING-POINT AND INTEGER MULTIPLY-ADD AND MULTIPLY-ACCUMULATE
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09277659
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Filing Dt:
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03/26/1999
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Title:
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APPARATUS AND METHOD FOR OPERATING A DUAL PORT MEMORY CELL
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09281620
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Filing Dt:
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03/30/1999
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Title:
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PROCESSOR WITH MULTIPLE EXECUTION UNITS AND LOCAL AND GLOBAL REGISTER BYPASSES
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09422045
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Filing Dt:
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10/20/1999
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Title:
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METHOD AND APPARATUS FOR VECTOR REGISTER WITH SCALAR VALUES
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09519524
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Filing Dt:
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03/06/2000
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09562055
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Filing Dt:
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05/01/2000
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Title:
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Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09562057
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Filing Dt:
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05/01/2000
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Title:
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Digital programmable delay element
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09562058
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Filing Dt:
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05/01/2000
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Title:
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Reduced line select decoder for a memory array
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09562061
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Filing Dt:
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05/01/2000
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Title:
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METHOD AND SYSTEM FOR REDUCING TAKEN BRANCH PENALTY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09562062
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Filing Dt:
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05/01/2000
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Title:
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SCALABLE REPLACEMENT METHOD AND SYSTEM IN A CACHE MEMORY
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09569543
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Filing Dt:
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05/12/2000
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Title:
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CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09569818
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Filing Dt:
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05/12/2000
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Title:
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SINGLE PHASE EDGE TRIGGER REGISTER
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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09654717
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Filing Dt:
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09/05/2000
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Title:
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A HIGH PERFORMANCE METHOD AND SYSTEM FOR PROCESSING INFORMANTION ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09654759
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Filing Dt:
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09/05/2000
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Title:
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METHOD AND SYSTEM FOR INITIATING COMPUTATION UPOPN UNORDERED RECEIPT OF DATA
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|
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09909316
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Filing Dt:
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07/19/2001
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Title:
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SYSTEM AND METHOD FOR A HIGH SPEED, BI-DIRECTIONAL, ZERO TURNAROUND TIME, PSEUDO DIFFERENTIAL BUS CAPABLE OF SUPPORTING ARBITRARY NUMBER OF DRIVERS AND RECEIVERS
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