Total properties:
10
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09851512
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Filing Dt:
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05/08/2001
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Title:
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CIRCUIT AND METHOD FOR DETERMINING THE OPERATING POINT OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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09888970
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Filing Dt:
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06/25/2001
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Title:
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SYSTEMS AND METHODS FOR A HIGH-SPEED DYNAMIC DATA BUS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10810510
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Filing Dt:
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03/26/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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Semiconductor device with a plurality of ground planes
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11208099
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Filing Dt:
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08/18/2005
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Title:
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PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11480234
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Filing Dt:
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06/30/2006
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Title:
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DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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11853006
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Filing Dt:
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09/10/2007
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Publication #:
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Pub Dt:
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03/13/2008
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Title:
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DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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12346437
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Filing Dt:
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12/30/2008
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Publication #:
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Pub Dt:
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04/30/2009
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Title:
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SEMICONDUCTOR DEVICE WITH A PLURALITY OF GROUND PLANES
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12646540
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Filing Dt:
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12/23/2009
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Publication #:
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Pub Dt:
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04/22/2010
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Title:
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PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
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Patent #:
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Issue Dt:
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08/02/2011
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Application #:
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12730795
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Filing Dt:
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03/24/2010
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Publication #:
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Pub Dt:
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09/09/2010
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Title:
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DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
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Patent #:
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|
Issue Dt:
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06/05/2012
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Application #:
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13093720
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Filing Dt:
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04/25/2011
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Publication #:
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Pub Dt:
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08/18/2011
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Title:
|
PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
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