|
Total properties:
55
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
11163116
|
Filing Dt:
|
10/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
|
Title:
|
ULTRA-THIN WAFER SYSTEM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
11339176
|
Filing Dt:
|
01/23/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
|
Title:
|
PADLESS DIE SUPPORT INTEGRATED CIRCUIT PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
11456554
|
Filing Dt:
|
07/10/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
11465769
|
Filing Dt:
|
08/18/2006
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
|
Title:
|
WORKPIECE DISPLACEMENT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
11536502
|
Filing Dt:
|
09/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2008
| | | | |
|
Title:
|
DUAL-DIE PACKAGE STRUCTURE HAVING DIES EXTERNALLY AND SIMULTANEOUSLY CONNECTED VIA BUMP ELECTRODES AND BOND WIRES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
11673558
|
Filing Dt:
|
02/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMP OVER VIA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
11687357
|
Filing Dt:
|
03/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MULTI-PACKAGE MODULE TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
11773886
|
Filing Dt:
|
07/05/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEX BUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12022296
|
Filing Dt:
|
01/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFER SCALE HEAT SLUG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12051246
|
Filing Dt:
|
03/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
|
Title:
|
FLIP CHIP INTERCONNECTION SYSTEM HAVING SOLDER POSITION CONTROL MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12055665
|
Filing Dt:
|
03/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
|
Title:
|
MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12184219
|
Filing Dt:
|
07/31/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
|
Title:
|
MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12408670
|
Filing Dt:
|
03/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12534029
|
Filing Dt:
|
07/31/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12580933
|
Filing Dt:
|
10/16/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12612603
|
Filing Dt:
|
11/04/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12714431
|
Filing Dt:
|
02/26/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED CONNECTOR AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12723596
|
Filing Dt:
|
03/12/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12775338
|
Filing Dt:
|
05/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12777415
|
Filing Dt:
|
05/11/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
12818750
|
Filing Dt:
|
06/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12823079
|
Filing Dt:
|
06/24/2010
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
12837562
|
Filing Dt:
|
07/16/2010
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12858593
|
Filing Dt:
|
08/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
12891232
|
Filing Dt:
|
09/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13031546
|
Filing Dt:
|
02/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MULTI-LAYERED UBM WITH INTERMEDIATE INSULATING BUFFER LAYER TO REDUCE STRESS FOR SEMICONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13034133
|
Filing Dt:
|
02/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13052590
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13053142
|
Filing Dt:
|
03/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13071433
|
Filing Dt:
|
03/24/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13105814
|
Filing Dt:
|
05/11/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13118214
|
Filing Dt:
|
05/27/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13154308
|
Filing Dt:
|
06/06/2011
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13163643
|
Filing Dt:
|
06/17/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13164114
|
Filing Dt:
|
06/20/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/20/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13167487
|
Filing Dt:
|
06/23/2011
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE OVER SEED LAYER ON CONTACT PAD OF SEMICONDUCTOR DIE WITHOUT UNDERCUTTING SEED LAYER BENEATH INTERCONNECT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13196279
|
Filing Dt:
|
08/02/2011
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13235202
|
Filing Dt:
|
09/16/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13239373
|
Filing Dt:
|
09/21/2011
|
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13311266
|
Filing Dt:
|
12/05/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13315010
|
Filing Dt:
|
12/08/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13326128
|
Filing Dt:
|
12/14/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13326728
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13326891
|
Filing Dt:
|
12/15/2011
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13360549
|
Filing Dt:
|
01/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13417034
|
Filing Dt:
|
03/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13419242
|
Filing Dt:
|
03/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
|
Title:
|
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13426442
|
Filing Dt:
|
03/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13492765
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13523261
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13542120
|
Filing Dt:
|
07/05/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/09/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13559430
|
Filing Dt:
|
07/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
|
Title:
|
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13615308
|
Filing Dt:
|
09/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2013
| | | | |
|
Title:
|
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13679615
|
Filing Dt:
|
11/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13756905
|
Filing Dt:
|
02/01/2013
|
|
Title:
|
SOLDER JOINT FLIP CHIP INTERCONNECTION
|
|
