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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09828553
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Filing Dt:
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04/05/2001
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Title:
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BUFFER CELL INSERTION AND ELECTRONIC DESIGN AUTOMATION
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09833142
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Filing Dt:
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04/11/2001
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Title:
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PROCESS FOR SOLVING ASSIGNMENT PROBLEMS IN INTEGRATED CIRCUIT DESIGNS WITH UNIMODAL OBJECT PENALTY FUNCTIONS AND LINEARLY ORDERED SET OF BOXES
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09836129
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Filing Dt:
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04/16/2001
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Title:
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STATIC TIMING ANALYSIS VALIDATION TOOL FOR ASIC CORES
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09837492
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Filing Dt:
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04/18/2001
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Title:
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CHIP CORE SIZE ESTIMATION
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09841824
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Filing Dt:
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04/25/2001
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Title:
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ASSIGNMENT OF CELL COORDINATES
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09841825
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Filing Dt:
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04/25/2001
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Title:
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TIMING RECOMPUTATION
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09842350
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Filing Dt:
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04/25/2001
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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PARALLELIZATION OF RESYNTHESIS
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09844361
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Filing Dt:
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04/27/2001
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Title:
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DENSITY DRIVEN ASSIGNMENT OF COORDINATES
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09847460
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Filing Dt:
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05/02/2001
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Title:
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CIRCUIT MODELING
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09847838
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Filing Dt:
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04/30/2001
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
Title:
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RTL ANNOTATION TOOL FOR LAYOUT INDUCED NETLIST CHANGES
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09848489
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Filing Dt:
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05/03/2001
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Title:
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METHOD AND APPARATUS FOR INDENTIFYING CAUSES OF POOR SILICON-TO-SIMULATION CORRELATION
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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09849691
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Filing Dt:
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05/04/2001
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Title:
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MINIMAL BENDS CONNECTION MODELS FOR WIRE DENSITY CALCULATION
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09849919
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Filing Dt:
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05/04/2001
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Title:
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PROCESS, APPARATUS AND PROGRAM FOR TRANSFORMING PROGRAM LANGUAGE DESCRIPTION OF AN IC TO AN RTL DESCRIPTION
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09858166
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Filing Dt:
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05/15/2001
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Title:
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NET DELAY OPTIMIZATION WITH RAMPTIME VIOLATION REMOVAL
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Patent #:
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|
Issue Dt:
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07/01/2003
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Application #:
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09859149
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Filing Dt:
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05/15/2001
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Title:
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MODELING DELAYS FOR SMALL NETS IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09862045
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Filing Dt:
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05/21/2001
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Title:
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IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09866137
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
Title:
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SUPPRESSION OF SIDE-LOBE PRINTING BY SHAPE ENGINEERING
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09866661
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Filing Dt:
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05/30/2001
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Title:
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RTL CODE OPTIMIZATION FOR RESOURCE SHARING STRUCTURES
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09871129
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Filing Dt:
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05/31/2001
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Title:
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IC TIMING ANALYSIS WITH KNOWN FALSE PATHS
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09875314
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Filing Dt:
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06/04/2001
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Title:
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METHOD OF CLOCK BUFFER PARTITIONING TO MINIMIZE CLOCK SKEW FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09876736
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Filing Dt:
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06/06/2001
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Title:
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METHOD OF GENERATING AN OPTIMAL CLOCK BUFFER SET FOR MINIMIZING CLOCK SKEW IN BALANCED CLOCK TREES
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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09878499
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Filing Dt:
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06/11/2001
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Title:
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HARD MACRO HAVING AN ANTENNA RULE VIOLATION FREE INPUT/OUTPUT PORTS
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09879297
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Filing Dt:
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06/12/2001
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Title:
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RTL BACK ANNOTATOR
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09879380
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Filing Dt:
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06/12/2001
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Title:
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OPTIMAL CLOCK TIMING SCHEDULE FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09879417
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Filing Dt:
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06/12/2001
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Title:
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METHOD OF ANALYZING STATIC CURRENT TEST VECTORS WITH REDUCED FILE SIZES FOR SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09879506
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Filing Dt:
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06/12/2001
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Title:
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METHOD OF ANALYZING STATIC CURRENT TEST VECTORS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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09879643
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Filing Dt:
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06/12/2001
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Title:
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PROCESS FOR FAST CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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09879664
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Filing Dt:
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06/12/2001
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Title:
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MASK CORRECTION FOR PHOTOLITHOGRAPHIC PROCESSES
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09879841
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Filing Dt:
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06/12/2001
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Title:
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METHOD AND APPARATUS FOR OPTIMIZING THE TIMING OF INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
10/15/2002
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Application #:
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09879845
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Filing Dt:
|
06/12/2001
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Title:
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EPSILON-DISCREPANT SELF-TEST TECHNIQUE
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Patent #:
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|
Issue Dt:
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08/26/2003
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Application #:
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09879846
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Filing Dt:
|
06/12/2001
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Title:
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MASK CORRECTION OPTIMIZATION
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Patent #:
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|
Issue Dt:
|
09/17/2002
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Application #:
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09880607
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Filing Dt:
|
06/12/2001
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Title:
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GENERATING STANDARD DELAY FORMAT FILES WITH CONDITIONAL PATH DELAY FOR DESIGNING INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
08/09/2005
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Application #:
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09880675
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Filing Dt:
|
06/13/2001
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Title:
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SCAN METHOD FOR BUILT-IN-SELF-REPAIR (BISR)
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09882114
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Filing Dt:
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06/15/2001
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Title:
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METHOD OF CONTROL CELL PLACEMENT TO MINIMIZE CONNECTION LENGTH AND CELL DELAY
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Patent #:
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|
Issue Dt:
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06/17/2003
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Application #:
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09882899
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Filing Dt:
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06/15/2001
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Title:
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METHOD FOR REDUCING SIMULATION OVERHEAD FOR EXTERNAL MODELS
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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09883733
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Filing Dt:
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06/18/2001
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Title:
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PSEUDO-RANDOM ONE-TO-ONE CIRCUIT SYNTHESIS
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09885589
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Filing Dt:
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06/19/2001
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Title:
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METHOD IN INTEGRATING CLOCK TREE SYNTHESIS AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09885596
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF GLOBAL PLACEMENT OF CONTROL CELLS AND HARDMAC PINS IN A DATAPATH MACRO FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09885896
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Filing Dt:
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06/20/2001
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Title:
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MODULAR COLLECTION OF SPARE GATES FOR USE IN HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
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Patent #:
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|
Issue Dt:
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07/01/2003
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Application #:
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09892241
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Filing Dt:
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06/26/2001
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Title:
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METHOD OF CONTROL CELL PLACEMENT FOR DATAPATH MACROS IN INTEGRATED CIRCUIT DESIGNS
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Patent #:
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|
Issue Dt:
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03/11/2003
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Application #:
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09894618
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Filing Dt:
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06/27/2001
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Title:
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TIMING DRIVEN INTERCONNECT ANALYSIS
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Patent #:
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|
Issue Dt:
|
08/26/2003
|
Application #:
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09895668
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Filing Dt:
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06/29/2001
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Title:
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METHOD FOR ESTIMATING CELL POROSITY OF HARDMACS
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Patent #:
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|
Issue Dt:
|
09/27/2005
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Application #:
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09916958
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Filing Dt:
|
07/27/2001
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Title:
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DESIGN SYSTEM UPGRADE MIGRATION
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Patent #:
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|
Issue Dt:
|
03/02/2004
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Application #:
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09928471
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Filing Dt:
|
08/13/2001
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Title:
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OPTICAL AND ETCH PROXIMITY CORRECTION
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Patent #:
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|
Issue Dt:
|
12/06/2005
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Application #:
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09934051
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Filing Dt:
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08/21/2001
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Title:
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BZFLASH SUBCIRCUIT TO DYNAMICALLY SUPPLY BZ CODES FOR CONTROLLED IMPEDANCE BUFFER DEVELOPMENT, VERIFICATION AND SYSTEM LEVEL SIMULATIONS
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|
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Patent #:
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|
Issue Dt:
|
07/01/2003
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Application #:
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09941359
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Filing Dt:
|
08/28/2001
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Title:
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OPTIMIZED METAL STACK STRATEGY
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Patent #:
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|
Issue Dt:
|
09/30/2003
|
Application #:
|
09955698
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Filing Dt:
|
09/19/2001
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Title:
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CELL PLACEMENT IN INTEGRATED CIRCUIT CHIPS TO REMOVE CELL OVERLAP, ROW OVERFLOW AND OPTIMAL PLACEMENT OF DUAL HEIGHT CELLS
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
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Application #:
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09964011
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Filing Dt:
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09/26/2001
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Title:
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VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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09964030
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Filing Dt:
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09/26/2001
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Title:
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METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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|
Issue Dt:
|
06/14/2005
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Application #:
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09968008
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Filing Dt:
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10/02/2001
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Title:
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INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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09968009
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Filing Dt:
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10/02/2001
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Title:
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INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Patent #:
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|
Issue Dt:
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09/14/2004
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Application #:
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09972100
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Filing Dt:
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10/05/2001
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Publication #:
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|
Pub Dt:
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05/01/2003
| | | | |
Title:
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SPICE TO VERILOG NETLIST TRANSLATOR AND DESIGN METHODS USING SPICE TO VERILOG AND VERILOG TO SPICE TRANSLATION
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Patent #:
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|
Issue Dt:
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05/23/2006
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Application #:
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09973153
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Filing Dt:
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10/09/2001
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Title:
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WEB BASED OLA MEMORY GENERATOR
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Patent #:
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|
Issue Dt:
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08/16/2005
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Application #:
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09978141
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Filing Dt:
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10/15/2001
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Title:
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AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09986912
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Filing Dt:
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11/13/2001
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Title:
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INTEGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09991574
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Filing Dt:
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11/20/2001
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Title:
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CHANGING CLOCK DELAYS IN AN INTEGRATED CIRCUIT FOR SKEW OPTIMIZATION
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Patent #:
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|
Issue Dt:
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09/07/2004
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Application #:
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09993015
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Filing Dt:
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11/05/2001
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Title:
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METHOD AND APPARATUS FOR AUTOMATIC MARKING OF INTERGRATED CIRCUITS IN WAFER SCALE TESTING
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09994299
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Filing Dt:
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11/26/2001
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Title:
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IDENTIFYING FAULTY PROGRAMMABLE INTERCONNECT RESOURCES OF FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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09997757
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Filing Dt:
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11/30/2001
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Title:
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ENHANCED FAULT COVERAGE
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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09997888
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Filing Dt:
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11/29/2001
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Title:
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DISTRIBUTED DELAY PREDICTION OF MULTI-MILLION GATE DEEP SUB-MICRON ASIC DESIGNS
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10003823
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Filing Dt:
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10/31/2001
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Title:
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VERILOG TO VITAL TRANSLATOR
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Patent #:
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|
Issue Dt:
|
07/27/2004
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Application #:
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10005062
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Filing Dt:
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12/03/2001
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING INCREMENTAL CHANGE TO CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
11/18/2003
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Application #:
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10008089
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Filing Dt:
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11/13/2001
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Title:
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DIRECT TRANSFORMATION OF ENGINEERING CHANGE ORDERS TO SYNTHESIZED IC CHIP DESIGNS
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10011796
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Filing Dt:
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12/05/2001
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Title:
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LONG PATH AT-SPEED TESTING
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10014746
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Filing Dt:
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10/24/2001
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Title:
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GRAPHICAL USER INTERFACE TO INTEGRATE THIRD PARTY TOOLS IN POWER INTEGRITY ANALYSIS
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10015194
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Filing Dt:
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11/20/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A METAMETHODOLOGY
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10021414
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Filing Dt:
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10/30/2001
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Title:
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INTERSCALABLE INTERCONNECT
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Patent #:
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Issue Dt:
|
09/14/2004
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Application #:
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10021619
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Filing Dt:
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10/30/2001
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Title:
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SYSTEM AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10021696
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Filing Dt:
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10/30/2001
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Title:
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SYSTEM AND METHOD FOR OPTIMIZING AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10025123
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Filing Dt:
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12/19/2001
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Title:
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DEVELOPMENT OF HARDMAC TECHNOLOGY FILES (CLF, TECH AND SYNLIB) FOR RTL AND FULL GATE LEVEL NETLISTS
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10027642
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Filing Dt:
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12/20/2001
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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MULTIDIRECTIONAL ROUTER
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10034535
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Filing Dt:
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12/27/2001
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Title:
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METHOD TO DEBUG IKOS METHOD
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10034839
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Filing Dt:
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12/27/2001
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Publication #:
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Pub Dt:
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07/03/2003
| | | | |
Title:
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SYSTEM AND METHOD FOR COEVOLUTIONARY CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10044781
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/10/2003
| | | | |
Title:
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ARCHITECTURE FOR A SEA OF PLATFORMS
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Patent #:
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Issue Dt:
|
11/11/2003
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Application #:
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10045473
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Filing Dt:
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11/08/2001
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Title:
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APPARATUS AND METHOD FOR SIGNAL SKEW CHARACTERIZATION UTILIZING CLOCK DIVISION
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|
|
Patent #:
|
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Issue Dt:
|
06/29/2004
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Application #:
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10059480
|
Filing Dt:
|
01/29/2002
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Publication #:
|
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Pub Dt:
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07/31/2003
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Title:
|
POWER ROUTING WITH OBSTACLES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10072008
|
Filing Dt:
|
02/07/2002
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Publication #:
|
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Pub Dt:
|
08/07/2003
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Title:
|
OVERLAP REMOVER MANAGER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10077066
|
Filing Dt:
|
02/15/2002
|
Title:
|
SYSTEM REAL-TIME ANALYSIS TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10083411
|
Filing Dt:
|
02/27/2002
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
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Title:
|
SYSTEM AND METHOD FOR IDENTIFYING AND ELIMINATING BOTTLENECKS IN INTEGRATED CIRCUIT DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10086232
|
Filing Dt:
|
02/27/2002
|
Publication #:
|
|
Pub Dt:
|
08/28/2003
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Title:
|
METHOD OF REPEATER INSERTION FOR HIERARCHICAL INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
10092195
|
Filing Dt:
|
03/06/2002
|
Title:
|
BLOCKED NET BUFFER INSERTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10097419
|
Filing Dt:
|
03/14/2002
|
Publication #:
|
|
Pub Dt:
|
09/18/2003
| | | | |
Title:
|
OPTICAL PROXIMITY CORRECTION DRIVEN HIERARCHY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10105579
|
Filing Dt:
|
03/25/2002
|
Title:
|
INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND FIELD PROGRAMMABLE GATE ARRAY, AND METHOD OF OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10106432
|
Filing Dt:
|
03/26/2002
|
Title:
|
INTEGRATED CIRCUIT HAVING INTEGRATED PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10106960
|
Filing Dt:
|
03/26/2002
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
SEQUENTIAL TEST PATTERN GENERATION USING CLOCK-CONTROL DESIGN FOR TESTABILITY STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10108286
|
Filing Dt:
|
03/27/2002
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
SYMBOLIC SIMULATION DRIVEN NETLIST SIMPLIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10109113
|
Filing Dt:
|
03/27/2002
|
Publication #:
|
|
Pub Dt:
|
10/02/2003
| | | | |
Title:
|
FLOOR PLAN TESTER FOR INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10119821
|
Filing Dt:
|
04/10/2002
|
Title:
|
INTEGRATED CIRCUIT HAVING A PROGRAMMABLE GATE ARRAY AND A FIELD PROGRAMMABLE GATE ARRAY AND METHODS OF DESIGNING AND MANUFACTURING THE SAME USING TESTING IC BEFORE CONFIGURING FPGA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10125675
|
Filing Dt:
|
04/18/2002
|
Publication #:
|
|
Pub Dt:
|
10/23/2003
| | | | |
Title:
|
INPUT/OUTPUT CHARACTERIZATION CHAIN FOR AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10132360
|
Filing Dt:
|
04/25/2002
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
Title:
|
MULTI-RESOLUTION VITERBI DECODING TECHNIQUE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10135189
|
Filing Dt:
|
04/30/2002
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
Title:
|
Extended instruction sets in a platform architecture
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10135869
|
Filing Dt:
|
04/30/2002
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
Title:
|
COLLABORATIVE INTEGRATION OF HYBRID ELECTRONIC AND MICRO AND SUB-MICRO LEVEL AGGREGATES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2004
|
Application #:
|
10140967
|
Filing Dt:
|
05/08/2002
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
CONTACT RING ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
10143155
|
Filing Dt:
|
05/10/2002
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
REVISION CONTROL FOR DATABASE OF EVOLVED DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10144101
|
Filing Dt:
|
05/09/2002
|
Publication #:
|
|
Pub Dt:
|
11/13/2003
| | | | |
Title:
|
METHOD AND APPARATUS FOR CUSTOM DESIGN IN A STANDARD CELL DESIGN ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10146363
|
Filing Dt:
|
05/15/2002
|
Title:
|
DESIGN AND OPTIMIZATION METHODS FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10151826
|
Filing Dt:
|
05/22/2002
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
Title:
|
CHIP DESIGN METHOD FOR DESIGNING INTEGRATED CIRCUIT CHIPS WITH EMBEDDED MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10153570
|
Filing Dt:
|
05/22/2002
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
Title:
|
SPANNING TREE METHOD FOR K-DIMENSIONAL SPACE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10155620
|
Filing Dt:
|
05/22/2002
|
Publication #:
|
|
Pub Dt:
|
11/27/2003
| | | | |
Title:
|
QUALITY MEASUREMENT OF AN AERIAL IMAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10163208
|
Filing Dt:
|
06/04/2002
|
Title:
|
METHOD AND SYSTEM FOR CHECKING FOR POWER ERRORS IN ASIC DESIGNS
|
|