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Total properties:
80
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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11276645
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Filing Dt:
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03/08/2006
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Publication #:
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Pub Dt:
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09/13/2007
| | | | |
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Title:
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INTEGRATED CIRCUIT LEADED STACKED PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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11462607
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Filing Dt:
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08/04/2006
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Publication #:
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Pub Dt:
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02/07/2008
| | | | |
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Title:
|
STACKABLE MULTI-CHIP PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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11610401
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Filing Dt:
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12/13/2006
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|
Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING A SUPPORT STRUCTURE WITH A RECESS
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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11677487
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Filing Dt:
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02/21/2007
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|
Publication #:
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|
Pub Dt:
|
08/23/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH L-SHAPED LEADFINGERS
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Patent #:
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Issue Dt:
|
05/21/2013
|
Application #:
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11768825
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Filing Dt:
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06/26/2007
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|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
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Title:
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PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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11769520
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Filing Dt:
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06/27/2007
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Publication #:
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|
Pub Dt:
|
01/01/2009
| | | | |
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Title:
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PACKAGING SYSTEM WITH HOLLOW PACKAGE AND METHOD FOR THE SAME
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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11856841
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Filing Dt:
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09/18/2007
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|
Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTERNAL INTERCONNECTS AT HIGH DENSITY
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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11952968
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Filing Dt:
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12/07/2007
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Publication #:
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Pub Dt:
|
06/11/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD
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Patent #:
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Issue Dt:
|
08/06/2013
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Application #:
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11965550
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Filing Dt:
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12/27/2007
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|
Publication #:
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|
Pub Dt:
|
07/02/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTENDED CORNER LEADS
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Patent #:
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Issue Dt:
|
06/04/2013
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Application #:
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12168803
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Filing Dt:
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07/07/2008
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|
Publication #:
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Pub Dt:
|
01/07/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMPED LEAD AND NONBUMPED LEAD
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Patent #:
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Issue Dt:
|
08/20/2013
|
Application #:
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12193540
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Filing Dt:
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08/18/2008
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Publication #:
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Pub Dt:
|
02/18/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM
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Patent #:
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Issue Dt:
|
07/16/2013
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Application #:
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12484099
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
|
10/08/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT SYSTEM HAVING DIFFERENT-SIZE SOLDER BUMPS AND DIFFERENT-SIZE BONDING PADS
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Patent #:
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Issue Dt:
|
04/23/2013
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Application #:
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12484158
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
|
12/16/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A STACK PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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12489122
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Filing Dt:
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06/22/2009
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Publication #:
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Pub Dt:
|
12/23/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/02/2013
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Application #:
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12639997
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Filing Dt:
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12/17/2009
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|
Publication #:
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Pub Dt:
|
06/23/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/30/2013
|
Application #:
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12710359
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Filing Dt:
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02/22/2010
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|
Publication #:
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Pub Dt:
|
08/25/2011
| | | | |
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Title:
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SEMICONDUCTOR PACKAGING SYSTEM WITH AN ALIGNED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/16/2013
|
Application #:
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12716271
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Filing Dt:
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03/02/2010
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|
Publication #:
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|
Pub Dt:
|
09/08/2011
| | | | |
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Title:
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CIRCUIT SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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12717085
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Filing Dt:
|
03/03/2010
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|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEX TAPE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/23/2013
|
Application #:
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12731472
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Filing Dt:
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03/25/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
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|
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Patent #:
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|
Issue Dt:
|
06/18/2013
|
Application #:
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12756067
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Filing Dt:
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04/07/2010
|
|
Publication #:
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|
Pub Dt:
|
08/05/2010
| | | | |
|
Title:
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SOLDER BUMP CONFINEMENT SYSTEM FOR AN INTEGRATED CIRCUIT PACKAGE
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Patent #:
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|
Issue Dt:
|
07/23/2013
|
Application #:
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12775324
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Filing Dt:
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05/06/2010
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Publication #:
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Pub Dt:
|
08/26/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12781772
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Filing Dt:
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05/17/2010
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Publication #:
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Pub Dt:
|
09/09/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT HEAT SPREADER STACKING SYSTEM
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12785951
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Filing Dt:
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05/24/2010
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|
Publication #:
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Pub Dt:
|
11/24/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
06/04/2013
|
Application #:
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12787216
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Filing Dt:
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05/25/2010
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|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/04/2013
|
Application #:
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12789077
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Filing Dt:
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05/27/2010
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Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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12789203
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Filing Dt:
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05/27/2010
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|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
08/06/2013
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Application #:
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12813315
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Filing Dt:
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06/10/2010
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Publication #:
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Pub Dt:
|
09/30/2010
| | | | |
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Title:
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SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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12856288
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Filing Dt:
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08/13/2010
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Publication #:
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Pub Dt:
|
04/07/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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12858163
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Filing Dt:
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08/17/2010
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Publication #:
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Pub Dt:
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02/23/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET CONDUCTIVE PILLARS OVER FIRST SUBSTRATE ALIGNED TO VERTICALLY OFFSET BOT INTERCONNECT SITES FORMED OVER SECOND SUBSTRATE
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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12871401
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Filing Dt:
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08/30/2010
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Publication #:
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Pub Dt:
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12/23/2010
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Title:
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Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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12874787
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Filing Dt:
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09/02/2010
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Publication #:
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Pub Dt:
|
03/08/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE
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Issue Dt:
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05/07/2013
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Application #:
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12874827
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Filing Dt:
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09/02/2010
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Publication #:
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Pub Dt:
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03/08/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
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07/16/2013
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Application #:
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12875496
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Filing Dt:
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09/03/2010
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Publication #:
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Pub Dt:
|
12/23/2010
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF
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Issue Dt:
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05/07/2013
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Application #:
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12880255
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Filing Dt:
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09/13/2010
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Publication #:
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Pub Dt:
|
03/15/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP
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Patent #:
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Issue Dt:
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06/18/2013
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Application #:
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12884134
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Filing Dt:
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09/16/2010
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Publication #:
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Pub Dt:
|
03/22/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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12885137
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Filing Dt:
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09/17/2010
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Publication #:
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Pub Dt:
|
03/22/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12887681
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Filing Dt:
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09/22/2010
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Publication #:
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Pub Dt:
|
03/22/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVAL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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12890338
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Filing Dt:
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09/24/2010
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Publication #:
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Pub Dt:
|
03/29/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12948756
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Filing Dt:
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11/17/2010
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Publication #:
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Pub Dt:
|
05/17/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FOLDABLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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Issue Dt:
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07/02/2013
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Application #:
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12953812
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Filing Dt:
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11/24/2010
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Publication #:
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Pub Dt:
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05/24/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH RECESSES FOR CAPTURING BUMPED SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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12957339
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Filing Dt:
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11/30/2010
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Publication #:
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Pub Dt:
|
05/31/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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12957361
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Filing Dt:
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11/30/2010
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Publication #:
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Pub Dt:
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05/31/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION SUPPORTS AND METHOD OF MANUFACTURE THEREOF
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08/06/2013
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12964617
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12/09/2010
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
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05/21/2013
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12964810
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Filing Dt:
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12/10/2010
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INDUCTOR WITHIN INTERCONNECT LAYER VERTICALLY SEPARATED FROM SEMICONDUCTOR DIE
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08/06/2013
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13017170
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01/31/2011
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Pub Dt:
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05/19/2011
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF
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04/16/2013
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13023244
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02/08/2011
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Pub Dt:
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05/26/2011
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
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06/18/2013
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13035669
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02/25/2011
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Pub Dt:
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08/30/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER AND OPPOSING BUILD-UP INTERCONNECT STRUCTURE WITH CONNECTING CONDUCTIVE TMV FOR ELECTRICAL INTERCONNECT OF FO-WLCSP
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Issue Dt:
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07/09/2013
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Application #:
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13048859
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03/15/2011
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Publication #:
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Pub Dt:
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09/20/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/30/2013
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Application #:
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13053096
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Filing Dt:
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03/21/2011
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Publication #:
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Pub Dt:
|
09/27/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/18/2013
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Application #:
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13070789
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03/24/2011
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Publication #:
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Pub Dt:
|
09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13081011
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Filing Dt:
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04/06/2011
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Publication #:
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Pub Dt:
|
07/28/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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07/02/2013
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Application #:
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13100235
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Filing Dt:
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05/03/2011
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Publication #:
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Pub Dt:
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11/08/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13101657
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Filing Dt:
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05/05/2011
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Publication #:
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Pub Dt:
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08/25/2011
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Title:
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WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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13112717
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Filing Dt:
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05/20/2011
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Publication #:
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Pub Dt:
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09/08/2011
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Title:
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THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13118310
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Filing Dt:
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05/27/2011
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Publication #:
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Pub Dt:
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11/29/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13159095
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
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10/06/2011
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Title:
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METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13162513
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Filing Dt:
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06/16/2011
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Publication #:
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Pub Dt:
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12/20/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13164015
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Filing Dt:
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06/20/2011
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13181290
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Filing Dt:
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07/12/2011
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND AXIS
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13185384
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Filing Dt:
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07/18/2011
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Publication #:
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Pub Dt:
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03/01/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL OVER SEMICONDUCTOR DIE AND CARRIER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13224725
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Filing Dt:
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09/02/2011
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Publication #:
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Pub Dt:
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03/07/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13228226
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Filing Dt:
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09/08/2011
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13228248
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Filing Dt:
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09/08/2011
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13235135
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Filing Dt:
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09/16/2011
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Publication #:
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Pub Dt:
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03/21/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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13269442
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Filing Dt:
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10/07/2011
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Publication #:
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Pub Dt:
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02/02/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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13272034
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Filing Dt:
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10/12/2011
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Publication #:
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Pub Dt:
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02/02/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13295843
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Filing Dt:
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11/14/2011
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECONSTITUTED WAFER WITH LARGER CARRIER TO ACHIEVE MORE EWLB PACKAGES PER WAFER WITH ENCAPSULANT DEPOSITED UNDER TEMPERATURE AND PRESSURE
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13314984
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Filing Dt:
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12/08/2011
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MAKING SINGLE LAYER SUBSTRATE WITH ASYMMETRICAL FIBERS AND REDUCED WARPAGE
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13326173
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Filing Dt:
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12/14/2011
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Publication #:
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Pub Dt:
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06/20/2013
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13333739
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Filing Dt:
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12/21/2011
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Publication #:
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Pub Dt:
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05/09/2013
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13349919
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Filing Dt:
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01/13/2012
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13421770
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Filing Dt:
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03/15/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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Semiconductor Device and Method of Forming With Three-Dimensional Vertically Oriented Integrated Capacitors
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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13423739
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CORE STRUCTURE AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13423832
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Filing Dt:
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03/19/2012
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Publication #:
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Pub Dt:
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07/12/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13476899
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Filing Dt:
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05/21/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
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Patent #:
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Issue Dt:
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07/16/2013
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Application #:
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13556064
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Filing Dt:
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07/23/2012
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Title:
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BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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13556106
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Filing Dt:
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07/23/2012
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Title:
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BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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13558586
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Filing Dt:
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07/26/2012
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Title:
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Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13606631
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Filing Dt:
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09/07/2012
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Publication #:
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Pub Dt:
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12/27/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PARTIALLY-ETCHED CONDUCTIVE LAYER RECESSED WITHIN SUBSTRATE FOR BONDING TO SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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13750975
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Filing Dt:
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01/25/2013
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Title:
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METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
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