|
Total properties:
76
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|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
11164335
|
Filing Dt:
|
11/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
|
Title:
|
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
11276942
|
Filing Dt:
|
03/17/2006
|
|
Publication #:
|
|
Pub Dt:
|
09/20/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
11278008
|
Filing Dt:
|
03/30/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEATSPREADER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
11330930
|
Filing Dt:
|
01/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2007
| | | | |
|
Title:
|
INTER-STACKING MODULE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
11382983
|
Filing Dt:
|
05/12/2006
|
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE TO PACKAGE STACKING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
11769296
|
Filing Dt:
|
06/27/2007
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
CIRCUIT SYSTEM WITH CIRCUIT ELEMENT AND REFERENCE PLANE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
11949255
|
Filing Dt:
|
12/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING INTEGRATED PASSIVE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12057360
|
Filing Dt:
|
03/27/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12059077
|
Filing Dt:
|
03/31/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2008
| | | | |
|
Title:
|
SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12060115
|
Filing Dt:
|
03/31/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR A PACKAGE HAVING MULTIPLE STACKED DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12328764
|
Filing Dt:
|
12/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
WIRE-ON-LEAD PACKAGE SYSTEM HAVING LEADFINGERS POSITIONED BETWEEN PADDLE EXTENSIONS AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12329430
|
Filing Dt:
|
12/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12331341
|
Filing Dt:
|
12/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12410983
|
Filing Dt:
|
03/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12411154
|
Filing Dt:
|
03/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12411310
|
Filing Dt:
|
03/25/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER BETWEEN STACKED SEMICONDUCTOR DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12412315
|
Filing Dt:
|
03/26/2009
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12537824
|
Filing Dt:
|
08/07/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12544578
|
Filing Dt:
|
08/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12557382
|
Filing Dt:
|
09/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIRECTIONAL RF COUPLER WITH IPD FOR ADDITIONAL RF SIGNAL PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12582582
|
Filing Dt:
|
10/20/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12636779
|
Filing Dt:
|
12/13/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12639984
|
Filing Dt:
|
12/16/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12699431
|
Filing Dt:
|
02/03/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12720057
|
Filing Dt:
|
03/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12726342
|
Filing Dt:
|
03/17/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONTACT ON PACKAGE LEADS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12731870
|
Filing Dt:
|
03/25/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12764805
|
Filing Dt:
|
04/21/2010
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
SEMICONDUCTOR METHOD OF FORMING BUMP ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
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|
|
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|
Patent #:
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|
Issue Dt:
|
03/19/2013
|
Application #:
|
12768177
|
Filing Dt:
|
04/27/2010
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
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|
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Patent #:
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|
Issue Dt:
|
01/22/2013
|
Application #:
|
12781751
|
Filing Dt:
|
05/17/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12787973
|
Filing Dt:
|
05/26/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
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|
|
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|
Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
12822504
|
Filing Dt:
|
06/24/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
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|
Patent #:
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|
Issue Dt:
|
03/05/2013
|
Application #:
|
12822659
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Filing Dt:
|
06/24/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
12834176
|
Filing Dt:
|
07/12/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12858602
|
Filing Dt:
|
08/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/26/2013
|
Application #:
|
12875981
|
Filing Dt:
|
09/03/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT
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|
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Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
12875998
|
Filing Dt:
|
09/03/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOUNTING
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|
|
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Patent #:
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|
Issue Dt:
|
01/15/2013
|
Application #:
|
12876013
|
Filing Dt:
|
09/03/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
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Patent #:
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|
Issue Dt:
|
02/19/2013
|
Application #:
|
12882067
|
Filing Dt:
|
09/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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|
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|
Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
12882110
|
Filing Dt:
|
09/14/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
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|
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Patent #:
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|
Issue Dt:
|
03/26/2013
|
Application #:
|
12884073
|
Filing Dt:
|
09/16/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/19/2013
|
Application #:
|
12885831
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Filing Dt:
|
09/20/2010
|
|
Publication #:
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|
Pub Dt:
|
03/22/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL WITH OPENINGS AROUND SEMICONDUCTOR DIE FOR MOLD UNDERFILL USING DISPENSER AND VACUUM ASSIST
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Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
12887811
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Filing Dt:
|
09/22/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE TSV WITH INSULATING ANNULAR RING
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Patent #:
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Issue Dt:
|
02/05/2013
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Application #:
|
12912728
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Filing Dt:
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10/26/2010
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|
Publication #:
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|
Pub Dt:
|
02/17/2011
| | | | |
|
Title:
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DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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|
Issue Dt:
|
02/19/2013
|
Application #:
|
12912730
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Filing Dt:
|
10/26/2010
|
|
Publication #:
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|
Pub Dt:
|
02/17/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
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|
Patent #:
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|
Issue Dt:
|
02/26/2013
|
Application #:
|
12947442
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Filing Dt:
|
11/16/2010
|
|
Publication #:
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|
Pub Dt:
|
05/17/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
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|
Patent #:
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|
Issue Dt:
|
02/12/2013
|
Application #:
|
12950631
|
Filing Dt:
|
11/19/2010
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
12961202
|
Filing Dt:
|
12/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/09/2013
|
Application #:
|
12961494
|
Filing Dt:
|
12/06/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/08/2013
|
Application #:
|
12963934
|
Filing Dt:
|
12/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL INTERCONNECT WITH STRESS RELIEF VOID
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/05/2013
|
Application #:
|
12964644
|
Filing Dt:
|
12/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
|
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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12968266
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12974265
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Filing Dt:
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12/21/2010
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Publication #:
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Pub Dt:
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04/14/2011
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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13006697
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Filing Dt:
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01/14/2011
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Publication #:
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Pub Dt:
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05/12/2011
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Title:
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SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/02/2013
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Application #:
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13053719
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Filing Dt:
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03/22/2011
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13070291
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Filing Dt:
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03/23/2011
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/09/2013
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Application #:
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13070899
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Filing Dt:
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03/24/2011
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13071449
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Filing Dt:
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03/24/2011
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Publication #:
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Pub Dt:
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09/27/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
03/19/2013
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Application #:
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13071760
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Filing Dt:
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03/25/2011
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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Issue Dt:
|
03/05/2013
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Application #:
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13116328
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Filing Dt:
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05/26/2011
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Publication #:
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Pub Dt:
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11/29/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING EWLB PACKAGE CONTAINING STACKED SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIAS FORMED IN ENCAPSULANT AROUND DIE
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Patent #:
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Issue Dt:
|
03/05/2013
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Application #:
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13118955
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Filing Dt:
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05/31/2011
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Publication #:
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Pub Dt:
|
12/06/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
04/02/2013
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Application #:
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13149669
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Filing Dt:
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05/31/2011
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Publication #:
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Pub Dt:
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12/06/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
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|
|
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Patent #:
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|
Issue Dt:
|
04/09/2013
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Application #:
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13160799
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Filing Dt:
|
06/15/2011
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Publication #:
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Pub Dt:
|
10/06/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
02/19/2013
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Application #:
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13161008
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Filing Dt:
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06/15/2011
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Publication #:
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Pub Dt:
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10/06/2011
| | | | |
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Title:
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METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
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Patent #:
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Issue Dt:
|
04/02/2013
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Application #:
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13161368
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Filing Dt:
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06/15/2011
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Publication #:
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Pub Dt:
|
12/20/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
01/15/2013
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Application #:
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13174033
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Filing Dt:
|
06/30/2011
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
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|
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Patent #:
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|
Issue Dt:
|
03/05/2013
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Application #:
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13197122
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Filing Dt:
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08/03/2011
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Publication #:
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Pub Dt:
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11/24/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
01/08/2013
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Application #:
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13209620
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Filing Dt:
|
08/15/2011
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Publication #:
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Pub Dt:
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12/08/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
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|
|
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Patent #:
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|
Issue Dt:
|
02/05/2013
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Application #:
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13211698
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Filing Dt:
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08/17/2011
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Publication #:
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Pub Dt:
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12/08/2011
| | | | |
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Title:
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SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/09/2013
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Application #:
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13215131
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Filing Dt:
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08/22/2011
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Publication #:
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Pub Dt:
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12/08/2011
| | | | |
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Title:
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NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
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|
|
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Patent #:
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|
Issue Dt:
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03/05/2013
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Application #:
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13219374
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Filing Dt:
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08/26/2011
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|
Publication #:
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Pub Dt:
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12/22/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
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|
|
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Patent #:
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|
Issue Dt:
|
02/05/2013
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Application #:
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13223478
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Filing Dt:
|
09/01/2011
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|
Publication #:
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Pub Dt:
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12/22/2011
| | | | |
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Title:
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Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/05/2013
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Application #:
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13233402
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Filing Dt:
|
09/15/2011
|
|
Publication #:
|
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Pub Dt:
|
01/05/2012
| | | | |
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Title:
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METHOD FOR MANUFACTURE OF INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTECTED CONDUCTIVE LAYERS FOR PADS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/19/2013
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Application #:
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13355354
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Filing Dt:
|
01/20/2012
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|
Publication #:
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Pub Dt:
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05/17/2012
| | | | |
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Title:
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METHOD OF FORMING TOP ELECTRODE FOR CAPACITOR AND INTERCONNECTION IN INTEGRATED PASSIVE DEVICE (IPD)
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|
|
|
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Patent #:
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|
Issue Dt:
|
03/05/2013
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Application #:
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13431816
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Filing Dt:
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03/27/2012
|
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Publication #:
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Pub Dt:
|
07/19/2012
| | | | |
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Title:
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METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
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13438155
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Filing Dt:
|
04/03/2012
|
|
Publication #:
|
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Pub Dt:
|
07/26/2012
| | | | |
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Title:
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THERMALLY ENHANCED SEMICONDUCTOR PACKAGE SYSTEM
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