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Total properties:
23
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Patent #:
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Issue Dt:
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08/27/1991
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Application #:
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07505242
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Filing Dt:
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04/05/1990
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Title:
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SEALED SELF ALIGNED CONTACTS USING TWO NITRIDES PROCESS
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Patent #:
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Issue Dt:
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12/24/1991
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Application #:
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07542573
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Filing Dt:
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06/22/1990
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Title:
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TRENCH CAPACITOR FOR LARGE SCALE INTEGRATED MEMORY
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Patent #:
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Issue Dt:
|
04/14/1992
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Application #:
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07559466
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Filing Dt:
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07/30/1990
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Title:
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METHOD FOR CREATING SELF-ALIGNED, NON-PATTERNED CONTACT AREAS & STACKED CAPACITORS USING THE METHOD
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Patent #:
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Issue Dt:
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10/19/1993
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Application #:
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07644902
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Filing Dt:
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01/23/1991
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Title:
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OUTPUT CONTROL CIRCUIT HAVING CONTINUOUSLY VARIABLE DRIVE CURRENT
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Patent #:
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Issue Dt:
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07/28/1992
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Application #:
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07644903
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Filing Dt:
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01/23/1991
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Title:
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CURRENT SUPPLY CIRCUIT FOR DRIVING HIGH CAPACITANCE LOAD IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/26/1992
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Application #:
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07644904
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Filing Dt:
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01/23/1991
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Title:
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REFERENCE GENERATOR FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/10/1992
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Application #:
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07681159
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Filing Dt:
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04/05/1991
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Title:
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STACKED CAPACITOR WITH SIDEWALL INSULATION
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Patent #:
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Issue Dt:
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12/08/1992
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Application #:
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07698841
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Filing Dt:
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05/10/1991
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Title:
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REACTION BARRIER FOR A MULTILAYER STRUCTURE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/01/1993
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Application #:
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07750098
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Filing Dt:
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08/26/1991
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Title:
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SELF SEALED ALIGNED CONTACT INCORPORATING A DOPANT SOURCE
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Patent #:
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Issue Dt:
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03/11/1997
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Application #:
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08267278
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Filing Dt:
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06/28/1994
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Title:
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PROCESS FOR FABRICATING TRANSISTORS USING COMPOSITE NITRIDE STRUCTURE
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Patent #:
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Issue Dt:
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10/15/1996
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Application #:
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08284384
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Filing Dt:
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08/02/1994
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Title:
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CIRCUIT WITH A SINGLE ADDRESS REGISTER THAT AUGMENTS A MEMORY CONTROLLER BY ENABLING CACHE READS AND PAGE-MODE WRITES
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08319289
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Filing Dt:
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10/06/1994
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Title:
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ENHANCED DRAM WITH ALL READS FROM ON-CHIP CACHE AND ALL WRITERS TO MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/24/1998
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Application #:
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08460665
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Filing Dt:
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06/02/1995
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Title:
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ENHANCED DRAM WITH SINGLE ROW SRAM CACHE FOR ALL DEVICE READ OPERATIONS
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08620450
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Filing Dt:
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03/22/1996
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Title:
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EDRAM WITH INTEGRATED GENERATION AND CONTROL OF WRITE ENABLE AND COLUMN LATCH SIGNALS AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
|
05/04/1999
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Application #:
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08840118
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Filing Dt:
|
04/01/1997
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Title:
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FIRST-IN, FIRST-OUT INTEGRATED CIRCUIT MEMORY DEVICE UTILIZING A DYNAMIC RANDOM ACCESS MEMORY ARRAY FOR DATA STORAGE IMPLEMENTED IN CONJUCTION WITH AN ASSOCIATED STATIC RANDOM ACCESS MEMORY CACHE
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08850802
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Filing Dt:
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05/02/1997
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Title:
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ENHANCED SIGNAL PROCESSING RANDOM ACCESS MEMORY DEVICE UTILIZING A DRAM MEMORY ARRAY INTEGRATED WITH AN ASSOCIATED SRAM CACHE AND INTERNAL REFRESH CONTROL
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08888371
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Filing Dt:
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07/03/1997
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Title:
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ENHANCED DRAM WITH EMBEDDED REGISTERS
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09069468
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Filing Dt:
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04/29/1998
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Title:
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TECHNIQUE FOR REDUCING ELEMENT DISABLE FUSE PITCH REQUIREMENTS IN AN INTEGRATED CIRCUIT DEVICE INCORPORATING REPLACEABLE CIRCUIT ELEMENTS
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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09108089
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Filing Dt:
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06/30/1998
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Title:
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EMBEDDED ENHANCED DRAM, AND ASSOCIATED METHOD
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09111822
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Filing Dt:
|
07/08/1998
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Title:
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MULTI-ARRAY MEMORY DEVICE, AND ASSOCIATED METHOD, HAVING SHARED DECODER CIRCUITRY
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Patent #:
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Issue Dt:
|
04/25/2000
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Application #:
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09146726
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Filing Dt:
|
09/03/1998
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Title:
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DYNAMIC RANDOM ACCESS MEMORY WORD LINE BOOST TECHNIQUE EMPLOYING A BOOST-ON-WRITES POLICY
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09178298
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Filing Dt:
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10/23/1998
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Title:
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MULTI-BANK ESDRAM WITH CROSS -COUPLED SRAM CACHE REGISTERS
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|
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Patent #:
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Issue Dt:
|
02/12/2002
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Application #:
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09182994
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Filing Dt:
|
10/30/1998
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Title:
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ENHANCED DRAM WITH EMBEDDED REGISTERS
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