Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021380/0249 | |
| Pages: | 20 |
| | Recorded: | 08/07/2008 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
11
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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11055579
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Filing Dt:
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02/09/2005
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Publication #:
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Pub Dt:
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10/27/2005
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Title:
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HIGH SPEED, DIRECT PATH, STAIR-STEP, ELECTRONIC CONNECTORS WITH IMPROVED SIGNAL INTEGRITY CHARACTERISTICS AND METHODS FOR THEIR MANUFACTURE
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11062112
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Filing Dt:
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02/18/2005
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Title:
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IC PACKAGING INTERPOSER HAVING CONTROLLED IMPEDANCE OR OPTICAL INTERCONNECTIONS AND AN INTEGRAL HEAT SPREADER
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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11092034
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Filing Dt:
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03/28/2005
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Publication #:
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Pub Dt:
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09/29/2005
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Title:
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ACTIVE CONNECTOR
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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11093266
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Filing Dt:
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03/28/2005
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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11097450
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Filing Dt:
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04/01/2005
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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SIGNAL-SEGREGATING CONNECTOR SYSTEM
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11607143
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Filing Dt:
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12/01/2006
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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11933445
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Filing Dt:
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11/01/2007
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Publication #:
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Pub Dt:
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05/07/2009
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Title:
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MEMORY SYSTEMS INCLUDING MEMORY DEVICES COUPLED TOGETHER IN A DAISY-CHAINED ARRANGEMENT
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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11939554
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Filing Dt:
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11/14/2007
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Publication #:
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Pub Dt:
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05/14/2009
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Title:
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CABLED SIGNALING SYSTEM AND COMPONENTS THEREOF
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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11965705
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Filing Dt:
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12/27/2007
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Publication #:
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Pub Dt:
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09/04/2008
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Title:
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MEMORY IC PACKAGE ASSEMBLY HAVING STAIR STEP METAL LAYER AND APERTURES
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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12127195
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Filing Dt:
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05/27/2008
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Publication #:
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Pub Dt:
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11/06/2008
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Title:
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ELECTRICAL INTERCONNECTION DEVICES INCORPORATING REDUNDANT CONTACT POINTS FOR REDUCING CAPACITIVE STUBS AND IMPROVED SIGNAL INTEGRITY
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Patent #:
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Issue Dt:
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07/05/2011
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Application #:
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12128620
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Filing Dt:
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05/29/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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TAPERED DIELECTRIC AND CONDUCTOR STRUCTURES AND APPLICATIONS THEREOF
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Assignee
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| 992 SOUTH DE ANZA BLVD., SUITE 201 |
| SAN JOSE, CALIFORNIA 95129 |
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Correspondence name and address
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RONALD R. SHEA, ESQ.
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2540 COUNTRY HILLS RD., APT. 192
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BREA, CA 92821
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