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Total properties:
70
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12/18/2012
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11163156
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Filing Dt:
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10/07/2005
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Publication #:
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Pub Dt:
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04/12/2007
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Title:
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WAFER LEVEL LASER MARKING SYSTEM FOR ULTRA-THIN WAFERS USING SUPPORT TAPE
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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11462509
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Filing Dt:
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08/04/2006
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Publication #:
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Pub Dt:
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02/07/2008
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FILLED WAFER RECESS
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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11608826
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Filing Dt:
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12/09/2006
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Publication #:
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Pub Dt:
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06/12/2008
| | | | |
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Title:
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STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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11689229
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Filing Dt:
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03/21/2007
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Publication #:
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Pub Dt:
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09/25/2008
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD SUPPORT
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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11773951
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Filing Dt:
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07/05/2007
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Publication #:
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Pub Dt:
|
01/08/2009
| | | | |
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Title:
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SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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11854989
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Filing Dt:
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09/13/2007
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Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS SEPARATED FROM A DIE PADDLE
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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11938371
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Filing Dt:
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11/12/2007
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Publication #:
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Pub Dt:
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05/14/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12035493
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Filing Dt:
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02/22/2008
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Publication #:
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Pub Dt:
|
08/27/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PENETRABLE FILM ADHESIVE
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12037343
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Filing Dt:
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02/26/2008
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG FILM
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Patent #:
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Issue Dt:
|
09/25/2012
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Application #:
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12046430
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Filing Dt:
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03/11/2008
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Publication #:
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Pub Dt:
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09/17/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATION PORT
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12051253
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Filing Dt:
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03/19/2008
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Publication #:
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Pub Dt:
|
09/24/2009
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Title:
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SEMICONDUCTOR DEVICE WITH CROSS-TALK ISOLATION USING M-CAP AND METHOD THEREOF
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12051305
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Filing Dt:
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03/19/2008
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Publication #:
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Pub Dt:
|
09/24/2009
| | | | |
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Title:
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PACKAGE IN PACKAGE SYSTEM INCORPORATING AN INTERNAL STIFFENER COMPONENT
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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12137529
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Filing Dt:
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06/11/2008
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Publication #:
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Pub Dt:
|
12/17/2009
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12172095
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Filing Dt:
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07/11/2008
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Publication #:
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Pub Dt:
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01/14/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHIP ON LEAD
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Patent #:
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Issue Dt:
|
11/13/2012
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Application #:
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12182283
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Filing Dt:
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07/30/2008
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Publication #:
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Pub Dt:
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02/05/2009
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12185061
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Filing Dt:
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08/01/2008
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Publication #:
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Pub Dt:
|
02/04/2010
| | | | |
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Title:
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FAN-IN INTERPOSER ON LEAD FRAME FOR AN INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12188995
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Filing Dt:
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08/08/2008
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
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Title:
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EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12207493
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Filing Dt:
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09/09/2008
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Publication #:
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Pub Dt:
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03/19/2009
| | | | |
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Title:
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MEMORY DEVICE SYSTEM WITH STACKED PACKAGES
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12332318
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Filing Dt:
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12/10/2008
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Publication #:
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Pub Dt:
|
06/10/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CONDUCTIVE VIA-IN-VIA STRUCTURE
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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12362627
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Filing Dt:
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01/30/2009
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Publication #:
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Pub Dt:
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07/23/2009
| | | | |
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Title:
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FLIP CHIP INTERCONNECT SOLDER MASK
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12533943
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Filing Dt:
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07/31/2009
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Publication #:
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Pub Dt:
|
02/03/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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12562874
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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03/24/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH QUAD FLAT NO-LEAD PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12563514
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Filing Dt:
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09/21/2009
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Publication #:
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Pub Dt:
|
03/24/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED VIA AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12618417
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Filing Dt:
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11/13/2009
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Publication #:
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Pub Dt:
|
05/19/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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12629877
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Filing Dt:
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12/02/2009
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Publication #:
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Pub Dt:
|
06/02/2011
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Title:
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PACKAGE SYSTEM WITH A SHIELDED INVERTED INTERNAL STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12635631
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Filing Dt:
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12/10/2009
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Publication #:
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Pub Dt:
|
06/16/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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12636696
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Filing Dt:
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12/11/2009
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Publication #:
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Pub Dt:
|
06/16/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12636703
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Filing Dt:
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12/11/2009
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Publication #:
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Pub Dt:
|
06/16/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12637746
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Filing Dt:
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12/14/2009
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Publication #:
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Pub Dt:
|
06/16/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12641319
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Filing Dt:
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12/17/2009
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Publication #:
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Pub Dt:
|
06/23/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12700114
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Filing Dt:
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02/04/2010
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Publication #:
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Pub Dt:
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06/03/2010
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Title:
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SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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12704366
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Filing Dt:
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02/11/2010
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Publication #:
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Pub Dt:
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06/10/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR FORMING PASSIVE CIRCUIT ELEMENTS WITH THROUGH SILICON VIAS TO BACKSIDE INTERCONNECT STRUCTURES
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Issue Dt:
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11/20/2012
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Application #:
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12711250
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02/23/2010
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Publication #:
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Pub Dt:
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08/25/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELD AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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12724367
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Filing Dt:
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03/15/2010
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Publication #:
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Pub Dt:
|
09/15/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER WITH REDUCED OPENING TO CONTACT PAD OF SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12727229
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Filing Dt:
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03/18/2010
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Publication #:
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Pub Dt:
|
09/22/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12729204
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Filing Dt:
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03/22/2010
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Publication #:
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Pub Dt:
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07/15/2010
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Title:
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SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12748335
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Filing Dt:
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03/26/2010
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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INTEGRATED CIRCUIT SYSTEM WITH STRESS REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12750555
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Filing Dt:
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03/30/2010
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Publication #:
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Pub Dt:
|
10/06/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF BALUN HAVING REDUCED CAPACITIVE COUPLING AND HIGH CMRR
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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12757889
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Filing Dt:
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04/09/2010
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Publication #:
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Pub Dt:
|
08/23/2012
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Title:
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FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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12816225
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Filing Dt:
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06/15/2010
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Publication #:
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Pub Dt:
|
12/15/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12818462
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Filing Dt:
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06/18/2010
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Publication #:
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Pub Dt:
|
12/22/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12821404
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Filing Dt:
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06/23/2010
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Publication #:
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Pub Dt:
|
12/29/2011
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Title:
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SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
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11/13/2012
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12826365
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
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10/21/2010
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Title:
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METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
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11/27/2012
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12853865
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08/10/2010
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Pub Dt:
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02/16/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
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Issue Dt:
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11/06/2012
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Application #:
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12854306
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08/11/2010
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Publication #:
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Pub Dt:
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02/16/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF
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Issue Dt:
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01/01/2013
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Application #:
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12857362
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Filing Dt:
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08/16/2010
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Publication #:
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Pub Dt:
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02/16/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
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Issue Dt:
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10/16/2012
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12868334
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Filing Dt:
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08/25/2010
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Pub Dt:
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03/01/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH DISCRETE SEMICONDUCTOR COMPONENTS MOUNTED UNDER AND OVER SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12878661
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Filing Dt:
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09/09/2010
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Publication #:
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Pub Dt:
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03/15/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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12881983
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Filing Dt:
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09/14/2010
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|
Publication #:
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Pub Dt:
|
03/15/2012
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12905825
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Filing Dt:
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10/15/2010
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Publication #:
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Pub Dt:
|
02/03/2011
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12914895
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Filing Dt:
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10/28/2010
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Publication #:
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Pub Dt:
|
05/03/2012
| | | | |
|
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
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Patent #:
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Issue Dt:
|
12/11/2012
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Application #:
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12916758
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Filing Dt:
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11/01/2010
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|
Publication #:
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Pub Dt:
|
02/24/2011
| | | | |
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Title:
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ULTRA THIN BUMPED WAFER WITH UNDER-FILM
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12942084
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Filing Dt:
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11/09/2010
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Publication #:
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Pub Dt:
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03/03/2011
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Title:
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ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12968257
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONDUCTORS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12973410
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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04/21/2011
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Title:
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WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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13019541
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Filing Dt:
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02/02/2011
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Publication #:
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Pub Dt:
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05/26/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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13028501
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Filing Dt:
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02/16/2011
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Publication #:
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Pub Dt:
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06/09/2011
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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13035617
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Filing Dt:
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02/25/2011
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Publication #:
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Pub Dt:
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08/30/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WAFER LEVEL PACKAGE STRUCTURE USING CONDUCTIVE VIA AND EXPOSED BUMP
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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13043179
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Filing Dt:
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03/08/2011
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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13070219
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Filing Dt:
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03/23/2011
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Publication #:
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Pub Dt:
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09/27/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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13081227
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Filing Dt:
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04/06/2011
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Publication #:
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Pub Dt:
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09/15/2011
| | | | |
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Title:
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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13095680
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Filing Dt:
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04/27/2011
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Publication #:
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Pub Dt:
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08/18/2011
| | | | |
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
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|
|
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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13153286
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Filing Dt:
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06/03/2011
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF USING LEADFRAME BODIES TO FORM OPENINGS THROUGH ENCAPSULANT FOR VERTICAL INTERCONNECT OF SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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13169387
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Filing Dt:
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06/27/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
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Title:
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PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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13235755
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Filing Dt:
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09/19/2011
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Publication #:
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Pub Dt:
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01/12/2012
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A COMPONENT IN AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13237828
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Filing Dt:
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09/20/2011
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Publication #:
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Pub Dt:
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01/12/2012
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Title:
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SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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13241153
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Filing Dt:
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09/22/2011
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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13300088
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Filing Dt:
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11/18/2011
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Publication #:
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Pub Dt:
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03/15/2012
| | | | |
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Title:
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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13350299
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Filing Dt:
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01/13/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
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|
|
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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13423263
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Filing Dt:
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03/18/2012
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Publication #:
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Pub Dt:
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07/12/2012
| | | | |
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
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