Total properties:
595
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Patent #:
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Issue Dt:
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11/11/1997
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Application #:
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08176353
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Filing Dt:
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12/30/1993
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Title:
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INTEGRATED CIRCUIT SCRIBE LINE STRUCTURES AND METHODS FOR MAKING SAME
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Patent #:
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Issue Dt:
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12/12/1995
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Application #:
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08187960
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Filing Dt:
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01/28/1994
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Title:
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SERIAL BUS I/O SYSTEM AND METHOD FOR SERIALIZING INTERRUPT REQUESTS AND DMA REQUESTS IN A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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02/11/1997
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Application #:
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08188373
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Filing Dt:
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01/27/1994
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Title:
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A SINGLE SHARED ROM FOR STORING KEYBOARD MICROCONTROLLER CODE PORTION AND CPU CODE PORTION AND DISABLING ACCESS TO A PORTION WHILE ACCESSING TO THE OTHER
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Patent #:
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Issue Dt:
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04/04/1995
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Application #:
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08188505
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Filing Dt:
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01/28/1994
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Title:
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METHOD FOR CONFIGURING MULTIPLE IDENTICAL SERIAL I/O DEVICES TO UNIQUE ADDRESSES THROUGH A SERIAL BUS
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Patent #:
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Issue Dt:
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09/19/1995
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Application #:
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08190419
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Filing Dt:
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02/02/1994
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Title:
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TAMPER PROTECTION CELL
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Patent #:
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Issue Dt:
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09/05/1995
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Application #:
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08207444
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Filing Dt:
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03/07/1994
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Title:
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METHOD FOR PERFORMING WRITES OF NON-CONTIGUOUS BYTES ON A PCI BUS IN A MINIMUM NUMBER OF WRITE CYCLES
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Patent #:
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Issue Dt:
|
03/07/1995
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Application #:
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08221338
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Filing Dt:
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03/31/1994
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Title:
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MOSFET WITH GATE-PENETRATING HALO IMPLANT
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Patent #:
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Issue Dt:
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04/25/1995
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Application #:
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08221740
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Filing Dt:
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03/31/1994
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Title:
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ANGLED LATERAL POCKET IMPLANTS ON P-TYPE SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/23/1995
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Application #:
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08222139
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Filing Dt:
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03/31/1994
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Title:
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SEMICONDUCTOR-ON-INSULATOR INTEGRATED CIRCUIT WITH SELECTIVELY THINNEDCHANNEL REGION
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Patent #:
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Issue Dt:
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10/24/1995
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Application #:
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08241268
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Filing Dt:
|
05/11/1994
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Title:
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EXTRACTION METHOD FOR AUTOMATED DETERMINATION OF SOURCE/DRAIN RESISTANCE
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Patent #:
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Issue Dt:
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06/17/1997
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Application #:
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08257968
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Filing Dt:
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06/10/1994
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Title:
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BIT ERROR PERFORMANCE OF A FREQUENCY HOPPING, RADIO COMMUNICATION SYSTEM
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Patent #:
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Issue Dt:
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02/13/1996
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Application #:
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08269798
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Filing Dt:
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06/30/1994
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Title:
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ADAPTABLE WAFER PROBE ASSEMBLY FOR TESTING ICS WITH DIFFERENT POWER/GROUND BOND PAD CONFIGURATIONS
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08269804
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Filing Dt:
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06/30/1994
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Title:
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MULTI-LEVEL VROM PROGRAMMING METHOD AND CIRCUIT
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Patent #:
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Issue Dt:
|
02/13/1996
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Application #:
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08272205
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Filing Dt:
|
07/08/1994
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Title:
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METHOD AND APPARATUS FOR SYNTHESIZING DATAPATHS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION
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|
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Patent #:
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|
Issue Dt:
|
12/03/1996
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Application #:
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08274928
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Filing Dt:
|
07/14/1994
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Title:
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CMOS INPUT BUFFER WITH NMOS GATE COUPLED TO VSS THROUGH UNDOPED GATE POLY RESISTOR
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|
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Patent #:
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|
Issue Dt:
|
02/20/1996
|
Application #:
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08275187
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Filing Dt:
|
07/14/1994
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Title:
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AN ABTU-FUSE STRUCTURE FOR REDUCING CONTAMINATION OF THE ANTI-FUSE MATERIAL
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|
|
Patent #:
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|
Issue Dt:
|
06/09/1998
|
Application #:
|
08277090
|
Filing Dt:
|
07/19/1994
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Title:
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DEVICE RELIABILITY OF MOS DEVICES USING SILICON RICH PLASMA OXIDE FILMS
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Patent #:
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|
Issue Dt:
|
12/05/1995
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Application #:
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08286292
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Filing Dt:
|
08/05/1994
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Title:
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METHOD AND APPARATUS FOR MINIMIZING POWER-UP CROWBAR CURRENT IN A RETARGETABLE SRAM MEMORRY SYSTEM
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Patent #:
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|
Issue Dt:
|
04/23/1996
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Application #:
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08286662
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Filing Dt:
|
08/05/1994
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Title:
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METHOD FOR CONTROLLING THE OPERATION OF A COMPUTER IMPLEMENTED APPARATUS TO SELECTIVELY EXECUTE INSTRUCTIONS OF DIFFERENT BIT LENGHTS
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Patent #:
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|
Issue Dt:
|
04/02/1996
|
Application #:
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08294783
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Filing Dt:
|
08/24/1994
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Title:
|
CMOS LOCOS ISOLATION FOR SELF-ALIGNED NPN BJT IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
|
06/04/1996
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Application #:
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08298988
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Filing Dt:
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08/31/1994
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Title:
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MEMORY SUBSYSTEMS HAVING LOOK-AHEAD INSTRUCTION PREFETCH BUFFERS AND INTELLIGENT POSTED WRITE BUFFERS FOR INCREASING THE THROUGHPUT OF DIGITAL COMPUTER SYSTEMS
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Patent #:
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|
Issue Dt:
|
07/09/1996
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Application #:
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08298989
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Filing Dt:
|
08/31/1994
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Title:
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DIGITAL COMPUTER SYSTEM HAVING AN IMPROVED DIRECT-MAPPED CACHE CONTROLLER (WITH FLAG MODIFICATION) FOR A CPU WITH ADDRES PIPELINING AND METHOD THEREFOR
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Patent #:
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|
Issue Dt:
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02/03/1998
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Application #:
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08308328
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Filing Dt:
|
09/19/1994
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Title:
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MULTI-MODE INFRARED INPUT/OUTPUT INTERFACE
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Patent #:
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|
Issue Dt:
|
02/20/1996
|
Application #:
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08314425
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Filing Dt:
|
09/28/1994
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Title:
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METHOD OF MAKING STRUCTURE FOR SUPPRESSION OF FIELD INVERSION CAUSED BY CHARGE BUILD-UP IN THE DIELECTRIC
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Patent #:
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|
Issue Dt:
|
12/17/1996
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Application #:
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08315465
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Filing Dt:
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09/30/1994
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Title:
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ARITHMETIC LOGIC UNIT WITH ZERO SUM PREDICTION
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Patent #:
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|
Issue Dt:
|
09/17/1996
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Application #:
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08316280
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Filing Dt:
|
09/30/1994
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Title:
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FILTER FOR COMPUTER BUS SIGNALS
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Patent #:
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|
Issue Dt:
|
05/14/1996
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Application #:
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08316313
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Filing Dt:
|
09/30/1994
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Title:
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CMOS OUTPUT BUFFER WITH ENHANCED ESD RESISTANCE
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Patent #:
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|
Issue Dt:
|
02/20/1996
|
Application #:
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08335306
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Filing Dt:
|
11/07/1994
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Title:
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CONDUCTIVE VIA STRUCTURE FOR INTEGRATED CIRCUITS AND METHOD FOR MAKING SAME
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|
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Patent #:
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|
Issue Dt:
|
05/21/1996
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Application #:
|
08339928
|
Filing Dt:
|
11/15/1994
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Title:
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DATAPATH SYNTHESIS METHOD AND APPARATUS UTILIZING A STRUCTURED CELL LIBRARY
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|
|
Patent #:
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|
Issue Dt:
|
12/24/1996
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Application #:
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08353022
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Filing Dt:
|
12/09/1994
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Title:
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BUMP FORMATION ON YIELDED SEMICONDUCTOR DIES
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|
|
Patent #:
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|
Issue Dt:
|
07/09/1996
|
Application #:
|
08353463
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Filing Dt:
|
12/09/1994
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Title:
|
HIGH-FREQUENCY COAXIAL INTERFACE TEST FIXTURE
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/1996
|
Application #:
|
08355310
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Filing Dt:
|
12/12/1994
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Title:
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METHOD FOR DETERMINING INSTANCE PLACEMENTS IN CIRCUIT LAYOUTS
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|
|
Patent #:
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|
Issue Dt:
|
02/11/1997
|
Application #:
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08357632
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Filing Dt:
|
12/16/1994
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Title:
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MICROPROCESSOR SYSTEM HAVING INSTRUCTION CACHE WITH RESERVED BRANCH TARGET SECTION
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|
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Patent #:
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|
Issue Dt:
|
06/25/1996
|
Application #:
|
08360880
|
Filing Dt:
|
12/21/1994
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Title:
|
WIREBOND LEAD SYSTEM WITH IMPROVED WIRE SEPARATION
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|
|
Patent #:
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|
Issue Dt:
|
07/16/1996
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Application #:
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08362028
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Filing Dt:
|
12/21/1994
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Title:
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INTEGRATED CIRCUIT FABRICATION USING STATE MACHINE EXTRACTION FROM BEHAVIORAL HARDWARE DESCRIPTION LANGUAGE
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|
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Patent #:
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|
Issue Dt:
|
07/08/1997
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Application #:
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08363064
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Filing Dt:
|
12/21/1994
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Title:
|
MULTIPLICATION/MULTIPLICATION-ACCUMULATION METHOD AND COMPUTING DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
06/11/1996
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Application #:
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08366699
|
Filing Dt:
|
12/30/1994
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Title:
|
METHOD OF PACKING AN IC DIE IN A MOLDED PLASTIC PACKAGE EMPLOYING AN ULTRA-THIN DIE COATING PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
09/10/1996
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Application #:
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08366701
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Filing Dt:
|
12/30/1994
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Title:
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METHOD AND APPARATUS FOR DETERMINING THE TIMING SPECIFICATION OF A DIGITAL CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
03/25/1997
|
Application #:
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08369601
|
Filing Dt:
|
01/06/1995
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Title:
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DUAL PURPOSE SECURITY ARCHITECTURE WITH PROTECTED INTERNAL OPERATING SYSTEM
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|
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Patent #:
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|
Issue Dt:
|
10/29/1996
|
Application #:
|
08369616
|
Filing Dt:
|
01/06/1995
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Title:
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DIGITAL RANDOMIZER FOR ON-CHIP GENERATION AND STORAGE OF RANDOM SELF-PROGRAMMING DATA BLOCK
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|
|
Patent #:
|
|
Issue Dt:
|
02/27/1996
|
Application #:
|
08371724
|
Filing Dt:
|
01/12/1995
|
Title:
|
HIGH-SPEED LOW-POWER CMOS PECL I/O TRANSMITTER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
08372423
|
Filing Dt:
|
01/13/1995
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Title:
|
SYSTEM MARGIN AND CORE TEMPERATURE MONITORING OF AN INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08376491
|
Filing Dt:
|
01/23/1995
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Title:
|
METHOD AND APPARATUS FOR IDENTIFYING FLIP-FLOPS IN HDL DESCRIPTIONS OF CIRCUITS WITHOUT SPECIFIC TEMPLATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/1997
|
Application #:
|
08383334
|
Filing Dt:
|
02/03/1995
|
Title:
|
FREQUENCY ADJUSTABLE PLL CLOCK GENERATION FOR A PLL BASED MICROPROCESSOR BASED ON TEMPERATURE AND/OR OPERATING VOLTAGE AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/1997
|
Application #:
|
08383385
|
Filing Dt:
|
02/03/1995
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Title:
|
APPARATUS FOR MONITORING DISTRIBUTED I/O DEVICE BY PROVIDING A MONITOR IN EACH I/O DEVICE CONTROL FOR GENERATING SIGNALS BASED UPON THE DEVICE STATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08407225
|
Filing Dt:
|
03/20/1995
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Title:
|
SLIP BUFFER FOR SYNCHRONIZING DATA TRANSFER BETWEEN TWO DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/1996
|
Application #:
|
08415182
|
Filing Dt:
|
04/03/1995
|
Title:
|
MULTI-LEVEL ANTIFUSE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08417622
|
Filing Dt:
|
04/06/1995
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Title:
|
METHOD FOR ELIMINATING A FALSE CRITICAL PATH IN A LOGIC CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
01/02/1996
|
Application #:
|
08433829
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Filing Dt:
|
05/04/1995
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Title:
|
FLOATING-POINT PROCESSOR WITH APPARENT-PRECISION BASED SELECTION OF EXECUTION-PRECISION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1997
|
Application #:
|
08434528
|
Filing Dt:
|
05/04/1995
|
Title:
|
METHOD FOR FORMING RELIABLE MOS DEVICES USING SILICON RICH PLASMA OXIDE FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/1996
|
Application #:
|
08443131
|
Filing Dt:
|
05/17/1995
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Title:
|
LOW NOISE LOW VOLTAGE PHASE LOCK LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/1996
|
Application #:
|
08445505
|
Filing Dt:
|
05/22/1995
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Title:
|
CARRY-CHAIN COMPILER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/1997
|
Application #:
|
08448597
|
Filing Dt:
|
07/20/1995
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Title:
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PIPELINED ANALOG TO DIGITAL CONVERTERS AND INTERSTAGE AMPLIFIERS FOR SUCH CONVERTERS
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|
|
Patent #:
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|
Issue Dt:
|
05/05/1998
|
Application #:
|
08471253
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Filing Dt:
|
06/06/1995
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Title:
|
TITANIUM BORIDE AND TITANIUM SILICIDE CONTACT BARRIER FORMATION FOR INTEGRATED CIRCUITS
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|
|
Patent #:
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|
Issue Dt:
|
08/27/1996
|
Application #:
|
08477197
|
Filing Dt:
|
06/07/1995
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Title:
|
METHOD AND APPARATUS FOR ATTENUATING JITTER IN A DIGITAL TRANSMISSION LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/1996
|
Application #:
|
08477311
|
Filing Dt:
|
06/06/1995
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Title:
|
A METHOD FOR REDUCING CONTAMINATION OF ANTI-FUSE MATERIAL IN AN ANTI- FUSE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/1996
|
Application #:
|
08485094
|
Filing Dt:
|
06/07/1995
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Title:
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METHOD AND APPARATUS FOR ATTENUATING JITTER IN A DIGITAL TRANSMISSION LINE
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|
|
Patent #:
|
|
Issue Dt:
|
04/08/1997
|
Application #:
|
08486401
|
Filing Dt:
|
06/05/1995
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Title:
|
DYNAMIC ARBITRATION SYSTEM AND METHOD
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|
|
Patent #:
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|
Issue Dt:
|
07/16/1996
|
Application #:
|
08486405
|
Filing Dt:
|
06/05/1995
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Title:
|
INTEGRATED CIRCUIT TEST JIG
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/1996
|
Application #:
|
08489525
|
Filing Dt:
|
06/12/1995
|
Title:
|
LARGE-TILTED-ANGLE NITROGEN IMPLANT INTO DIELECTRIC REGIONS OVERLAYING SOURCE/DRAIN REGIONS OF A TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08493204
|
Filing Dt:
|
06/20/1995
|
Title:
|
BUILT-IN SELF TEST FOR INTEGRATED CIRCUITS HAVING READ/WRITE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
|
08500386
|
Filing Dt:
|
07/10/1995
|
Title:
|
METHOD AND APPARATUS FOR GUARANTEEING VALID DATA OUTPUT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/1996
|
Application #:
|
08500416
|
Filing Dt:
|
07/10/1995
|
Title:
|
DIGITAL PHASE DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/1996
|
Application #:
|
08502464
|
Filing Dt:
|
07/13/1995
|
Title:
|
MULTI-FINGER INPUT BUFFER WITH TRANSISTOR GATES CAPACITIVELY COUPLED TO GROUND
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1997
|
Application #:
|
08503795
|
Filing Dt:
|
07/18/1995
|
Title:
|
ENCODING ASSERTION AND DE-ASSERTION OF INTERRUPT REQUESTS AND DMA REQUESTS IN A SERIAL BUS I/O SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08504936
|
Filing Dt:
|
07/20/1995
|
Title:
|
INPUT/OUTPUT(I/O) HOLDOFF MECHANISM FOR USE IN A SYSTEM WHERE I/O DEVICE INPUTS ARE FED THROUGH A LATENCY INTRODUCING BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/1996
|
Application #:
|
08504944
|
Filing Dt:
|
07/20/1995
|
Title:
|
SPRING PROBE BGA (BALL GRID ARRAY) CONTACTOR WITH DEVICE STOP AND METHOD THEREFOR
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|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08510076
|
Filing Dt:
|
08/01/1995
|
Title:
|
METHOD AND APPARATUS FOR ENHANCING ACCESS TO A SHARED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/1996
|
Application #:
|
08522856
|
Filing Dt:
|
09/01/1995
|
Title:
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CENTRAL PROCESSING UNIT DATA ENTERING AND INTERROGATING DEVICE AND METHOD THEREFOR
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|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08526119
|
Filing Dt:
|
09/07/1995
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Title:
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STATUS REGISTER WITH ASYNCHRONOUS READ AND RESET AND METHOD FOR PROVIDING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
03/04/1997
|
Application #:
|
08526956
|
Filing Dt:
|
09/12/1995
|
Title:
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HIGH SPEED PHASE ALIGNER WITH JITTER REMOVAL
|
|
|
Patent #:
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|
Issue Dt:
|
10/20/1998
|
Application #:
|
08528660
|
Filing Dt:
|
09/14/1995
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Title:
|
METHOD AND A SYSTEM FOR SPECIFYING AND AUTOMATICALLY ANALYZING MULTIPLE CLOCK TIMING CONSTRAINTS IN A VLSI CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
08530617
|
Filing Dt:
|
09/20/1995
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING AND MAXIMIZING CONCURRENT OPERATIONS IN A SHARED MEMORY SYSTEM WHICH INCLUDES DISPLAY MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08532343
|
Filing Dt:
|
09/19/1995
|
Title:
|
MULTI-PURPOSE KEYBOARD INTERFACE
|
|
|
Patent #:
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|
Issue Dt:
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02/10/1998
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Application #:
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08532936
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Filing Dt:
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09/22/1995
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Title:
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COMPUTING DEVICE HAVING SEMI-DEDICATED HIGH SPEED BUS
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Patent #:
|
|
Issue Dt:
|
07/28/1998
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Application #:
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08542498
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Filing Dt:
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10/13/1995
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Title:
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SYSTEM FOR REDUCING THE POWER CONSUMPTION OF A COMPUTER SYSTEM AND METHOD THEREFOR
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Patent #:
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|
Issue Dt:
|
04/20/1999
|
Application #:
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08542869
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Filing Dt:
|
10/13/1995
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Title:
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METHOD AND A SYSTEM FOR FIXING HOLD TIME VIOLATIONS IN HIERARCHICAL DESIGNS
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Patent #:
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|
Issue Dt:
|
11/24/1998
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Application #:
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08542870
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Filing Dt:
|
10/13/1995
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Title:
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METHOD AND APPARATUS FOR EXTRACTING A CLOCK SIGNAL FROM A RECEIVED SIGNAL
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Patent #:
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|
Issue Dt:
|
06/24/1997
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Application #:
|
08549985
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Filing Dt:
|
10/30/1995
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Title:
|
MULTI-LAYERED, INTEGRATED CIRCUIT PACKAGE HAVING REDUCED PARASITIC NOISE CHARACTERISTICS
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|
Patent #:
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|
Issue Dt:
|
09/09/1997
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Application #:
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08552666
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Filing Dt:
|
11/03/1995
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Title:
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GTL INPUT RECEIVER WITH HYSTERESIS
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|
Patent #:
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|
Issue Dt:
|
01/20/1998
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Application #:
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08553113
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Filing Dt:
|
11/07/1995
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Title:
|
LEADFRAME BALL GRID ARRAY PACKAGE
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|
Patent #:
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|
Issue Dt:
|
12/08/1998
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Application #:
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08554688
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Filing Dt:
|
11/07/1995
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Title:
|
MOLDED LEADFRAME BALL GRID ARRAY
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Patent #:
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|
Issue Dt:
|
03/18/1997
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Application #:
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08567408
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Filing Dt:
|
12/05/1995
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Title:
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DATA PROCESSOR WITH FLEXIBLE REGISTER MAPPING SCHEME
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|
Patent #:
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|
Issue Dt:
|
10/08/1996
|
Application #:
|
08574862
|
Filing Dt:
|
12/19/1995
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Title:
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ADAPTABLE LOAD BOARD ASSEMBLY FOR TESTING ICS WITH DIFFERENT POWER/GROUND BOND PAD AND/OR PIN
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Patent #:
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|
Issue Dt:
|
12/01/1998
|
Application #:
|
08578102
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Filing Dt:
|
12/27/1995
|
Title:
|
WRAPPED-LINE CACHE FOR MICROPROCESSOR SYSTEM
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|
Patent #:
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|
Issue Dt:
|
06/09/1998
|
Application #:
|
08578120
|
Filing Dt:
|
12/26/1995
|
Title:
|
A SYSTEM FOR COMBINING DATA PACKETS FROM MULTIPLE SERIAL DATA STREAMS TO PROVIDE A SINGLE SERIAL DATA OUTPUT AND METHOD THEREFOR
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|
Patent #:
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|
Issue Dt:
|
08/17/1999
|
Application #:
|
08579172
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Filing Dt:
|
12/27/1995
|
Title:
|
ELECTRICALLY CONDUCTIVE INTERCONNECTS FOR INTEGRATED CIRCUITS `
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|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08579489
|
Filing Dt:
|
12/27/1995
|
Title:
|
METHOD FORMING FOCUS/EXPOSURE MATRIX ON A WAFER USING OVERLAPPED EXPOSURE
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|
|
Patent #:
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|
Issue Dt:
|
01/30/2001
|
Application #:
|
08579490
|
Filing Dt:
|
12/27/1995
|
Title:
|
HIGH VOLTAGE DETECT CIRCUIT WITH INCREASED LONG TERM RELIABILITY
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|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08579605
|
Filing Dt:
|
12/26/1995
|
Title:
|
OPTIMIZED STRUCTURES FOR DUMMY FILL MASK DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
08/04/1998
|
Application #:
|
08579824
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Filing Dt:
|
12/28/1995
|
Title:
|
METHODS AND APPARATUS FOR FABRICATING ANTI-FUSE DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08581646
|
Filing Dt:
|
12/28/1995
|
Title:
|
SYSTEM AND METHOD FOR PROGRAMMING VROM LINKS
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|
|
Patent #:
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|
Issue Dt:
|
05/26/1998
|
Application #:
|
08581647
|
Filing Dt:
|
12/28/1995
|
Title:
|
SYSTEM AND METHOD FOR ALTERING BUS SPEED BASED ON BUS UTILIZATION
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|
|
Patent #:
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|
Issue Dt:
|
07/21/1998
|
Application #:
|
08582844
|
Filing Dt:
|
12/29/1995
|
Title:
|
METHOD OF MAKING ANTIFUSE STRUCTURES USING IMPLANTATION OF BOTH NEUTRAL AND DOPANT SPECIES
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|
|
Patent #:
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|
Issue Dt:
|
02/18/1997
|
Application #:
|
08586138
|
Filing Dt:
|
01/16/1996
|
Title:
|
CHARGE PUMP ADDRESSING
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|
|
Patent #:
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|
Issue Dt:
|
04/08/1997
|
Application #:
|
08593898
|
Filing Dt:
|
01/30/1996
|
Title:
|
METHOD FOR IMPROVING THE MANUFACTURABILITY OF THE SPIN-ON GLASS ETCHBACK PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
06/17/1997
|
Application #:
|
08593900
|
Filing Dt:
|
01/30/1996
|
Title:
|
DUMMY UNDERLAYERS FOR IMPROVEMENT IN REMOVAL RATE CONSISTENCY DURING CHEMICAL MECHANICAL POLISHING
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|
|
Patent #:
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|
Issue Dt:
|
07/21/1998
|
Application #:
|
08594874
|
Filing Dt:
|
01/31/1996
|
Title:
|
OPTIMIZED UNDERLAYER STRUCTURES FOR MAINTAINING CHEMICAL MECHANICAL POLISHING REMOVAL RATES
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|
|
Patent #:
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|
Issue Dt:
|
10/13/1998
|
Application #:
|
08601137
|
Filing Dt:
|
02/13/1996
|
Title:
|
METHOD FOR ACHIEVING ACCURATE SOG ETCHBACK SELECTIVITY
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|
|
Patent #:
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|
Issue Dt:
|
12/24/1996
|
Application #:
|
08607372
|
Filing Dt:
|
02/27/1996
|
Title:
|
DYNAMIC DIRECTION LOOK AHEAD READ BUFFER
|
|