Total properties:
595
Page
4
of
6
Pages:
1 2 3 4 5 6
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08837429
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Filing Dt:
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04/17/1997
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Title:
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SYSTEM FOR OPTIMIZING BUS ARBITRATION LATENCY AND METHOD THEREFOR
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Patent #:
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|
Issue Dt:
|
07/28/1998
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Application #:
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08837433
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Filing Dt:
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04/17/1997
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Title:
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DIGITAL POSITIONING JOYSTICK SYSTEM AND METHOD THEREFOR
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Patent #:
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Issue Dt:
|
01/11/2000
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Application #:
|
08838020
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Filing Dt:
|
04/22/1997
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Title:
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APPARATUS FOR AUTOMATED PILLAR LAYOUT AND METHOD FOR IMPLEMENTING SAME
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Patent #:
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Issue Dt:
|
10/05/1999
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Application #:
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08838021
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Filing Dt:
|
04/22/1997
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Title:
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VIRTUAL CONTIGUOUS FIFO HAVING THE PROVISION OF PACKET-DRIVEN AUTOMATIC ENDIAN CONVERSION
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Patent #:
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Issue Dt:
|
02/22/2000
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Application #:
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08844266
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Filing Dt:
|
04/18/1997
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Title:
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COMMUNICATION TIMING CONTROL ARRANGEMENT AND METHOD THEREOF
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Patent #:
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|
Issue Dt:
|
01/18/2000
|
Application #:
|
08846294
|
Filing Dt:
|
04/30/1997
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Title:
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VIRTUAL CONTIGUOUS FIFO FOR COMBINING MULTIPLE DATA PACKETS INTO A SINGLE CONTIGUOUS STREAM
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Patent #:
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Issue Dt:
|
04/06/1999
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Application #:
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08846655
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Filing Dt:
|
05/01/1997
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Title:
|
SAMPLE RATE CONVERSION BETWEEN ASYNCHRONOUS DIGITAL SYSTEMS
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|
|
Patent #:
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|
Issue Dt:
|
08/18/1998
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Application #:
|
08846833
|
Filing Dt:
|
04/30/1997
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Title:
|
ETCHING METALS USING CHLORINE GAS AND HYDROCHLORIC GAS IN DE-IONIZED WATER
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Patent #:
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|
Issue Dt:
|
01/05/1999
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Application #:
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08848541
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Filing Dt:
|
04/28/1997
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Title:
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A WAFER WITH A FOCUS/EXPOSURE MATRIX
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|
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Patent #:
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|
Issue Dt:
|
07/13/1999
|
Application #:
|
08851842
|
Filing Dt:
|
05/06/1997
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Title:
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METHOD FOR ACHIEVING LOW CAPACITANCE DIFFUSION PATTERN FILLING
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|
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Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
08853288
|
Filing Dt:
|
05/09/1997
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Title:
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SYSTEM AND METHOD FOR SHARING PHYSICAL MEMORY AMONG DISTINCT COMPUTER ENVIRONMENTS
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Patent #:
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|
Issue Dt:
|
07/13/1999
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Application #:
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08853355
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Filing Dt:
|
05/08/1997
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Title:
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DEVICE AND A METHOD FOR MONITORING A SYSTEM CLOCK SIGNAL
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Patent #:
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|
Issue Dt:
|
03/09/1999
|
Application #:
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08856949
|
Filing Dt:
|
05/15/1997
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Title:
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MOISTURE BARRIER GAP FILL STRUCTURE AND METHOD FOR MAKING THE SAME
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Patent #:
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|
Issue Dt:
|
08/08/2000
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Application #:
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08857477
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Filing Dt:
|
05/15/1997
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Title:
|
METHOD AND APPARATUS FOR PERFORMING A SECURE OPERATION
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|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08858147
|
Filing Dt:
|
05/15/1997
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Title:
|
SINGLE EVENT UPSET DETECTION AND PROTECTION IN AN INTEGRATED CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
12/26/2000
|
Application #:
|
08859168
|
Filing Dt:
|
05/20/1997
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Title:
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MEMORY SPACE COMPRESSION TECHNIQUE FOR A SEQUENTIALLY ACCESSIBLE MEMORY
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|
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Patent #:
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|
Issue Dt:
|
06/08/1999
|
Application #:
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08861941
|
Filing Dt:
|
05/22/1997
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Title:
|
METHOD AND SYSTEM FOR TUNGSTEN CHEMICAL MECHANICAL POLISHING FOR UNPLANARIZED DIELECTRIC SURFACES
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08864237
|
Filing Dt:
|
05/28/1997
|
Title:
|
WELL-BASED METHOD FOR ACHIEVING LOW CAPACITANCE DIFFUSION PATTERN FILLING
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|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08868853
|
Filing Dt:
|
06/04/1997
|
Title:
|
BUILT-IN SELF TEST FUNCTIONAL SYSTEM BLOCK FOR UTOPIA INTERFACE
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|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
08868886
|
Filing Dt:
|
06/04/1997
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Title:
|
SECURE CRYPTOGRAPHIC MULTI-EXPONENTIATION METHOD AND COPROCESSOR SUBSYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08870167
|
Filing Dt:
|
06/06/1997
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Title:
|
PIN-REDUCED LOW POWER KEYBOARD SCANNER
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|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08873099
|
Filing Dt:
|
06/10/1997
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Title:
|
MULTI-MASTER PCI BUS SYSTEM WITHIN A SINGLE INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08876389
|
Filing Dt:
|
06/16/1997
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Title:
|
TECHNIQUE TO PRODUCE CAVITY-UP HBGA PACKAGES
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|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08877095
|
Filing Dt:
|
06/17/1997
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Title:
|
PLASMA ASH FOR SILICON SURFACE PREPARATION
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|
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Patent #:
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|
Issue Dt:
|
07/13/1999
|
Application #:
|
08879578
|
Filing Dt:
|
06/20/1997
|
Title:
|
METHOD OF MAKING A CUSTOM LASER CONDUCTOR LINKAGE FOR THE INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08880580
|
Filing Dt:
|
06/23/1997
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Title:
|
OXIDE ETCH STOP TECHNIQUES FOR UNIFORM DAMASCENE TRENCH DEPTH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08881614
|
Filing Dt:
|
06/25/1997
|
Title:
|
METHOD OF FORMING A VIA STRUCTURE INCLUDING CVD TUNGSTEN SILICDE BARRIER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08883403
|
Filing Dt:
|
06/26/1997
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Title:
|
LOW POWER PROGRAMMABLE FUSE STRUCTURES SAME
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|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
08885052
|
Filing Dt:
|
06/30/1997
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Title:
|
DIGITAL INTEGRATED CIRCUIT BUFFER DIGITAL DEVICE AND METHOD FOR BUFFERING DATA
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|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08885302
|
Filing Dt:
|
06/30/1997
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Title:
|
SELF-ALIGNED SILICIDATION TECHNIQUE TO INDEPENDENTLY FORM SILICIDES OF DIFFERENT THICKNESS ON A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
08885378
|
Filing Dt:
|
06/30/1997
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Title:
|
SELECTIVE EXCLUSION OF SILICIDE FORMATION TO MAKE POLYSILICON RESISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
08885740
|
Filing Dt:
|
06/30/1997
|
Title:
|
METALLIZATION TECHNIQUE FOR GATE ELECTRODES AND LOCAL INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08886170
|
Filing Dt:
|
06/30/1997
|
Title:
|
SELF-ALIGNED PROCESSING OF SEMICONDUCTOR DEVICE FEATURES
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
08887459
|
Filing Dt:
|
07/02/1997
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Title:
|
LOW VOLTAGE CMOS PROCESS AND DEVICE WITH INDIVIDUALLY ADJUSTABLE LDD SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08890127
|
Filing Dt:
|
07/09/1997
|
Title:
|
FIRST-IN-FIRST-OUT (FIFO) CONTROLLER FOR BUFFERING DATA BETWEEN SYSTEMS WHICH ARE ASYNCHRONOUS AND FREE OF FALSE FLAGS AND INTERNAL METASTABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08890910
|
Filing Dt:
|
07/10/1997
|
Title:
|
INTEGRATED CIRCUIT SCRIBE LINE STRUCTURES AND METHODS FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08892302
|
Filing Dt:
|
07/14/1997
|
Title:
|
RECEIVER SAMPLE RATE FREQUENCY ADJUSTMENT FOR SAMPLE RATE CONVERSION BETWEEN ASYNCHRONOUS DIGITAL SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
08892565
|
Filing Dt:
|
07/14/1997
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Title:
|
ELASTIC BUFFER TO INTERFACE DIGITAL SYSTEMS
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|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08897216
|
Filing Dt:
|
07/14/1997
|
Title:
|
SMART RETRY MECHANISM TO PROGRAM THE RETRY LATENCY OF A PCI INITIATOR AGENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08899531
|
Filing Dt:
|
07/24/1997
|
Title:
|
METHODS FOR MAKING SEMICONDUCTOR DEVICES HAVING AIR DIELECTRIC INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08901465
|
Filing Dt:
|
07/28/1997
|
Title:
|
METHOD AND SYSTEM FOR ACCURATE TEMPORAL DETERMINATION OF REAL-TIME EVENTS WITHIN A UNIVERSAL SERIAL BUS SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08902091
|
Filing Dt:
|
07/29/1997
|
Title:
|
PERSONAL HANDYPHONE SYSTEM HARDWARE CHECKING OF BROADCASTING RECEPTION INDICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
08902202
|
Filing Dt:
|
07/29/1997
|
Title:
|
HARDWARE PCH CHECKING FOR PERSONAL HANDYPHONE SYSTEM PORTABLE STATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08904918
|
Filing Dt:
|
08/01/1997
|
Title:
|
REGISTER-BASED PROGRAMMABLE POST-SILICON SYSTEM TO PATCH AND DYNAMICALLY MODIFY THE BEHAVIOR OF SYNCHRONOUS STATE MACHINES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08905234
|
Filing Dt:
|
08/01/1997
|
Title:
|
FABRICATION METHOD FOR SUB-HALF MICRON CMOS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08906482
|
Filing Dt:
|
08/05/1997
|
Title:
|
METHOD FOR ACHIEVING ACCURATE SOG ETCHBACK SELECTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
08907099
|
Filing Dt:
|
08/06/1997
|
Title:
|
SILICON-ENRICHED SHALLOW TRENCH OXIDE FOR REDUCED RECESS DURING LDD SPACER ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08910590
|
Filing Dt:
|
07/25/1997
|
Title:
|
SELECTING A TEST DATA INPUT BUS TO SUPPLY TEST DATA TO LOGICAL BLOCKS WITHIN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
08915543
|
Filing Dt:
|
08/13/1997
|
Title:
|
A METHOD AND SYSTEM FOR USING DATA DECOMPRESSION ON COMPRESSED SOFTWARE STORED IN NON-VOLATILE MEMORY OF AN EMBEDDED COMPUTER SYSTEM TO YIELD DECOMPRESSED SOFTWARE INCLUDING INITIALIZED VARIABLES FOR A RUNTIME ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08918596
|
Filing Dt:
|
08/23/1997
|
Title:
|
LOGIC IMPLEMENTATION OF CONTROL SIGNALS FOR ON-SILICON MULTI-MASTER DATA TRANSFER BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
08921361
|
Filing Dt:
|
08/29/1997
|
Title:
|
METHOD AND SYSTEM FOR FLOORPLANNING A CIRCUIT DESIGN AT A HIGH LEVEL OF ABSTRACTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/1998
|
Application #:
|
08922953
|
Filing Dt:
|
09/03/1997
|
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING AN AIR DIELECTRIC AND DIELECTRIC SUPPORT PILLARS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08923106
|
Filing Dt:
|
09/03/1997
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING ALIGNMENT FOR METAL MASKING IN CONJUCTION WITH OXIDE AND TUNGSTEN CMP
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1999
|
Application #:
|
08925040
|
Filing Dt:
|
09/08/1997
|
Title:
|
PHOTO ALIGNMENT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08927479
|
Filing Dt:
|
09/11/1997
|
Title:
|
SELF-ALIGNED SILICIDATION STRUCTURE AND METHOD OF FORMATION THEREOF `
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
08932310
|
Filing Dt:
|
09/17/1997
|
Title:
|
COUNTER BASED RINGER INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08932651
|
Filing Dt:
|
09/18/1997
|
Title:
|
METHOD FOR MAINTAINING BUS OWNERSHIP WHILE BUS MASTERING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08934449
|
Filing Dt:
|
09/19/1997
|
Title:
|
FLOATING-POINT PROCESSOR WITH OPERAND-FORMAT PRECISION GREATER THAN EXECUTION PRECISION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08934831
|
Filing Dt:
|
09/22/1997
|
Title:
|
METHODS OF FORMING PAIRS OF TRANSISTORS, AND METHODS OF FORMING PAIRS OF TRANSISTORS HAVING DIFFERENT VOLTAGE TOLERANCES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08941803
|
Filing Dt:
|
10/03/1997
|
Title:
|
STANDARD CELL RING OSCILLATOR OF A NON-DETERMINISTIC RANDOMIZER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
08941898
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHODS AND APPARATUS FOR DESIGN RULE CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
08942108
|
Filing Dt:
|
09/30/1997
|
Title:
|
PERSONAL HANDY-PHONE SYSTEM WIRELESS LOCAL LOOPS AND METHODS OF TRANSMITTING INFORMATION WITHIN PERSONAL HANDY-PHONE SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08943891
|
Filing Dt:
|
10/03/1997
|
Title:
|
METHOD FOR FORMING VIA CONTACT HOLE IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
08944463
|
Filing Dt:
|
10/06/1997
|
Title:
|
SHAPED ETCH-FRONT FOR SELF-ALIGNED CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08947378
|
Filing Dt:
|
10/08/1997
|
Title:
|
SECURE MEMORY MANAGEMENT UNIT WHICH UTILIZES A SYSTEM PROCESSOR TO PERFORM PAGE SWAPPING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2006
|
Application #:
|
08948189
|
Filing Dt:
|
10/09/1997
|
Title:
|
MICROPROCESSOR WITH PROGRAMMABLE INSTRUCTION TRAP FOR DEIMPLEMENTING INSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08951396
|
Filing Dt:
|
10/16/1997
|
Title:
|
METHOD FOR MEASURING THE EFFECTIVENESS OF OPTICAL PROXIMITY CORRECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08955012
|
Filing Dt:
|
10/20/1997
|
Title:
|
DIFFERENTIAL MOS CURRENT-MODE LOGIC CIRCUIT HAVING HIGH GAIN AND FAST SPEED
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
08957671
|
Filing Dt:
|
10/24/1997
|
Title:
|
STANDARD CELL POWER-ON-RESET CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08958052
|
Filing Dt:
|
10/27/1997
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Title:
|
HOST PROCESSOR AND COPROCESSOR ARRANGEMENT FOR PROCESSING PLATFORM-INDEPENDENT CODE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08958530
|
Filing Dt:
|
10/27/1997
|
Title:
|
SCAN TESTABLE CIRCUIT ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08960184
|
Filing Dt:
|
10/29/1997
|
Title:
|
PRIORITY ARBITRATION SYSTEM PROVIDING LOW LATENCY AND GUARANTEED ACCESS FOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08961648
|
Filing Dt:
|
10/31/1997
|
Title:
|
HIGH SPEED DIFFERENTIAL DRIVER CIRCUITRY AND METHODS FOR IMPLEMENTING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08962466
|
Filing Dt:
|
10/31/1997
|
Title:
|
PHASE-LOCKED LOOP HAVING IMPROVED LOCKING TIMES AND A METHOD OF OPERATION THEREFORE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08962593
|
Filing Dt:
|
10/31/1997
|
Title:
|
SCALABLE N-PORT MEMORY STRUCTURES
|
|
|
Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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08962597
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Filing Dt:
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10/31/1997
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Title:
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CUSTOM IC HARDWARE MODELING USING STANDARD ICS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08968555
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Filing Dt:
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11/12/1997
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Title:
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METHOD AND SYSTEM FOR LATCHING AN ADDRESS FOR ACCESSING SYNCHRONOUS RANDOM ACCESS MEMORY USING A SINGLE ADDRESS STATUS SIGNAL CONTROL LINE
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08969567
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Filing Dt:
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11/13/1997
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Title:
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BI-LAYER PROGRAMMABLE RESISTOR MEMORY
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Patent #:
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Issue Dt:
|
11/30/1999
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Application #:
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08972771
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Filing Dt:
|
11/18/1997
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Title:
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VCO HAVING A LOW SENSITIVITY TO NOISE ON THE POWER SUPPLY
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Patent #:
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Issue Dt:
|
10/26/1999
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Application #:
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08972838
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Filing Dt:
|
11/18/1997
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Title:
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VCO CIRCUIT HAVING LOW GAIN VARIATION OVER DIFFERENT PROCESSES AND OPERATING TEMPERATURES AND HAVING LOW POWER SUPPLY NOISE SENSITIVITY
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Patent #:
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Issue Dt:
|
05/22/2001
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Application #:
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08974043
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Filing Dt:
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11/19/1997
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Title:
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METHOD AND APPARATUS FOR DETECTING MISALIGNMENTS IN INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
|
04/10/2001
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Application #:
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08974131
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Filing Dt:
|
11/19/1997
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Title:
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METHOD FOR INTRODUCING HARMONICS INTO AN AUDIO STREAM FOR IMPROVING THREE DIMENSIONAL AUDIO POSITIONING
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Patent #:
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Issue Dt:
|
09/14/1999
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Application #:
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08974203
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Filing Dt:
|
11/19/1997
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Title:
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METHOD FOR ALIGNMENT USING MULTIPLE WAVELENGTHS OF LIGHT
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Patent #:
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Issue Dt:
|
05/30/2000
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Application #:
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08976190
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Filing Dt:
|
11/21/1997
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Title:
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HIGH-SPEED LOGIC EMBODIED DIFFERENTIAL DYNAMIC CMOS TRUE SINGLE PHASE CLOCK LATCHES AND FLIP-FLOPS WITH SINGLE TRANSISTOR CLOCK LATCHES
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Patent #:
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Issue Dt:
|
02/15/2000
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Application #:
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08976564
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Filing Dt:
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11/24/1997
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Title:
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APPARATUS FOR EQUALIZING SIGNAL PARAMETERS IN FLIP CHIP REDISTRIBUTION LAYERS
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Patent #:
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|
Issue Dt:
|
12/05/2000
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Application #:
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08978074
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Filing Dt:
|
11/25/1997
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Title:
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INTEGRATED CIRCUIT INCLUDING PATCHING CIRCUITRY TO BYPASS PORTIONS OF AN INTERNALLY FLAWED READ ONLY MEMORY AND A METHOD THEREFORE
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|
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Patent #:
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|
Issue Dt:
|
05/30/2000
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Application #:
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08978333
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Filing Dt:
|
11/25/1997
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Title:
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AUDIO-RECORDING REMOTE CONTROL AND METHOD THEREFOR
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|
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Patent #:
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Issue Dt:
|
04/10/2001
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Application #:
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08984483
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Filing Dt:
|
12/01/1997
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Title:
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VIA ALIGNMENT ETCH COMPLETION AND CRITICAL DIMENSION MEASUREMENT METHOD AND STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
03/14/2000
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Application #:
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08989833
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Filing Dt:
|
12/12/1997
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Title:
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INPUT SLOPE TIMING ANALYSIS AND NON-LINEAR DELAY TABLE OPTIMIZATION
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|
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Patent #:
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Issue Dt:
|
07/18/2000
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Application #:
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08993244
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Filing Dt:
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12/18/1997
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Title:
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LOW POWER CLOCK SOUARER WITH TIGHT DUTY CYCLE CONTROL
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|
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Patent #:
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|
Issue Dt:
|
07/25/2000
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Application #:
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08995651
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Filing Dt:
|
12/22/1997
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Title:
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METHOD FOR MAKING RELIABLE INTERCONNECT STRUCTURES
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|
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Patent #:
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|
Issue Dt:
|
03/07/2000
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Application #:
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08996836
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Filing Dt:
|
12/23/1997
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Title:
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SIO2 WIRE BOND INSULATION IN SEMICONDUCTOR ASSEMBLIES
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|
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Patent #:
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Issue Dt:
|
04/04/2000
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Application #:
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08997295
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Filing Dt:
|
12/23/1997
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Title:
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OXIDE WIRE BOND INSULATION IN SEMICONDUCT0R ASEMBLIES
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|
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Patent #:
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|
Issue Dt:
|
10/15/2002
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Application #:
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08999266
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Filing Dt:
|
12/29/1997
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Title:
|
DATA COMMUNICATION DEVICES, PERSONAL HANDY-PHONE SYSTEM BASE STATIONS, AND METHODS OF COMMUNICATING DATA
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|
Patent #:
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Issue Dt:
|
06/27/2000
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Application #:
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09002103
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Filing Dt:
|
12/30/1997
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Title:
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METHOD FOR PREVENTING MICROMASKING IN SHALLOW TRENCH ISOLATION PROCESS ETCHING
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|
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Patent #:
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|
Issue Dt:
|
05/09/2000
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Application #:
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09005244
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Filing Dt:
|
01/12/1998
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Title:
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INTEGRATED ETCH PROCESS FOR POLYSILICON/METAL GATE
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|
Patent #:
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|
Issue Dt:
|
06/13/2000
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Application #:
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09005358
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Filing Dt:
|
01/09/1998
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Title:
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SINGLE ADDRESS QUEUE FOR HANDLING MULTIPLE PRIORITY REQUESTS
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|
Patent #:
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|
Issue Dt:
|
09/03/2002
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Application #:
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09006926
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Filing Dt:
|
01/14/1998
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Title:
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METHOD FOR FORMING STRAPLESS ANTI-FUSE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09007117
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Filing Dt:
|
01/14/1998
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Title:
|
METHOD OF SELECTIVELY APPLYING DOPANTS TO AN INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITHOUT USING A MASK
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09007673
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Filing Dt:
|
01/15/1998
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Publication #:
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Pub Dt:
|
12/13/2001
| | | | |
Title:
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SEMICONDUCTOR PROCESSING METHODS AND STRUCTURES FOR DETERMINING ALIGNMENT DURING SEMICONDUCTOR WAFER PROCESSING
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|