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Reel/Frame:033102/0270   Pages: 90
Recorded: 06/06/2014
Attorney Dkt #:040981-0072
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 3258
Page 11 of 33
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
Patent #:
Issue Dt:
05/29/2001
Application #:
09115464
Filing Dt:
07/14/1998
Title:
POLY ROUTING FOR CHIP INTERCONNECTS WITH MINIMAL IMPACT ON CHIP PERFORMANCE
2
Patent #:
Issue Dt:
07/10/2001
Application #:
09118232
Filing Dt:
07/17/1998
Title:
SELF-ALIGNED FUSE STRUCTURE AND METHOD WITH HEAT SINK
3
Patent #:
Issue Dt:
09/18/2001
Application #:
09118387
Filing Dt:
07/17/1998
Title:
AUDIO/VIDEO DEVICE INCLUDING AN INFRARED TRANSCEIVER FOR TRANSMITTING AND RECEIVING CONFIGURATION DATA, AND METHOD FOR CONFIGURING SAME
4
Patent #:
Issue Dt:
05/09/2000
Application #:
09118602
Filing Dt:
07/17/1998
Title:
SELF-ALIGNED FUSE STRUCTURE AND METHOD WITH ANTI-REFLECTIVE COATING
5
Patent #:
Issue Dt:
01/30/2001
Application #:
09118661
Filing Dt:
07/16/1998
Title:
METAL LAYER ASSIGNMENT
6
Patent #:
Issue Dt:
08/29/2000
Application #:
09118737
Filing Dt:
07/17/1998
Title:
APPARATUS FOR GATHERING AND DISPLAYING INFORMATION ABOUT THE CONTENTS OF ONE OR MORE OPTICAL DISKS STORED WITHIN AN OPTICAL DISK PLAYER
7
Patent #:
Issue Dt:
09/11/2001
Application #:
09119829
Filing Dt:
07/21/1998
Publication #:
Pub Dt:
06/28/2001
Title:
CIRCUIT AND METHOD FOR INITIATING EXCEPTION ROUTINES USING IMPLICIT EXCEPTION CHECKING
8
Patent #:
Issue Dt:
02/13/2001
Application #:
09119990
Filing Dt:
07/21/1998
Title:
SYSTEM FOR INITIATING EXCEPTION ROUTINE IN RESPONSE TO MEMORY ACCESS EXCEPTION BY STORING EXCEPTION INFORMATION AND EXCEPTION BIT WITHIN ARCHITECTURED REGISTER
9
Patent #:
Issue Dt:
06/25/2002
Application #:
09120617
Filing Dt:
07/22/1998
Title:
WIRE ROUTING OPTIMIZATION
10
Patent #:
Issue Dt:
08/29/2000
Application #:
09120622
Filing Dt:
07/22/1998
Title:
TEMPERATURE-COMPENSATED REFERENCE VOLTAGE GENERATOR AND METHOD THEREFOR
11
Patent #:
Issue Dt:
12/05/2000
Application #:
09121283
Filing Dt:
07/22/1998
Title:
ISOLATION TRENCH IN SEMICONDUCTOR SUBSTRATE WITH NITROGEN-CONTAINING BARRIER REGION, AND PROCESS FOR FORMING SAME
12
Patent #:
Issue Dt:
12/05/2000
Application #:
09122335
Filing Dt:
07/24/1998
Title:
LASER MARKING OF SEMICONDUCTOR WAFER SUBSTRATE WHILE INHIBITING ADHERENCE TO SUBSTRATE SURFACE OF PARTICLES GENERATED DURING LASER MARKING
13
Patent #:
Issue Dt:
05/23/2000
Application #:
09124494
Filing Dt:
07/29/1998
Title:
TESTER-COMPATIBLE TIMING TRANSLATION SYSTEM AND METHOD USING TIME-SET PARTNERING
14
Patent #:
Issue Dt:
08/15/2000
Application #:
09126118
Filing Dt:
07/30/1998
Title:
ATAPI STATE MACHINE CONTROLLED BY A MICROCONTROLLER FOR INTERFACING A DVD CONTROLLER WITH AN ATA HOST BUS
15
Patent #:
Issue Dt:
02/27/2001
Application #:
09126125
Filing Dt:
07/30/1998
Title:
DEMODULATION OF DVD CODEWORDS USING DEPENECY-SORTED TABLES FOR DUPLICATE/DEPENDENT AND UNIQUE/NON-DEPENDENT MAPPINGS
16
Patent #:
Issue Dt:
06/05/2001
Application #:
09127486
Filing Dt:
07/31/1998
Title:
UNIVERSAL I/O PAD STRUCTURE FOR IN-LINE OR STAGGERED WIRE BONDING OR ARRAYED FLIP-CHIP ASSEMBLY
17
Patent #:
Issue Dt:
12/31/2002
Application #:
09128730
Filing Dt:
08/04/1998
Title:
DUAL-PRIME MOTION ESTIMATION ENGINE
18
Patent #:
Issue Dt:
06/27/2000
Application #:
09131921
Filing Dt:
08/10/1998
Title:
METHOD OF DETECTING A POLISHING ENDPOINT LAYER OF A SEMICONDUCTOR WAFER WHICH INCLUDES A NON-REACTIVE REPORTING SPECIE
19
Patent #:
Issue Dt:
09/12/2000
Application #:
09136239
Filing Dt:
08/18/1998
Title:
SYSTEM AND METHOD TO PROTECT SDRAM DATA DURING WARM RESETS
20
Patent #:
Issue Dt:
07/17/2001
Application #:
09143083
Filing Dt:
08/28/1998
Title:
BACKSIDE FAILURE ANALYSIS CAPABLE INTEGRATED CIRCUIT PACKAGING
21
Patent #:
Issue Dt:
03/18/2003
Application #:
09143086
Filing Dt:
08/28/1998
Title:
METHOD AND APPARATUS FOR DATA SHARING BETWEEN TWO DIFFERENT BLOCKS IN AN INTEGRATED CIRCUIT
22
Patent #:
Issue Dt:
01/30/2001
Application #:
09143195
Filing Dt:
08/31/1998
Title:
SOFTWARE TEST CASE CLIENT/SERVER SYSTEM AND METHOD
23
Patent #:
Issue Dt:
01/22/2002
Application #:
09148028
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR CHEMICAL-MECHANICAL POLISHING
24
Patent #:
Issue Dt:
06/19/2001
Application #:
09150220
Filing Dt:
09/09/1998
Title:
METHOD AND APPARATUS FOR REMOVING PARTICLES FROM A SEMICONDUCTOR WAFER
25
Patent #:
Issue Dt:
09/05/2000
Application #:
09150778
Filing Dt:
09/10/1998
Title:
COMBINATIONAL LOGIC FOR COMPARING N-BIT WIDE BUSES
26
Patent #:
Issue Dt:
04/09/2002
Application #:
09151228
Filing Dt:
09/10/1998
Title:
SIMULATION FORMAT CREATION SYSTEM AND METHOD
27
Patent #:
Issue Dt:
08/07/2001
Application #:
09151900
Filing Dt:
09/11/1998
Title:
EXTRACTOR AND SCHEMATIC VIEWER FOR A DESIGN REPRESENTATION, AND ASSOCIATED METHOD
28
Patent #:
Issue Dt:
03/06/2001
Application #:
09153949
Filing Dt:
09/16/1998
Title:
ERROR-TOLERANT TARGET-SECTOR SEARCH USING PREVIOUS N SECTOR ID FOR HIGH-SPEED CD
29
Patent #:
Issue Dt:
10/16/2001
Application #:
09156432
Filing Dt:
09/18/1998
Title:
METHOD AND APPARATUS FOR PROCESSING DATA PACKETS
30
Patent #:
Issue Dt:
10/01/2002
Application #:
09157214
Filing Dt:
09/18/1998
Title:
IO POWER MANAGEMENT: SYNCHRONOUSLY REGULATED OUTPUT SKEW
31
Patent #:
Issue Dt:
04/03/2001
Application #:
09162407
Filing Dt:
09/29/1998
Title:
SEMICONDUCTOR DEVICE WITH A [AIR OF TRANSISTORS HAVING DUAL WORK FUNCTION GATE ELECTRODES
32
Patent #:
Issue Dt:
05/30/2000
Application #:
09163623
Filing Dt:
09/30/1998
Title:
REDUCTION OF SILICON DEFECT INDUCED FAILURES AS A RESULT OF IMPLANTS IN CMOS AND OTHER INTEGRATED CIRCUITS
33
Patent #:
Issue Dt:
08/29/2000
Application #:
09163683
Filing Dt:
09/30/1998
Title:
RADIALLY-INCREASING CORE POWER BUS GRID ARCHITECTURE
34
Patent #:
Issue Dt:
03/19/2002
Application #:
09163835
Filing Dt:
09/30/1998
Title:
BUFFER CONTROLLER
35
Patent #:
Issue Dt:
09/02/2003
Application #:
09164069
Filing Dt:
09/30/1998
Title:
METHOD FOR COMPOSING A DIELECTRIC LAYER WITHIN AN INTERCONNECT STRUCTURE OF A MULTILAYER SEMICONDUCTOR DEVICE
36
Patent #:
Issue Dt:
12/03/2002
Application #:
09164245
Filing Dt:
09/30/1998
Title:
TRANSMISSION CIRCUIT HAVING AN INDUCTOR-ASSISTED TERMINATION
37
Patent #:
Issue Dt:
05/01/2001
Application #:
09164864
Filing Dt:
10/01/1998
Title:
SYSTEM AND METHOD FOR GAIN COMPENSATION FOR THERMAL ASPERITY CORRECTION
38
Patent #:
Issue Dt:
05/22/2001
Application #:
09164867
Filing Dt:
10/01/1998
Title:
METHOD AND APPARATUS FOR REDUCING RINGING USING FEED FORWARD COMPENSATION
39
Patent #:
Issue Dt:
05/13/2003
Application #:
09165182
Filing Dt:
10/01/1998
Title:
METHOD AND APPARTUS FOR ADAPTING THE BOOST OF A READ CHANNEL FILTER
40
Patent #:
Issue Dt:
08/01/2000
Application #:
09166012
Filing Dt:
10/02/1998
Title:
OMNIBUS CLOSED CAPTIONING DECODER FOR ENCODED VIDEO
41
Patent #:
Issue Dt:
06/12/2001
Application #:
09166262
Filing Dt:
10/05/1998
Title:
INTEGRATED CIRCUIT WITH UNIFIED MEMORY SYSTEM AND DUAL BUS ARCHITECTURE
42
Patent #:
Issue Dt:
05/07/2002
Application #:
09166304
Filing Dt:
10/05/1998
Title:
METHOD AND CIRCUIT FOR TESTING DEVICES WITH SERIAL DATA LINKS
43
Patent #:
Issue Dt:
05/15/2001
Application #:
09169368
Filing Dt:
10/09/1998
Title:
OPTICAL DRIVE ERROR TRACKING METHOD AND APPARATUS
44
Patent #:
Issue Dt:
06/19/2001
Application #:
09169812
Filing Dt:
10/09/1998
Title:
SYSTEM AND METHOD FOR BANDPASS SHAPING IN AN OVERSAMPLING CONVERTER
45
Patent #:
Issue Dt:
10/03/2000
Application #:
09170497
Filing Dt:
10/13/1998
Title:
METHOD AND APPARATUS FOR CALCULATING A CRC REMAINDER
46
Patent #:
Issue Dt:
08/22/2000
Application #:
09172563
Filing Dt:
10/14/1998
Title:
METHOD AND APPARATUS FOR TERMINATING A BUS SUCH THAT STUB LENGTH REQUIREMENTS ARE MET
47
Patent #:
Issue Dt:
12/18/2001
Application #:
09174790
Filing Dt:
10/19/1998
Title:
N-WAY RAID 1 ON M DRIVES BLOCK MAPPING METHOD
48
Patent #:
Issue Dt:
03/14/2000
Application #:
09175605
Filing Dt:
10/20/1998
Title:
CONTROLLABLE REACTANCE CIRCUIT FOR AN INTEGRATED CIRCUIT
49
Patent #:
Issue Dt:
03/13/2001
Application #:
09177335
Filing Dt:
10/22/1998
Title:
METHOD AND APPARATUS FOR DETECTING A PLANARIZED OUTER LAYER OF A SEMICONDUCTOR WAFER WITH A CONFOCAL OPTICAL SYSTEM
50
Patent #:
Issue Dt:
01/16/2001
Application #:
09183292
Filing Dt:
10/30/1998
Title:
OFF-GRID METAL LAYER UTILIZATION
51
Patent #:
Issue Dt:
08/14/2001
Application #:
09183637
Filing Dt:
10/30/1998
Title:
INTEGRATED CIRCUIT DESIGN WITH DELAYED CELL SELECTION
52
Patent #:
Issue Dt:
02/20/2007
Application #:
09183694
Filing Dt:
10/30/1998
Publication #:
Pub Dt:
08/08/2002
Title:
COMMAND QUEUEING ENGINE
53
Patent #:
Issue Dt:
02/06/2001
Application #:
09186043
Filing Dt:
11/03/1998
Title:
INTERRUPT MECHANISM ON NORTHBAY
54
Patent #:
Issue Dt:
05/27/2003
Application #:
09192102
Filing Dt:
11/13/1998
Title:
METHOD OF PROTECTING HIGH DEFINITION VIDEO SIGNAL
55
Patent #:
Issue Dt:
07/23/2002
Application #:
09192891
Filing Dt:
11/16/1998
Title:
SYSTEM FOR TRANSFERRING DATA PACKETS OF DIFFERENT CONTEXT UTILIZING SINGLE INTERFACE AND CONCURRENTLY PROCESSING DATA PACKETS OF DIFFERENT CONTEXTS
56
Patent #:
Issue Dt:
08/21/2001
Application #:
09197323
Filing Dt:
11/19/1998
Title:
ON-THE-FLY ROW-SYNDROME GENERATION FOR DVD CONTROLLER ECC
57
Patent #:
Issue Dt:
06/13/2000
Application #:
09198062
Filing Dt:
11/23/1998
Title:
TECHNIQUE FOR REDUCING PEAK CURRENT IN MEMORY OPERATIONS
58
Patent #:
Issue Dt:
05/29/2001
Application #:
09198208
Filing Dt:
11/23/1998
Title:
CONSISTENT ALIGNMENT MARK PROFILES ON SEMICONDUCTOR WAFERS USING PVD SHADOWING
59
Patent #:
Issue Dt:
04/06/2004
Application #:
09204766
Filing Dt:
12/03/1998
Title:
METHOD AND APPARATUS FOR ISOCHRONOUS DATA TRANSFER WITH RETRY CAPABILITY
60
Patent #:
Issue Dt:
01/16/2001
Application #:
09204767
Filing Dt:
12/03/1998
Title:
APPARATUS AND METHOD FOR DETECTING AN ENDPOINT OF AN ETCHING PROCESS BY TRANSMITTING INFRARED LIGHT SIGNALS THROUGH A SEMICONDUCTOR WAFER
61
Patent #:
Issue Dt:
09/19/2000
Application #:
09204813
Filing Dt:
12/03/1998
Title:
APPARATUS AND METHOD FOR BLOCKING THE DEPOSITION OF OXIDE ON A WAFER
62
Patent #:
Issue Dt:
09/05/2000
Application #:
09204815
Filing Dt:
12/03/1998
Title:
METHOD FOR FORMING AN ION IMPLANTED ELECTROSTATIC CHUCK
63
Patent #:
Issue Dt:
08/22/2000
Application #:
09205555
Filing Dt:
12/04/1998
Title:
SINGLE CELL PER BIT SHIFT REGISTER
64
Patent #:
Issue Dt:
10/08/2002
Application #:
09206448
Filing Dt:
12/07/1998
Title:
SCRIPTING METHOD AND APPARATUS FOR TESTING DEVICES
65
Patent #:
Issue Dt:
10/23/2001
Application #:
09207191
Filing Dt:
12/08/1998
Title:
FILE DRIVEN MASK INSERTION FOR AUTOMATIC TEST EQUIPMENT TEST PATTERN GENERATION
66
Patent #:
Issue Dt:
01/16/2001
Application #:
09207349
Filing Dt:
12/08/1998
Title:
ERROR CORRECTION APPARATUS AND ASSOCIATED METHOD UTILIZING PARELLEL PROCESSING
67
Patent #:
Issue Dt:
11/07/2000
Application #:
09207395
Filing Dt:
12/08/1998
Title:
NOVEL WELL FORMATION FOR CMOS DEVICES INTEGRATED CIRCUIT STRUCTURES
68
Patent #:
Issue Dt:
08/21/2001
Application #:
09207553
Filing Dt:
12/08/1998
Title:
SYSTEM AND METHOD FOR A STORAGE-EFFICIENT PARALLEL CHIEN SEARCH
69
Patent #:
Issue Dt:
10/09/2001
Application #:
09207704
Filing Dt:
12/09/1998
Title:
METHOD AND APPARATUS FOR ESTIMATING A SQUARE OF A NUMBER
70
Patent #:
Issue Dt:
04/09/2002
Application #:
09207878
Filing Dt:
12/08/1998
Title:
MODIFIED DESIGN REPRESENTATION FOR FAST FAULT SIMULATION OF AN INTEGRATED CIRCUIT
71
Patent #:
Issue Dt:
09/19/2000
Application #:
09209704
Filing Dt:
12/11/1998
Title:
APPARATUS AND METHOD OF DETECTING A POLISHING ENDPOINT LAYER OF A SEMICONDUCTOR WAFER WHICH INCLUDES A METALLIC REPORTING SUBSTANCE
72
Patent #:
Issue Dt:
10/16/2001
Application #:
09209855
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR SCRIBING A CODE IN AN INACTIVE OUTER CLEAR OUT AREA OF A SEMICONDUCTOR WAFER
73
Patent #:
Issue Dt:
07/10/2001
Application #:
09209856
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR CONFIGURING A SECTOR MAP FOR AN OPTICAL STORAGE DEVICE
74
Patent #:
Issue Dt:
07/18/2000
Application #:
09209907
Filing Dt:
12/11/1998
Title:
TESTING SEMICONDUCTOR DEVICE FOR DATA RETENTION
75
Patent #:
Issue Dt:
05/23/2000
Application #:
09209938
Filing Dt:
12/11/1998
Title:
REDUNDANCY ANALYSIS FOR EMBEDDED MEMORIES WITH BUILT-IN SELF TEST AND BUILT-IN SELF REPAIR
76
Patent #:
Issue Dt:
04/02/2002
Application #:
09209996
Filing Dt:
12/11/1998
Title:
TESTING METHODOLOGY FOR EMBEDDED MEMORIES USING BUILT-IN SELF REPAIR AND IDENTIFICATION CIRCUITRY
77
Patent #:
Issue Dt:
09/11/2001
Application #:
09210184
Filing Dt:
12/11/1998
Publication #:
Pub Dt:
05/24/2001
Title:
METHOD AND APPARATUS FOR REMOVING RESIDUAL MATERIAL FROM AN ALIGNMENT MARK OF A SEMICONDUCTOR WAFER
78
Patent #:
Issue Dt:
09/04/2001
Application #:
09210284
Filing Dt:
12/11/1998
Title:
METHOD AND APPARATUS FOR AUTOMATIC SECTOR FORMAT IDENTIFICATION IN AN OPTICAL STORAGE DEVICE
79
Patent #:
Issue Dt:
10/16/2001
Application #:
09211129
Filing Dt:
12/14/1998
Title:
METHOD AND APPARATUS FOR PERFORMING EFFICIENT RESEEKS IN AN OPTICAL STORAGE DEVICE
80
Patent #:
Issue Dt:
11/21/2000
Application #:
09211207
Filing Dt:
12/13/1998
Title:
SYSTEM, APPARATUS, AND METHOD FOR AUTOMATIC NODE ISOLATING SCSI TERMINATOR SWITCH
81
Patent #:
Issue Dt:
07/18/2000
Application #:
09211922
Filing Dt:
12/15/1998
Title:
METHOD FOR COMPOSING A THERMALLY CONDUCTIVE THIN FILM HAVING A LOW DIELECTRIC PROPERTY
82
Patent #:
Issue Dt:
03/19/2002
Application #:
09212315
Filing Dt:
12/15/1998
Title:
IMPROVED DUAL GATE OXIDE PROCESS FOR DEEP SUBMICRON ICS
83
Patent #:
Issue Dt:
11/21/2000
Application #:
09212366
Filing Dt:
12/15/1998
Title:
COPPER CONTAMINATION CONTROL OF IN-LINE PROBE INSTRUMENTS
84
Patent #:
Issue Dt:
12/11/2001
Application #:
09212450
Filing Dt:
12/16/1998
Title:
TUNGSTEN LOCAL INTERCONNECT FOR SILICON INTEGRATED CIRCUIT STRUCTURES, AND METHOD OF MAKING SAME
85
Patent #:
Issue Dt:
09/12/2000
Application #:
09212503
Filing Dt:
12/15/1998
Title:
ENDPOINT DETECTION METHOD AND APPARATUS WHICH UTILIZE A CHELATING AGENT TO DETECT A POLISHING ENDPOINT
86
Patent #:
Issue Dt:
04/10/2001
Application #:
09212769
Filing Dt:
12/16/1998
Title:
INTEGRATED CIRCUIT DESIGN USING A FREQUENCY SYNTHESIZER THAT AUTOMATICALLY ENSURES TESTABILITY
87
Patent #:
Issue Dt:
08/21/2001
Application #:
09212931
Filing Dt:
12/16/1998
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A RECESSED GATE STRUCTURE
88
Patent #:
Issue Dt:
11/13/2001
Application #:
09213803
Filing Dt:
12/17/1998
Title:
APPARATUS AND METHOD OF PLANARIZING A SEMICONDUCTOR WAFER THAT INCLUDES A FIRST REFLECTIVE SUBSTANCE AND A SECOND REFLECTIVE SUBSTANCE
89
Patent #:
Issue Dt:
01/23/2001
Application #:
09213847
Filing Dt:
12/17/1998
Title:
FABRICATION OF METAL-INSULATOR-METAL CAPACITIVE STRUCTURES
90
Patent #:
Issue Dt:
03/04/2003
Application #:
09213948
Filing Dt:
12/17/1998
Title:
SUBSTRATE PLANARIZATION WITH A CHEMICAL MECHANICAL POLISHING STOP LAYER
91
Patent #:
Issue Dt:
05/22/2001
Application #:
09216394
Filing Dt:
12/18/1998
Title:
FABRICATION OF DIFFERENTIAL GATE OXIDE THICKNESSES ON A SINGLE INTEGRATED CIRCUIT CHIP
92
Patent #:
Issue Dt:
11/28/2000
Application #:
09216636
Filing Dt:
12/18/1998
Title:
DISK FORMATTER WRITE GATE LOOK-AHEAD DEVICE
93
Patent #:
Issue Dt:
08/28/2001
Application #:
09217182
Filing Dt:
12/21/1998
Title:
ON-CHIP SINGLE LAYER HORIZONTAL DEFLECTING WAVEGUIDE AND DAMASCENE METHOD OF FABRICATING THE SAME
94
Patent #:
Issue Dt:
08/10/2004
Application #:
09217183
Filing Dt:
12/21/1998
Title:
ON-CHIP GRADED INDEX OF REFRACTION OPTICAL WAVEGUIDE AND DAMASCENE METHOD OF FABRICATING THE SAME
95
Patent #:
Issue Dt:
11/27/2001
Application #:
09217184
Filing Dt:
12/21/1998
Title:
ON-CHIP MULTIPLE LAYER VERTICALLY TRANSITIONING OPTICAL WAVEGUIDE AND DAMASCENE METHOD OF FABRICATING THE SAME
96
Patent #:
Issue Dt:
09/18/2001
Application #:
09217974
Filing Dt:
12/18/1998
Title:
METHOD TO ALLOW HARDWARE CONFIGURABLE DATA STRUCTURES
97
Patent #:
Issue Dt:
04/01/2003
Application #:
09219246
Filing Dt:
12/22/1998
Title:
MULTIDIRECTIONAL COMMUNICATION SYSTEMS
98
Patent #:
Issue Dt:
08/06/2002
Application #:
09219247
Filing Dt:
12/22/1998
Title:
IMPROVEMENTS RELATING TO MULTIDIRECTIONAL COMMUNICATION SYSTEMS
99
Patent #:
Issue Dt:
07/24/2001
Application #:
09219567
Filing Dt:
12/22/1998
Title:
CONTROLLABLE LATCH/REGISTER CIRCUIT
100
Patent #:
Issue Dt:
07/09/2002
Application #:
09219655
Filing Dt:
12/23/1998
Title:
VERTICAL INTERDIGITATED METAL-INSULATOR-MATAL CAPACITOR FOR AN INTEGRATED CIRCUIT
Assignor
1
Exec Dt:
04/06/2007
Assignee
1
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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