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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09637230
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Filing Dt:
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08/11/2000
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Title:
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INSTRUCTION TRANSLATION SYSTEM AND METHOD ACHIEVING SINGLE-CYCLE TRANSLATION OF VARIABLE-LENGTH MIPS16 INSTRUCTIONS
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09639375
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Filing Dt:
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08/15/2000
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Title:
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Information storage systems utilizing media with optically-differentiated data sites
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09639534
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Filing Dt:
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08/16/2000
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Title:
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METHOD AND APPARATUS FOR CONTROLLING AND NORMALIZING THE DESIRED RATE OF A VISUAL PROCESS ACROSS DIFFERENT COMPUTING PLATFORMS AND ENVIRONMENTS
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09641661
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Filing Dt:
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08/18/2000
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Title:
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TEST LIMITS BASED ON POSITION
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09644187
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Filing Dt:
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08/22/2000
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Title:
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METHOD AND APPARATUS FOR MODULATION ENCODING DATA FOR STORAGE ON A MULTI-LEVEL OPTICAL RECORDING MEDIUM
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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09645637
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Filing Dt:
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08/24/2000
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Title:
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METHOD AND ARCHITECTURE TO ASSOCIATE ENCLOSURE SERVICE DATA WITH PHYSICAL DEVICES ON A FIBRE CHANNEL LOOP WITH SOFT ADDRESSES
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09645949
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Filing Dt:
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08/25/2000
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Title:
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RAID VOLUME FOR SEQUENTIAL USE THAT NEEDS NO REDUNDANCY PRE-INITIALIZATION
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09650164
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Filing Dt:
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08/29/2000
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Title:
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RESIDUAL OXYGEN REDUCTION SYSTEM
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09651308
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Filing Dt:
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08/30/2000
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Title:
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THIN FORM FACTOR FLIP CHIP BALL GRID ARRAY
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09654689
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Filing Dt:
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09/05/2000
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Title:
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INTEGRATED CIRCUIT ISOLATION SYSTEM
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09654952
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Filing Dt:
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09/05/2000
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Title:
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DATA-BURST-COUNT-BASE RECEIVE FIFO CONTROL DESIGN AND EARLY PACKET DISCARD FOR DMA OPTIMIZATION
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09661465
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Filing Dt:
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09/13/2000
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Title:
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PROCESS FOR PLANARIZATION OF INTEGRATED CIRCUIT STRUCTURE WHICH INHIBITS CRACKING OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL ADJACENT UNDERLYING RAISED STRUCTURES
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09665924
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Filing Dt:
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09/20/2000
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Title:
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INCREMENTER/DECREMENTER CIRCUIT
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09665988
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Filing Dt:
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09/20/2000
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Title:
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CONCENTRIC OPTICAL CABLE WITH FULL DUPLEX CONNECTORS
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09666507
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Filing Dt:
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09/20/2000
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Title:
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EXHAUST FLOW CONTROL SYSTEM
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09666676
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Filing Dt:
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09/20/2000
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Title:
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METHOD AND APPARATUS FOR ACCOMMODATING IRREGULAR MEMORY WRITE WORD WIDTHS
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09669979
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Filing Dt:
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09/26/2000
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Title:
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Planarization system
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09670448
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Filing Dt:
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09/26/2000
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Title:
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SHALLOW JUNCTION FORMATION
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09670997
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Filing Dt:
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09/27/2000
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Title:
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NONVOLATILE MEMORY IN CMOS PROCESS FLOW
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09670998
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Filing Dt:
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09/27/2000
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Title:
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PROCESS FOR PLANARIZING AN ISOLATION STRUCTURE IN A SUBSTRATE
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09675109
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Filing Dt:
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09/28/2000
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Title:
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REDUCED SOFT ERROR RATE (SER) CONSTRUCTION FOR INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09676516
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Filing Dt:
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10/02/2000
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Title:
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DIGITAL-TO-ANALOG CONVERTER WITH HIGH DYNAMIC RANGE
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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09676909
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Filing Dt:
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10/02/2000
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Title:
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SERIAL DATA COMMUNICATION RECEIVER HAVING ADAPTIVE TERMINATION RESISTORS
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09677269
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Filing Dt:
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10/02/2000
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Title:
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SERIAL DATA COMMUNICATION RECEIVER HAVING ADAPTIVE EQUALIZATION
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09677276
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DETECING EQUIVALENT AND ANTI-EQUIVALENT PINS
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Patent #:
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Issue Dt:
|
03/02/2004
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Application #:
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09677350
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Filing Dt:
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10/02/2000
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Title:
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SERIAL DATA COMMUNICATION RECEIVER HAVING ADAPTIVELY MINIMIZED CAPTURE LATCH OFFSET VOLTAGE
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09677475
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR TIMING DRIVEN RESYNTHESIS
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09677623
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Filing Dt:
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10/03/2000
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Title:
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METHOD TO MAKE A PHASE-LOCKED LOOP'S JITTER TRANSFER FUNCTION INDEPENDENT OF DATA TRANSITION DENSITY
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09677940
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR QUICK SEARCH FOR IDENTITIES APPLICABLE TO SPECIFIED FORMULA
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09678201
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Filing Dt:
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10/01/2000
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Title:
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METHOD AND APPARATUS FOR FORMULAE AREA AND DELAY MINIMIZATION
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09678478
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR DYNAMIC BUFFER AND INVERTER TREE OPTIMIZATION
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09678479
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR LOCAL RESYNTHESIS OF LOGIC TREES WITH MULTIPLE COST FUNCTIONS
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09678481
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Filing Dt:
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10/02/2000
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Title:
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METHOD AND APPARATUS FOR OPTIMAL CRITICAL NETLIST AREA SELECTION
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09679209
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Filing Dt:
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10/04/2000
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Title:
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FAST FLEXIBLE SEARCH ENGINE FOR LONGEST PREFIX MATCH
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09679313
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Filing Dt:
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10/04/2000
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Title:
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FLEXIBLE SEARCH ENGINE HAVING SORTED BINARY SEARCH TREE FOR PERFECT MATCH
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09680759
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Filing Dt:
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10/06/2000
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Title:
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BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09680893
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ANALYSIS OF TIMING MARGINS AND SIGNAL SKEWS OF RELEVANT LOGIC CELLS USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09684770
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Filing Dt:
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10/06/2000
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Title:
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METHOD OF AUTOMATICALLY GENERATING SCHEMATIC AND WAVEFORM DIAGRAMS FOR ISOLATING FAULTS FROM MULTIPLE FAILING PATHS IN A CIRCUIT USING INPUT SIGNAL PREDICTORS AND TRANSITION TIMES
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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09684868
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Filing Dt:
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10/06/2000
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Title:
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DIAGNOSTIC ARCHITECTURE USING FPGA CORE IN SYSTEM ON A CHIP DESIGN
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09685856
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Filing Dt:
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10/11/2000
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Title:
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MODULATION OF A PRIMARY DATA CHANNEL REFERENCE CLOCK TO FORM A SEPARATE DATA COMMUNICATION CHANNEL
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09685990
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Filing Dt:
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10/10/2000
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Title:
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METHOD AND APPARATUS FOR MINIMIZATION OF NET DELAY BY OPTIMAL BUFFER INSERTION
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09686675
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Filing Dt:
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10/11/2000
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Title:
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VITERBI DECODER WITH ADAPTIVE TRACEBACK
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09687263
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Filing Dt:
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10/12/2000
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Title:
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INSULATED BONDING WIRE FOR MICROELECTRONIC PACKAGING
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09690047
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Filing Dt:
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10/16/2000
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Title:
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METHOD AND APPARATUS FOR WASHING DRUMS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09694534
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Filing Dt:
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10/23/2000
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Title:
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METHOD THAT ALLOWS I/O REQUESTS TO RUN CONCURRENTLY WITH A ROLLBACK FROM A SNAPSHOT IN A DRIVE ARRAY
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09695540
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Filing Dt:
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10/24/2000
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Title:
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APPARATUS SUITABLE FOR MOUNTING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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09702202
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Filing Dt:
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10/30/2000
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Title:
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STORAGE DEVICE, SYSTEM AND METHOD WHICH CAN USE TAG BITS TO SYNCHRONIZE QUEUING BETWEEN TWO CLOCK DOMAINS, AND DETECT VALID ENTRIES WITHIN THE STORAGE DEVICE
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09702384
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Filing Dt:
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10/31/2000
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Title:
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Multiple bit line memory architecture
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09703616
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Filing Dt:
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10/30/2000
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Title:
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PROCESS FOR CMP REMOVAL OF EXCESS TRENCH OR VIA FILLER METAL WHICH INHIBITS FORMATION OF CONCAVE REGIONS ON OXIDE SURFACE OF INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09703745
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Filing Dt:
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10/31/2000
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Title:
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PROCESS FOR PLANARIZATION OF METAL-FILLED TRENCHES OF INTEGRATED CIRCUIT STRUCTURES BY FORMING A LAYER OF PLANARIZABLE MATERIAL OVER THE METAL LAYER PRIOR TO PLANARIZING
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09704164
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Filing Dt:
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10/31/2000
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Title:
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PROCESS FOR FORMING LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09704200
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Filing Dt:
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10/31/2000
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Title:
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09704635
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Filing Dt:
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11/01/2000
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Title:
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PROCESS FOR INHIBITING CRACK FORMATION IN LOW DIELECTRIC CONSTANT DIELECTRIC FILMS OF INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09705030
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Filing Dt:
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11/02/2000
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Title:
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Laser fuse circuit design
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09706286
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Filing Dt:
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11/03/2000
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Title:
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PROCESS MONITOR WITH STATISTICALLY SELECTED RING OSCILLATOR
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09710359
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Filing Dt:
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11/09/2000
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Title:
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METHOD TO TRANSLATE UDPS USING GATE PRIMITIVES
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09711498
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Filing Dt:
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11/13/2000
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Title:
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METHOD AND APPARATUS FOR DIRECTLY BOOTING A RAID VOLUME AS THE PRIMARY OPERATING SYSTEM MEMORY
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09711594
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Filing Dt:
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11/13/2000
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Title:
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SYSTEM AND METHOD FOR SYNCHRONIZING DATA MIRRORED BY STORAGE SUBSYSTEMS
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Patent #:
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Issue Dt:
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01/15/2002
|
Application #:
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09713085
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Filing Dt:
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11/15/2000
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Title:
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Photovoltaic power source for portable electronic device
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Patent #:
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Issue Dt:
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08/19/2003
|
Application #:
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09714000
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Filing Dt:
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11/15/2000
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Title:
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PROCESS FOR FORMING PLANARIZED ISOLATION TRENCH IN INTEGRATED CIRCUIT STRUCTURE ON SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
|
12/17/2002
|
Application #:
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09715814
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Filing Dt:
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11/17/2000
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Title:
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STANDARD LIBRARY GENERATOR FOR CELL TIMING MODEL
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Patent #:
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Issue Dt:
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07/06/2004
|
Application #:
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09721079
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Filing Dt:
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11/22/2000
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Title:
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PAUSING AN INSTRUCTION CACHE LINE FETCH IN RESPONSE TO A BRANCH INSTRUCTION AND RESUMING FROM WHERE PAUSED AFTER EVALUATING A BRANCH PREDICTION
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09721319
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Filing Dt:
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11/22/2000
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Title:
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COMPACT DISC EMULATION IN A FLASH
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Patent #:
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Issue Dt:
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01/20/2004
|
Application #:
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09722892
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Filing Dt:
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11/27/2000
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Title:
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METHOD AND SYSTEM FOR EXPANDING VOLUME CAPACITY
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09723095
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Filing Dt:
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11/27/2000
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Title:
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SYSTEM AND METHOD FOR AUTOMATIC DYNAMIC EXPANSION OF A SNAPSHOT REPOSITORY
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Patent #:
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Issue Dt:
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02/25/2003
|
Application #:
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09723434
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Filing Dt:
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11/27/2000
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Title:
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METAL-INSULATOR-METAL CAPACITOR FORMED BY DAMASCENE PROCESSES BETWEEN METAL INTERCONNECT LAYERS AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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05/20/2003
|
Application #:
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09723476
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Filing Dt:
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11/27/2000
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Title:
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LASER-BREAKABLE FUSE LINK WITH ALIGNMENT AND BREAK POINT POMOTION STRUCTURES
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Patent #:
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Issue Dt:
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08/20/2002
|
Application #:
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09723516
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Filing Dt:
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11/28/2000
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Title:
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SILICON NITRIDE AND SILICON DIOXIDE GATE INSULATOR TRANSISTORS AND METHOD OF FORMING SAME IN A HYBRID INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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02/18/2003
|
Application #:
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09724225
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Filing Dt:
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11/28/2000
|
Title:
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METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBIRD INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBIRD CIRCUIT
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Patent #:
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Issue Dt:
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04/08/2003
|
Application #:
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09724444
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Filing Dt:
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11/28/2000
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Title:
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SILICON GERMANIUM CMOS CHANNEL
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Patent #:
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Issue Dt:
|
11/19/2002
|
Application #:
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09725543
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Filing Dt:
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11/29/2000
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Title:
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INTEGRATED EJTAG EXTERNAL BUS INTERFACE
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Patent #:
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Issue Dt:
|
04/29/2003
|
Application #:
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09725631
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Filing Dt:
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11/29/2000
|
Title:
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DEVICE FREQUENCY MEASUREMENT SYSTEM
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Patent #:
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Issue Dt:
|
01/15/2002
|
Application #:
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09726107
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Filing Dt:
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11/29/2000
|
Title:
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Programmable read only memory in CMOS process flow
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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09726144
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Filing Dt:
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11/29/2000
|
Publication #:
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Pub Dt:
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05/30/2002
| | | | |
Title:
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SIMPLE BRANCH PREDICTION AND MISPREDICTION RECOVERY METHOD
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Patent #:
|
|
Issue Dt:
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01/17/2006
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Application #:
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09726819
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Filing Dt:
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11/30/2000
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Title:
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SYSTEM TO EFFICIENTLY TRANSMIT TWO HDTV CHANNELS OVER SATELLITE USING TURBO CODED 8PSK MODULATION FOR DSS COMPLIANT RECEIVERS
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Patent #:
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Issue Dt:
|
01/14/2003
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Application #:
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09727043
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Filing Dt:
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11/30/2000
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Title:
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INTEGRATED CIRCUIT MEMORY HAVING COLUMN REDUNDANCY
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Patent #:
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Issue Dt:
|
09/10/2002
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Application #:
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09727426
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Filing Dt:
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11/30/2000
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Publication #:
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Pub Dt:
|
05/30/2002
| | | | |
Title:
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PIN PLACEMENT METHOD FOR INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
10/15/2002
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Application #:
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09727427
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Filing Dt:
|
11/30/2000
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Title:
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NON-ISOTHERMAL ELECTROMIGRATION TESTING OF MICROELECTRONIC PACKAGING INTERCONNECTS
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|
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Patent #:
|
|
Issue Dt:
|
04/02/2002
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Application #:
|
09729020
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Filing Dt:
|
12/04/2000
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Title:
|
INTEGRATED CIRCUIT MEMORY HAVING COLUMN REDUNDANCY WITH NO TIMING PENALITY
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|
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Patent #:
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|
Issue Dt:
|
12/06/2005
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Application #:
|
09729508
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Filing Dt:
|
12/04/2000
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Title:
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PROCESSOR PIPELINE STALL BASED ON DATA REGISTER STATUS
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|
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Patent #:
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|
Issue Dt:
|
07/02/2002
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Application #:
|
09730704
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Filing Dt:
|
12/06/2000
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Publication #:
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|
Pub Dt:
|
06/14/2001
| | | | |
Title:
|
CMP SLURRY RECYCLING APPARATUS AND METHOD FOR RECYCLING CMP SLURRY
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|
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Patent #:
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|
Issue Dt:
|
06/24/2003
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Application #:
|
09731476
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Filing Dt:
|
12/06/2000
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Title:
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DATA-CACHE DATA-PATH
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|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
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Application #:
|
09731596
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Filing Dt:
|
12/06/2000
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Title:
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METHOD FOR PROBING A SEMICONDUCTOR WAFER
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|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09732946
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Filing Dt:
|
12/08/2000
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Title:
|
DATA CACHE STORE BUFFER
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|
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Patent #:
|
|
Issue Dt:
|
04/20/2004
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Application #:
|
09734539
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Filing Dt:
|
12/11/2000
|
Title:
|
A METHOD FOR MINIMIZING CLOCK SKEW BY RELOCATING A CLOCK BUFFER UNTIL CLOCK SKEW IS WITHIN A TOLERABLE LIMIT
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|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09734999
|
Filing Dt:
|
12/12/2000
|
Title:
|
System for programmable chip initialization
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09735084
|
Filing Dt:
|
12/11/2000
|
Title:
|
ETCH RESISTANT SHALLOW TRENCH ISOLATION IN A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09735085
|
Filing Dt:
|
12/11/2000
|
Title:
|
INTERCONNECTOR AND METHOD OF CONNECTING PROBES TO A DIE FOR FUNCTIONAL ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
01/22/2002
|
Application #:
|
09735233
|
Filing Dt:
|
12/11/2000
|
Title:
|
Designing memory for testability to support scan capability in an asic design
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|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09735255
|
Filing Dt:
|
12/12/2000
|
Title:
|
DELAY/LOAD ESTIMATION FOR USE IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
09735820
|
Filing Dt:
|
12/12/2000
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
Title:
|
TESTING OF HIGH SPEED DDR INTERFACE USING SINGLE CLOCK EDGE TRIGGERED TESTER DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09735837
|
Filing Dt:
|
12/13/2000
|
Title:
|
CELL PIN EXTENSIONS FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
09736571
|
Filing Dt:
|
12/14/2000
|
Title:
|
NETLIST RESYNTHESIS PROGRAM USING STRUCTURE CO-FACTORING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
09736883
|
Filing Dt:
|
12/14/2000
|
Title:
|
INTERFACE FOR BUS INDEPENDENT CORE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2003
|
Application #:
|
09737239
|
Filing Dt:
|
12/14/2000
|
Title:
|
NETLIST RESYNTHESIS PROGRAM BASED ON PHYSICAL DELAY CALCULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09737837
|
Filing Dt:
|
12/15/2000
|
Title:
|
SOURCE PULSED, DYNAMIC THRESHOLD COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STATIC RAM CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
09738485
|
Filing Dt:
|
12/15/2000
|
Title:
|
CONFIGURABLE HARDWARE REGISTER STACK FOR CPU ARCHITECTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
09739956
|
Filing Dt:
|
12/19/2000
|
Title:
|
GENERATOR OF GRAPHICS IN COMPUTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09740604
|
Filing Dt:
|
12/19/2000
|
Title:
|
NOVEL WAY TO COMPENSATE THE EFFECT OF COUPLING BETWEEN BITLINES IN A MULTI-PORT MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2004
|
Application #:
|
09740907
|
Filing Dt:
|
12/19/2000
|
Title:
|
BUS MONITOR AND METHOD OF GATHERING BUS PHASE INFORMATION IN REAL-TIME
|
|