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Reel/Frame:033102/0270   Pages: 90
Recorded: 06/06/2014
Attorney Dkt #:040981-0072
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 3258
Page 17 of 33
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
Patent #:
Issue Dt:
07/01/2003
Application #:
09843443
Filing Dt:
04/26/2001
Title:
DUAL CHIP IN PACKAGE WITH A WIRE BONDED DIE MOUNTED TO A SUBSTRATE
2
Patent #:
Issue Dt:
03/04/2003
Application #:
09844299
Filing Dt:
04/26/2001
Title:
SUPPLY DEGRADATION COMPENSATION FOR MEMORY SELF TIME CIRCUITS
3
Patent #:
Issue Dt:
07/27/2004
Application #:
09844352
Filing Dt:
04/27/2001
Title:
IN SITU LINER BARRIER
4
Patent #:
Issue Dt:
01/28/2003
Application #:
09844361
Filing Dt:
04/27/2001
Title:
DENSITY DRIVEN ASSIGNMENT OF COORDINATES
5
Patent #:
Issue Dt:
07/22/2003
Application #:
09844531
Filing Dt:
04/27/2001
Title:
ANALOG CAPACITOR DUAL DAMASCENE PROCESS
6
Patent #:
Issue Dt:
02/17/2004
Application #:
09845909
Filing Dt:
04/30/2001
Title:
METHOD AND APPARATUS FOR LOADING/STORING MULTIPLE DATA SOURCES TO COMMON MEMORY UNIT
7
Patent #:
Issue Dt:
08/13/2002
Application #:
09846435
Filing Dt:
05/01/2001
Title:
TEST FIXTURE FOR FLIP CHIP BALL GRID ARRAY CIRCUITS
8
Patent #:
Issue Dt:
12/31/2002
Application #:
09847460
Filing Dt:
05/02/2001
Title:
CIRCUIT MODELING
9
Patent #:
Issue Dt:
03/04/2003
Application #:
09847838
Filing Dt:
04/30/2001
Publication #:
Pub Dt:
10/31/2002
Title:
RTL ANNOTATION TOOL FOR LAYOUT INDUCED NETLIST CHANGES
10
Patent #:
Issue Dt:
05/11/2004
Application #:
09847848
Filing Dt:
04/30/2001
Title:
PARAMETERIZABLE QUEUED MEMORY ACCESS SYSTEM
11
Patent #:
Issue Dt:
12/10/2002
Application #:
09848489
Filing Dt:
05/03/2001
Title:
METHOD AND APPARATUS FOR INDENTIFYING CAUSES OF POOR SILICON-TO-SIMULATION CORRELATION
12
Patent #:
Issue Dt:
10/26/2004
Application #:
09848569
Filing Dt:
05/02/2001
Title:
METHOD AND APPARATUS FOR PROCESSING CHAIN MESSAGES (SGL CHAINING)
13
Patent #:
Issue Dt:
01/07/2003
Application #:
09848758
Filing Dt:
05/02/2001
Publication #:
Pub Dt:
11/07/2002
Title:
PROCESS FOR FORMING METAL-FILLED OPENINGS IN LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL WHILE INHIBITING VIA POISONING
14
Patent #:
Issue Dt:
12/31/2002
Application #:
09848942
Filing Dt:
05/04/2001
Title:
HIGH SPEED INPUT BUFFER CIRCUIT
15
Patent #:
Issue Dt:
09/16/2003
Application #:
09849640
Filing Dt:
05/04/2001
Title:
CONTROL CIRCUIT FOR POWER
16
Patent #:
Issue Dt:
07/11/2006
Application #:
09849691
Filing Dt:
05/04/2001
Title:
MINIMAL BENDS CONNECTION MODELS FOR WIRE DENSITY CALCULATION
17
Patent #:
Issue Dt:
11/26/2002
Application #:
09849919
Filing Dt:
05/04/2001
Title:
PROCESS, APPARATUS AND PROGRAM FOR TRANSFORMING PROGRAM LANGUAGE DESCRIPTION OF AN IC TO AN RTL DESCRIPTION
18
Patent #:
Issue Dt:
04/12/2005
Application #:
09850865
Filing Dt:
05/08/2001
Title:
PIPELINED PROCESSOR AND METHOD USING A PROFILE REGISTER STORING THE RETURN FROM EXCEPTION ADDRESS OF AN EXECUTED INSTRUCTION SUPPLIED BY AN EXCEPTION PROGRAM COUNTER CHAIN FOR CODE PROFILING
19
Patent #:
Issue Dt:
05/09/2006
Application #:
09851181
Filing Dt:
05/08/2001
Title:
APPLICATION SPECIFIC INTEGRATED CIRCUIT HAVING A PROGRAMMABLE LOGIC CORE AND A METHOD OF OPERATION THEREOF
20
Patent #:
Issue Dt:
11/18/2008
Application #:
09851504
Filing Dt:
05/08/2001
Title:
FIELD PROGRAMMABLE NETWORK APPLICATION SPECIFIC INTEGRATED CIRCUIT AND A METHOD OF OPERATION THEREOF
21
Patent #:
Issue Dt:
12/02/2003
Application #:
09851712
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
07/18/2002
Title:
BURST SIGNAL GENERATION FOR PIPELINED ACCESS TO AMBA BUS
22
Patent #:
Issue Dt:
10/05/2004
Application #:
09851860
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
07/04/2002
Title:
BIT REDUCTION USING DITHER, ROUNDING AND ERROR FEEDBACK
23
Patent #:
Issue Dt:
09/16/2003
Application #:
09852437
Filing Dt:
05/10/2001
Title:
BUS SNOOPING FOR CACHE COHERENCY FOR A BUS WITHOUT BUILT-IN BUS SNOOPING CAPABILITIES
24
Patent #:
Issue Dt:
08/03/2004
Application #:
09853562
Filing Dt:
05/11/2001
Title:
DATA TIMELINE MANAGEMENT USING SNAPSHOT VOLUMES
25
Patent #:
Issue Dt:
03/27/2007
Application #:
09855011
Filing Dt:
05/14/2001
Title:
VIDEO HORIZONTAL AND VERTICAL VARIABLE SCALING FILTER
26
Patent #:
Issue Dt:
01/14/2003
Application #:
09858166
Filing Dt:
05/15/2001
Title:
NET DELAY OPTIMIZATION WITH RAMPTIME VIOLATION REMOVAL
27
Patent #:
Issue Dt:
03/01/2005
Application #:
09858686
Filing Dt:
05/15/2001
Title:
MINIMUM METAL CONSUMPTION POWER DISTRIBUTION NETWORK ON A BONDED DIE
28
Patent #:
Issue Dt:
07/01/2003
Application #:
09859149
Filing Dt:
05/15/2001
Title:
MODELING DELAYS FOR SMALL NETS IN AN INTEGRATED CIRCUIT DESIGN
29
Patent #:
Issue Dt:
07/08/2003
Application #:
09859880
Filing Dt:
05/17/2001
Publication #:
Pub Dt:
02/06/2003
Title:
HEXADECAGONAL ROUTING
30
Patent #:
Issue Dt:
08/23/2005
Application #:
09860149
Filing Dt:
05/17/2001
Publication #:
Pub Dt:
01/09/2003
Title:
PROGRAMMABLE COUNTERS FOR SETTING BUS ARBITRATION DELAYS INVOLVES COUNTING CLOCK CYCLES EQUAL TO A COUNT NUMBER LOADED FROM A MEMORY
31
Patent #:
Issue Dt:
08/31/2004
Application #:
09862000
Filing Dt:
05/04/2001
Title:
PREFIX COMPARATOR
32
Patent #:
Issue Dt:
12/16/2003
Application #:
09862045
Filing Dt:
05/21/2001
Title:
IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
33
Patent #:
Issue Dt:
02/28/2006
Application #:
09862261
Filing Dt:
05/21/2001
Publication #:
Pub Dt:
07/25/2002
Title:
CYCLIC BUFFER FOR INFRARED
34
Patent #:
Issue Dt:
11/16/2004
Application #:
09862531
Filing Dt:
05/22/2001
Publication #:
Pub Dt:
06/13/2002
Title:
APPARATUS AND METHOD FOR DETECTING A PREDETERMINED PATTERN OF BITS IN A BITSTREAM
35
Patent #:
Issue Dt:
08/08/2006
Application #:
09863736
Filing Dt:
05/22/2001
Publication #:
Pub Dt:
05/16/2002
Title:
DEVICE AND METHOD FOR EFFICIENT DECODING WITH TIME REVERSED DATA
36
Patent #:
Issue Dt:
07/13/2004
Application #:
09863744
Filing Dt:
05/23/2001
Publication #:
Pub Dt:
07/18/2002
Title:
APPARATUS AND METHOD OF INTERRUPT DETECTION IN AN OPTICAL DISC ENVIRONMENT
37
Patent #:
Issue Dt:
09/30/2003
Application #:
09864760
Filing Dt:
05/24/2001
Title:
MESSAGE INDEX DESCRIPTOR
38
Patent #:
Issue Dt:
01/14/2003
Application #:
09865900
Filing Dt:
05/25/2001
Publication #:
Pub Dt:
11/28/2002
Title:
SELF ALIGNED GATE
39
Patent #:
Issue Dt:
03/22/2005
Application #:
09866525
Filing Dt:
05/25/2001
Title:
LINE INTERFACE, APPARATUS AND METHOD FOR COUPLING TRANSCEIVER AND TRANSMISSION LINE
40
Patent #:
Issue Dt:
08/20/2002
Application #:
09866661
Filing Dt:
05/30/2001
Title:
RTL CODE OPTIMIZATION FOR RESOURCE SHARING STRUCTURES
41
Patent #:
Issue Dt:
08/24/2004
Application #:
09867052
Filing Dt:
05/29/2001
Publication #:
Pub Dt:
05/30/2002
Title:
METHOD AND APPARATUS FOR REDUCING NOISE IN A TRACKING ERROR SIGNAL
42
Patent #:
Issue Dt:
02/01/2005
Application #:
09870136
Filing Dt:
05/30/2001
Title:
MULTI-CHANNEL INTERFACE CONTROLLER FOR ENABLING A HOST TO INTERFACE WITH ONE OR MORE HOST DEVICES
43
Patent #:
Issue Dt:
05/06/2003
Application #:
09870851
Filing Dt:
05/30/2001
Title:
SLOPED SIDEWALL VIA FOR INTEGRATED CIRCUIT STRUCTURE TO SUPPRESS VIA POISONING AND PROCESS FOR FORMING SAME
44
Patent #:
Issue Dt:
11/05/2002
Application #:
09870949
Filing Dt:
05/31/2001
Title:
METHOD AND APPARATUS FOR TESTING HIGH FREQUENCY DELAY LOCKED LOOPS
45
Patent #:
Issue Dt:
04/01/2003
Application #:
09871023
Filing Dt:
05/31/2001
Title:
PROGRAMMABLE SELF TIME CIRCUITRY FOR MEMORIES
46
Patent #:
Issue Dt:
10/08/2002
Application #:
09871129
Filing Dt:
05/31/2001
Title:
IC TIMING ANALYSIS WITH KNOWN FALSE PATHS
47
Patent #:
Issue Dt:
01/27/2004
Application #:
09871177
Filing Dt:
05/31/2001
Title:
OUT OF ORDER EXECUTION MEMORY ACCESS REQUEST FIFO
48
Patent #:
Issue Dt:
06/24/2003
Application #:
09872058
Filing Dt:
05/31/2001
Title:
PROCESS FOR FORMING A LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL ON AN INTEGRATED CIRCUIT STRUCTURE
49
Patent #:
Issue Dt:
04/11/2006
Application #:
09872246
Filing Dt:
05/31/2001
Title:
DYNAMIC BREAK LOOP FOR CLOSED LOOP UNMANAGED STACKING SWITCHES
50
Patent #:
Issue Dt:
07/08/2003
Application #:
09872327
Filing Dt:
06/01/2001
Title:
THERMAL AND MECHANICAL ATTACHMENT OF A HEATSPREADER TO A FLIP-CHIP INTEGRATED CIRCUIT STRUCTURE USING UNDERFILL
51
Patent #:
Issue Dt:
11/09/2004
Application #:
09872486
Filing Dt:
05/31/2001
Title:
CREATION OF SYNCHRONIZATION MARKS IN MULTILEVEL OPTICAL DATA STORAGE
52
Patent #:
Issue Dt:
02/27/2007
Application #:
09872582
Filing Dt:
06/04/2001
Title:
TESTING IMPLEMENTATION SUITABLE FOR BUILT-IN SELF-REPAIR (BISR) MEMORIES
53
Patent #:
Issue Dt:
06/15/2004
Application #:
09872643
Filing Dt:
06/01/2001
Title:
METHOD TO PROTECT AND RECOVER A WRITE AHEAD LOG FROM INTERRUPTIONS
54
Patent #:
Issue Dt:
11/11/2003
Application #:
09872883
Filing Dt:
06/01/2001
Title:
ADDRESS TRANSLATION CIRCUIT FOR PROCESSORS UTILIZING A SINGLE CODE IMAGE
55
Patent #:
Issue Dt:
05/13/2003
Application #:
09873043
Filing Dt:
05/31/2001
Title:
PROCESS FOR REMOVAL OF RESIST MASK OVER LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL OF AN INTEGRATED CIRCUIT STRUCTURE, AND REMOVAL OF RESIDUES FROM VIA ETCH AND RESIST MASK REMOVAL
56
Patent #:
Issue Dt:
12/31/2002
Application #:
09875314
Filing Dt:
06/04/2001
Title:
METHOD OF CLOCK BUFFER PARTITIONING TO MINIMIZE CLOCK SKEW FOR AN INTEGRATED CIRCUIT DESIGN
57
Patent #:
Issue Dt:
08/27/2002
Application #:
09876736
Filing Dt:
06/06/2001
Title:
METHOD OF GENERATING AN OPTIMAL CLOCK BUFFER SET FOR MINIMIZING CLOCK SKEW IN BALANCED CLOCK TREES
58
Patent #:
Issue Dt:
01/07/2003
Application #:
09876854
Filing Dt:
06/07/2001
Publication #:
Pub Dt:
11/29/2001
Title:
PROGRAMMABLE WRITE SIGNAL GENERATOR
59
Patent #:
Issue Dt:
11/29/2005
Application #:
09878142
Filing Dt:
06/08/2001
Title:
LINE DRIVER FOR ASYMMETRIC DIGITAL SUBSCRIBER LINE SYSTEM
60
Patent #:
Issue Dt:
09/14/2004
Application #:
09878499
Filing Dt:
06/11/2001
Title:
HARD MACRO HAVING AN ANTENNA RULE VIOLATION FREE INPUT/OUTPUT PORTS
61
Patent #:
Issue Dt:
06/01/2004
Application #:
09878594
Filing Dt:
06/11/2001
Title:
BLOCK MOVE ENGINE WITH MACROBLOCK ADDRESSING MODES
62
Patent #:
Issue Dt:
03/13/2007
Application #:
09878604
Filing Dt:
06/11/2001
Title:
MULTI-STAGE FILTER CIRCUIT AND DIGITAL SIGNAL PROCESSING CIRCUIT EMPLOYING THE SAME
63
Patent #:
Issue Dt:
12/24/2002
Application #:
09878741
Filing Dt:
06/11/2001
Title:
OPTICAL INTENSITY MODIFIER
64
Patent #:
Issue Dt:
04/05/2005
Application #:
09878820
Filing Dt:
06/11/2001
Publication #:
Pub Dt:
12/12/2002
Title:
PLASMA TREATMENT SYSTEM
65
Patent #:
Issue Dt:
08/27/2002
Application #:
09879297
Filing Dt:
06/12/2001
Title:
RTL BACK ANNOTATOR
66
Patent #:
Issue Dt:
05/09/2006
Application #:
09879416
Filing Dt:
06/12/2001
Title:
DELAY-LOCKED LOOP WITH BUILT-IN SELF-TEST OF PHASE MARGIN
67
Patent #:
Issue Dt:
09/10/2002
Application #:
09879417
Filing Dt:
06/12/2001
Title:
METHOD OF ANALYZING STATIC CURRENT TEST VECTORS WITH REDUCED FILE SIZES FOR SEMICONDUCTOR INTEGRATED CIRCUITS
68
Patent #:
Issue Dt:
02/17/2004
Application #:
09879506
Filing Dt:
06/12/2001
Title:
METHOD OF ANALYZING STATIC CURRENT TEST VECTORS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
69
Patent #:
Issue Dt:
08/23/2005
Application #:
09879664
Filing Dt:
06/12/2001
Title:
MASK CORRECTION FOR PHOTOLITHOGRAPHIC PROCESSES
70
Patent #:
Issue Dt:
07/20/2004
Application #:
09879783
Filing Dt:
06/12/2001
Title:
COMPOSITION WITH EMC SHIELDING CHARACTERISTICS
71
Patent #:
Issue Dt:
09/28/2004
Application #:
09879824
Filing Dt:
06/11/2001
Title:
METHOD AND APPARATUS FOR CONTROLLING OSCILLATION AMPLITUDE AND OSCILLATION FREQUENCY OF CRYSTAL OSCILLATOR
72
Patent #:
Issue Dt:
03/15/2005
Application #:
09879841
Filing Dt:
06/12/2001
Title:
METHOD AND APPARATUS FOR OPTIMIZING THE TIMING OF INTEGRATED CIRCUITS
73
Patent #:
Issue Dt:
10/15/2002
Application #:
09879845
Filing Dt:
06/12/2001
Title:
EPSILON-DISCREPANT SELF-TEST TECHNIQUE
74
Patent #:
Issue Dt:
08/26/2003
Application #:
09879846
Filing Dt:
06/12/2001
Title:
MASK CORRECTION OPTIMIZATION
75
Patent #:
Issue Dt:
05/11/2004
Application #:
09880283
Filing Dt:
06/13/2001
Publication #:
Pub Dt:
07/18/2002
Title:
APPARATUS AND METHOD PROVIDING A MIRROR AVERAGING FUNCTION TO GENERATE A MIRROR SIGNAL FROM OPTICAL DATA ON AN OPTICAL DISC
76
Patent #:
Issue Dt:
08/08/2006
Application #:
09880291
Filing Dt:
06/13/2001
Title:
TRIPLE CONVERSION RF TUNER WITH SYNCHRONOUS LOCAL OSCILLATORS
77
Patent #:
Issue Dt:
06/11/2002
Application #:
09880491
Filing Dt:
06/13/2001
Title:
LOW POWER HIGH DENSITY ASYNCHRONOUS MEMORY ARCHITECTURE
78
Patent #:
Issue Dt:
05/06/2003
Application #:
09880492
Filing Dt:
06/13/2001
Title:
METHOD AND/OR ARCHITECTURE FOR IMPLEMENTING A VARIABLE GAIN AMPLIFIER CONTROL
79
Patent #:
Issue Dt:
09/17/2002
Application #:
09880607
Filing Dt:
06/12/2001
Title:
GENERATING STANDARD DELAY FORMAT FILES WITH CONDITIONAL PATH DELAY FOR DESIGNING INTEGRATED CIRCUITS
80
Patent #:
Issue Dt:
08/09/2005
Application #:
09880675
Filing Dt:
06/13/2001
Title:
SCAN METHOD FOR BUILT-IN-SELF-REPAIR (BISR)
81
Patent #:
Issue Dt:
07/05/2005
Application #:
09881151
Filing Dt:
06/14/2001
Title:
CONVERTER DEVICE
82
Patent #:
Issue Dt:
06/25/2002
Application #:
09881365
Filing Dt:
06/14/2001
Title:
FEEDBACK CONTROL OF CLOCK DUTY CYCLE
83
Patent #:
Issue Dt:
12/31/2002
Application #:
09881570
Filing Dt:
06/13/2001
Title:
SWITCHED-CAPACITOR DAC/CONTINOUS-TIME RECONSTRUCTION FILTER INTERFACE CIRCUIT
84
Patent #:
Issue Dt:
01/31/2006
Application #:
09881584
Filing Dt:
06/14/2001
Title:
SYSTEM AND METHOD FOR DATA VERIFICATION IN A RAID SYSTEM
85
Patent #:
Issue Dt:
08/19/2003
Application #:
09882114
Filing Dt:
06/15/2001
Title:
METHOD OF CONTROL CELL PLACEMENT TO MINIMIZE CONNECTION LENGTH AND CELL DELAY
86
Patent #:
Issue Dt:
01/07/2003
Application #:
09882124
Filing Dt:
06/14/2001
Title:
PROCESS FOR SELECTIVE POLISHING OF METAL-FILLED TRENCHES OF INTEGRATED CIRCUIT STRUCTURES
87
Patent #:
Issue Dt:
12/24/2002
Application #:
09882497
Filing Dt:
06/15/2001
Title:
AMPLIFIER CIRCUIT FOR LINE DRIVER
88
Patent #:
Issue Dt:
04/20/2004
Application #:
09882499
Filing Dt:
06/15/2001
Title:
AMPLIFIER AND LINE DRIVER FOR BROADBAND COMMUNICATIONS
89
Patent #:
Issue Dt:
11/23/2004
Application #:
09882786
Filing Dt:
06/15/2001
Title:
TESTING IMPLEMENTATION FOR SIGNAL CHARACTERIZATION
90
Patent #:
Issue Dt:
06/17/2003
Application #:
09882899
Filing Dt:
06/15/2001
Title:
METHOD FOR REDUCING SIMULATION OVERHEAD FOR EXTERNAL MODELS
91
Patent #:
Issue Dt:
02/11/2003
Application #:
09882977
Filing Dt:
06/15/2001
Title:
DESIGN SIMPLICITY OF VERY HIGH-SPEED SEMICONDUCTOR DEVICE
92
Patent #:
Issue Dt:
12/07/2004
Application #:
09883139
Filing Dt:
06/15/2001
Title:
METHOD TO SUPPORT GENERAL ENCLOSURE WIRING WHEN ASSOCIATING SES DATA WITH PHYSICAL DEVICE ON A FIBER CHANNEL LOOP WITH SOFT ADDRESSES
93
Patent #:
Issue Dt:
12/30/2003
Application #:
09883141
Filing Dt:
06/15/2001
Title:
DATA STORAGE SYSTEM AND METHOD FOR MANAGING CRITICAL DATA IN AN N-WAY MIRRORED STORAGE DEVICE USING FIRST AND SECOND SEQUENCE NUMBERS
94
Patent #:
Issue Dt:
01/13/2004
Application #:
09883142
Filing Dt:
06/15/2001
Title:
SYSTEM AND METHOD FOR READING AND WRITING N-WAY MIRRORED STORAGE DEVICES
95
Patent #:
Issue Dt:
05/23/2006
Application #:
09883733
Filing Dt:
06/18/2001
Title:
PSEUDO-RANDOM ONE-TO-ONE CIRCUIT SYNTHESIS
96
Patent #:
Issue Dt:
06/14/2005
Application #:
09883761
Filing Dt:
06/18/2001
Publication #:
Pub Dt:
06/27/2002
Title:
METHOD AND APPARATUS FOR ESTIMATION OF ERROR IN DATA RECOVERY SCHEMES
97
Patent #:
Issue Dt:
05/06/2003
Application #:
09884327
Filing Dt:
06/19/2001
Title:
INVERTING LEVEL SHIFTER WITH START-UP CIRCUIT
98
Patent #:
Issue Dt:
06/25/2002
Application #:
09884711
Filing Dt:
06/18/2001
Title:
UNIVERSAL TEST COUPON FOR PERFORMING PREQUALIFICATION TESTS ON SUBSTRATES
99
Patent #:
Issue Dt:
08/16/2005
Application #:
09884736
Filing Dt:
06/19/2001
Title:
PLASMA TREATMENT OF LOW DIELECTRIC CONSTANT DIELECTRIC MATERIAL TO FORM STRUCTURES USEFUL IN FORMATION OF METAL INTERCONNECTS AND/OR FILLED VIAS FOR INTEGRATED CIRCUIT STRUCTURE
100
Patent #:
Issue Dt:
10/01/2002
Application #:
09885299
Filing Dt:
06/20/2001
Title:
HIGH DENSITY SIGNAL ROUTING
Assignor
1
Exec Dt:
04/06/2007
Assignee
1
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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