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09/03/2002
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09885491
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06/20/2001
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09/09/2003
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09885497
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06/19/2001
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Title:
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04/15/2003
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09885589
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06/19/2001
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Title:
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METHOD IN INTEGRATING CLOCK TREE SYNTHESIS AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT DESIGN
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01/14/2003
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09885596
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06/19/2001
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METHOD OF GLOBAL PLACEMENT OF CONTROL CELLS AND HARDMAC PINS IN A DATAPATH MACRO FOR AN INTEGRATED CIRCUIT DESIGN
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07/06/2004
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09885687
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06/19/2001
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Title:
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SEMICONDUCTOR DEVICE PACKAGE SUBSTRATE PROBE FIXTURE
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11/18/2003
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09885896
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06/20/2001
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MODULAR COLLECTION OF SPARE GATES FOR USE IN HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS
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02/15/2005
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09887131
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06/22/2001
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03/11/2003
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09887838
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06/22/2001
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03/14/2002
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Title:
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TRANSCONDUCTANCE CONTINUOUS TIME FILTER CIRCUIT
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08/31/2004
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09888207
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06/22/2001
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POWER SEQUENCE PROTECTION FOR A LEVEL SHIFTER
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06/08/2004
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09888302
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06/21/2001
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WAFER HOLDER FOR BACKSIDE VIEWING FRONTSIDE PROBING ON AUTOMATED WAFER PROBE STATIONS
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11/19/2002
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09888866
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06/25/2001
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HIGH SPEED TCP/IP STACK IN SILICON
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05/06/2003
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09891648
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06/26/2001
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METHOD TO REDUCE POWER BUS TRANSIENTS IN SYNCHRONOUS INTEGRATED CIRCUITS
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07/01/2003
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09892241
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06/26/2001
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METHOD OF CONTROL CELL PLACEMENT FOR DATAPATH MACROS IN INTEGRATED CIRCUIT DESIGNS
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05/06/2003
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09892250
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06/27/2001
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH LOW DIELECTRIC CONSTANT MATERIAL BETWEEN CLOSELY SPACED APART METAL LINES
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03/11/2003
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09894210
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06/27/2001
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MICROSTRIP PACKAGE HAVING OPTIMIZED SIGNAL LINE IMPEDANCE CONTROL
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03/11/2003
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09894618
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06/27/2001
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09/30/2003
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09894643
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06/27/2001
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08/26/2003
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09895668
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06/29/2001
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METHOD FOR ESTIMATING CELL POROSITY OF HARDMACS
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11/02/2004
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09896363
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06/28/2001
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DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
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03/19/2002
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09896958
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06/29/2001
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SILICON CARBIDE CMOS CHANNEL
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01/20/2004
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09897517
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06/29/2001
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SHALLOW JUNCTION FORMATION
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11/05/2002
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09897828
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06/29/2001
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DEFECT SCREENING USING DELTA VDD
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01/06/2004
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09898194
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07/02/2001
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PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK
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08/15/2006
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09900940
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07/09/2001
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BLOCK MOVE ENGINE WITH SCALING AND/OR FILTERING FOR VIDEO OR GRAPHICS
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08/13/2002
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09906331
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07/16/2001
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METHOD OF COUPLING CAPACITANCE REDUCTION
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08/20/2002
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09907202
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07/17/2001
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SYSTEM AND METHOD FOR PROVIDING ROW REDUNDANCY WITH NO TIMING PENALTY FOR BUILT-IN-SELF-REPAIR (BISR) IN HIGH DENSITY MEMORIES
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12/03/2002
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09907424
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07/17/2001
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11/29/2005
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09909175
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07/19/2001
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ARRANGEMENT AND METHOD FOR CONTROLLING THE TRANSMISSION OF A LIGHT SIGNAL BASED ON INTENSITY OF A RECEIVED LIGHT SIGNAL
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03/15/2005
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09910088
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07/20/2001
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METHODS AND APPARATUS FOR BOOTING A HOST ADAPTER DEVICE DEVOID OF NONVOLATILE PROGRAM MEMORY
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12/02/2003
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09910464
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07/19/2001
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03/21/2002
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METHOD AND APPARATUS FOR READING AND WRITING A MULTILEVEL SIGNAL FROM AN OPTICAL DISC
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05/04/2004
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09910658
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07/20/2001
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METHODS AND APPARATUS FOR SAVING AND RESTORING SCATTER/GATHER LIST PROCESSING CONTEXT IN INTELLIGENT CONTROLLERS
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08/13/2002
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09915237
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07/25/2001
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04/25/2006
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07/26/2001
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METHOD FOR MULTIPROCESSOR COMMUNICATION WITHIN A SHARED MEMORY ARCHITECTURE
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05/09/2006
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09916924
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07/27/2001
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SYSTEM AND METHOD FOR STATE RESTORATION IN A DIAGNOSTIC MODULE FOR A HIGH-SPEED MICROPROCESSOR
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09/27/2005
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07/27/2001
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12/14/2004
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09916974
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07/27/2001
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08/15/2002
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11/04/2003
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09918011
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07/30/2001
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RANDOM REPLACEMENT GENERATOR FOR A CACHE CIRCUIT
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02/04/2003
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09918012
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07/30/2001
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SET-ASSOCIATIVE CACHE HAVING A CONFIGUABLE SPLIT AND UNIFIED MODE
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05/13/2003
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09918021
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07/30/2001
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METHOD AND APPARATUS FOR DEFINING CACHEABLE ADDRESS RANGES
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01/13/2004
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09918028
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07/30/2001
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METHODS AND STRUCTURE FOR RECURSIVE SCATTER/GATHER LISTS
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03/23/2004
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09918183
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07/30/2001
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01/22/2002
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07/30/2001
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06/28/2005
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07/31/2001
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PROTOCOL STACK ENCAPSULATION FOR VOICE PROCESSOR
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08/12/2003
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07/31/2001
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09/09/2003
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09921028
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08/02/2001
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APPARATUS AND METHOD OF PROTECTING A PROBE CARD DURING A SORT SEQUENCE
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08/16/2005
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08/02/2001
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02/15/2005
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08/06/2001
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MULTIPROCESSOR SYSTEM AND METHOD FOR SIMULTANEOUSLY PLACING ALL PROCESSORS INTO DEBUG MODE
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03/01/2005
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09923155
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08/06/2001
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05/20/2003
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08/06/2001
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08/20/2002
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09923657
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08/07/2001
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12/17/2002
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08/09/2001
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METHOD FOR SIMULTANEOUSLY FORMATION OF INTEGRATED CAPACITOR AND FUSE
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01/25/2005
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08/10/2001
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08/09/2005
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08/10/2001
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03/18/2003
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08/10/2001
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03/02/2004
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08/13/2001
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06/01/2004
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08/13/2001
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03/11/2003
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08/14/2001
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DIVIDER CIRCUIT, METHOD OF OPERATION THEREOF AND A PHASE-LOCKED LOOP CIRCUIT INCORPORATING THE SAME
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05/13/2003
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08/17/2001
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04/20/2004
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09932527
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08/17/2001
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PROCESS FOR REDUCING DEFECTS IN COPPER-FILLED VIAS AND/OR TRENCHES FORMED IN POROUS LOW-K DIELECTRIC MATERIAL
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07/06/2004
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08/17/2001
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CHARACTERISTIC IMPEDANCE EQUALIZER AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
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12/06/2005
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08/21/2001
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BZFLASH SUBCIRCUIT TO DYNAMICALLY SUPPLY BZ CODES FOR CONTROLLED IMPEDANCE BUFFER DEVELOPMENT, VERIFICATION AND SYSTEM LEVEL SIMULATIONS
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04/30/2002
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08/21/2001
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08/14/2007
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08/23/2001
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09/16/2004
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11/19/2002
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08/24/2001
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02/18/2003
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09940130
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08/27/2001
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01/03/2006
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09940754
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08/28/2001
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PROGRAMMABLE DIGITAL FILTER IMPLEMENTATION FOR LOSS-OF-SIGNAL DETECTION FOR SERIAL COMMUNICATIONS APPLICATIONS
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07/01/2003
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08/28/2001
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11/29/2005
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09941540
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08/29/2001
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PROGRAMMABLE POLARITY FOR HIGH SPEED DIFFERENTIAL INTERFACES
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05/24/2005
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09942220
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08/29/2001
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SYSTEM AND METHOD FOR OPTIMIZING THE ELECTROSTATIC REMOVAL OF A WORKPIECE FROM A CHUCK
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11/22/2005
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09942390
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08/29/2001
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Title:
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METHOD AND APPARATUS OF ESTABLISHING A DYNAMICALLY ADJUSTABLE LOOP OF DELAYED READ COMMANDS FOR COMPLETION IN A QUEUE BUFFER
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Patent #:
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Issue Dt:
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10/13/2009
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Application #:
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09943196
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Filing Dt:
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08/30/2001
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Title:
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ARRANGEMENT AND METHOD FOR FABRICATING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09943403
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Filing Dt:
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08/30/2001
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Title:
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SEMICONDUCTOR WAFER ARRANGEMENT AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09946000
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Filing Dt:
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09/04/2001
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Title:
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SYSTEM AND METHOD TO ELIMINATE RACE CONDITIONS IN INPUT/OUTPUT OPERATIONS FOR HIGH BANDWIDTH ARCHITECTURES
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09946033
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Filing Dt:
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09/04/2001
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Title:
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INTEGRATED CIRCUIT HAVING DEDICATED PROBE PADS FOR USE IN TESTING DENSELY PATTERNED BONDING PADS
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09946253
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Filing Dt:
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09/05/2001
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Title:
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CHEMICAL MECHANICAL POLISHING PAD
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09946759
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Filing Dt:
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09/04/2001
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Title:
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SENSE AMPLIFIER IMBALANCE COMPENSATION FOR MEMORY SELF- TIMED CIRCUITS
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09946895
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Filing Dt:
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09/05/2001
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Title:
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METHOD FOR CMP ENDPOINT DETECTION
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09947740
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Filing Dt:
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09/06/2001
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Title:
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OSCILLATOR HAVING UNIDIRECTIONAL CURRENT FLOW BETWEEN RESONANT CIRCUIT AND ACTIVE DEVICES
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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09948015
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Filing Dt:
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09/06/2001
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Publication #:
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Pub Dt:
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05/23/2002
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Title:
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APPARATUS AND METHOD FOR ACQUIRING PHASE LOCK TIMING RECOVERY IN A PARTIAL RESPONSE MAXIMUM LIKELIHOOD (PRML) CHANNEL
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09948190
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Filing Dt:
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09/07/2001
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Title:
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POWER REDISTRIBUTION BUS FOR A WIRE BONDED INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09948808
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Filing Dt:
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09/07/2001
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Title:
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METHOD OF TESTING THE PROCESSING OF A SEMICONDUCTOR WAFER ON A CMP APPARATUS
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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09949399
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Filing Dt:
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09/07/2001
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Title:
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METHOD AND SYSTEM FOR PERFORMING BUILT-IN SELF-TEST ROUTINES USING AN ACCUMULATOR TO STORE FAULT INFORMATION
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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09949974
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Filing Dt:
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09/10/2001
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Title:
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SET TOP BOX ACCESS HUB SYSTEM
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09950008
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Filing Dt:
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09/10/2001
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Title:
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ALKALINE COPPER PLATING
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09951252
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Filing Dt:
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09/13/2001
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Title:
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LOOP FILTER AND METHOD FOR GENERATING A CONTROL SIGNAL IN PHASE-LOCKED LOOP CIRCUITS
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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09951939
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Filing Dt:
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09/12/2001
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Title:
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A SYSTEM AND METHOD FOR SYNCHRONIZING A SELECTED MASTER CIRCUIT WITH A SLAVE CIRCUIT BY RECEIVING AND FORWARDING A CONTROL SIGNAL BETWEEN THE CIRCUITS AND OPERATING THE CIRCUITS BASED ON THEIR RECEIVED CONTROL SIGNAL
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09952343
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Filing Dt:
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09/14/2001
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Title:
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ION BEAM DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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09952540
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Filing Dt:
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09/14/2001
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Title:
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METHOD AND APPARATUS FOR DETERMINING TEMPERATURE OF A SEMICONDUCTOR WAFER DURING FABRICATION THEREOF
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09952790
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Filing Dt:
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09/11/2001
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Title:
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INTERGRATED CIRCUIT PROCESS MONITORING AND METROLOGY SYSTEM
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09953667
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Filing Dt:
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09/17/2001
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Title:
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METHOD AND APPARATUS FOR ESTIMATING STATE-DEPENDENT GATE LEAKAGE IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09953842
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Filing Dt:
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09/17/2001
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Title:
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ADDRESS DECODER WITH PSEUDO AND OR PSEUDO NAND GATE
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09955399
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Filing Dt:
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09/18/2001
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Title:
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STEPPED GAIN AMPLIFIER WITH IMPROVED ATTENUATION
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09955698
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Filing Dt:
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09/19/2001
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Title:
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CELL PLACEMENT IN INTEGRATED CIRCUIT CHIPS TO REMOVE CELL OVERLAP, ROW OVERFLOW AND OPTIMAL PLACEMENT OF DUAL HEIGHT CELLS
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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09956302
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Filing Dt:
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09/19/2001
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Title:
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METHOD FOR TESTING SEMICONDUCTOR DEVICES HAVING BUILT-IN SELF REPAIR (BISR) MEMORY
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09957106
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Filing Dt:
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09/20/2001
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Publication #:
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Pub Dt:
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03/20/2003
| | | | |
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Title:
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HARDWARE CHAIN PULL
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09957232
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Filing Dt:
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09/20/2001
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Title:
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METHOD AND APPARATUS FOR CALIBRATED PHASE-SHIFT NETWORKS
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09957410
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Filing Dt:
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09/20/2001
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Title:
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METHOD FOR RELIABILITY TESTING LEAKAGE CHARACTERISTICS IN AN ELECTRONIC CIRCUIT AND A TESTING DEVICE FOR ACCOMPLISHING THE SAME
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09957555
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Filing Dt:
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09/19/2001
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Title:
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LIQUID BASED AIR FILTRATION SYSTEM
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09960441
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Filing Dt:
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09/21/2001
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Title:
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ARRANGEMENT FOR MEASURING PRESSURE ON A SEMICONDUCTOR WAFER AND AN ASSOCIATED METHOD FOR FABRICATING A SEMICONDUCTOR WAFER
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|
|
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Patent #:
|
|
Issue Dt:
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05/30/2006
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Application #:
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09960560
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Filing Dt:
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09/21/2001
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Title:
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DIGITALLY CALIBRATED NARROWBAND FILTER WITH ANALOG CHANNEL COMPENSATION
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