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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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09960572
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Filing Dt:
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09/21/2001
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Title:
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BLOCK MOVE ENGINE WITH GAMMA AND COLOR CONVERSIONS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09960578
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Filing Dt:
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09/21/2001
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Title:
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VIDEO SAMPLING STRUCTURE CONVERSION IN BMME
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Patent #:
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Issue Dt:
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01/07/2003
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09960765
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Filing Dt:
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09/21/2001
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Title:
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INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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09960771
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Filing Dt:
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09/21/2001
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Title:
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INTEGRATION OF VIDEO PROCESSING INTO A BLOCK MOVE ENGINE
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Issue Dt:
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03/14/2006
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09961596
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Filing Dt:
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09/24/2001
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Title:
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HIGH RATE PRODUCT CODE DECODING FOR PARTIAL RESPONSE CHANNEL
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Issue Dt:
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04/13/2004
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09962541
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Filing Dt:
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09/24/2001
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Title:
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ALGORITHM FOR MAINTAINING MAXIMUM STREAMING PERFORMANCE OF MIRRORED DISKS
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Issue Dt:
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03/25/2003
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09962630
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Filing Dt:
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09/24/2001
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Title:
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VARIABLE DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTER
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Issue Dt:
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04/13/2004
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09962645
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Filing Dt:
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09/25/2001
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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BUFFER PARTITIONING FOR MANAGING MULTIPLE DATA STREAMS
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09964011
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Filing Dt:
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09/26/2001
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Title:
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VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
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Issue Dt:
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03/28/2006
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09964030
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Filing Dt:
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09/26/2001
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Title:
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METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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09/16/2003
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09964157
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Filing Dt:
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09/26/2001
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Title:
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METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS
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Issue Dt:
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12/26/2006
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09965292
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Filing Dt:
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09/27/2001
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Title:
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INFINIBAND ISOLATION BRIDGE MERGED WITH ARCHITECTURE OF AN INFINIBAND TRANSLATION BRIDGE
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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09966327
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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REDUCING THE EFFECT OF SIMULTANEOUS SWITCHING NOISE
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Issue Dt:
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05/18/2004
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Application #:
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09966651
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Filing Dt:
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09/28/2001
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Title:
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HIGH FREQUENCY ELECTROCHEMICAL DEPOSITION
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Patent #:
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Issue Dt:
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05/10/2005
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09966867
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Filing Dt:
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09/28/2001
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Title:
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SYSTEM AND METHOD FOR OPTIMIZING REMOTE DATA CONTENT DISTRIBUTION
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Issue Dt:
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04/27/2004
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09967074
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Filing Dt:
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09/28/2001
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Title:
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FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES
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Issue Dt:
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12/17/2002
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09967195
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Filing Dt:
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09/28/2001
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Title:
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TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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09968008
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Filing Dt:
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10/02/2001
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Title:
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INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Issue Dt:
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06/14/2005
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Application #:
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09968009
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Filing Dt:
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10/02/2001
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Title:
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INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Patent #:
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12/02/2003
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09968286
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Filing Dt:
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10/01/2001
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Title:
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DIE POWER DISTRIBUTION SYSTEM
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Patent #:
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Issue Dt:
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10/29/2002
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09968944
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Filing Dt:
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10/02/2001
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Title:
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METHOD OF MAKING INTERCONNECT STRUCTURE INCLUDING DIAMOND BARRIER LAYER
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Issue Dt:
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02/22/2005
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09969377
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Filing Dt:
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10/02/2001
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Title:
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IO BASED EMBEDDED PROCESSOR CLOCK SPEED CONTROL
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Patent #:
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Issue Dt:
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11/11/2003
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09970392
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10/03/2001
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Pub Dt:
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04/10/2003
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Title:
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LATENT DEFECT CLASSIFICATION SYSTEM
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Patent #:
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Issue Dt:
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10/29/2002
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09971329
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Filing Dt:
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10/04/2001
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Title:
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PHOTOLITHOGRAPHY OVERLAY CONTROL
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Patent #:
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Issue Dt:
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09/19/2006
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09972330
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Filing Dt:
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10/05/2001
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Title:
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REQUEST AND COMPLETION QUEUE LOAD BALANCING
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Patent #:
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Issue Dt:
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05/23/2006
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09973153
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Filing Dt:
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10/09/2001
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Title:
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WEB BASED OLA MEMORY GENERATOR
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Patent #:
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Issue Dt:
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07/20/2004
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09973267
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Filing Dt:
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10/08/2001
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Title:
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FIELD PROGRAMMABLE UNIVERSAL SERIAL BUS APPLICATION SPECIFIC INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09974251
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Filing Dt:
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10/10/2001
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Title:
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LIQUID LEVEL HEIGHT MEASUREMENT SYSTEM
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Patent #:
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Issue Dt:
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10/03/2006
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09975293
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Filing Dt:
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10/11/2001
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Title:
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CONSTRUCTION OF AN OPTIMIZED SEC-DED CODE AND LOGIC FOR SOFT ERRORS IN SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09975871
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Filing Dt:
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10/12/2001
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Title:
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INTEGRATED CIRCUIT PACKAGE VIA
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09978141
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Filing Dt:
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10/15/2001
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Title:
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AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09981154
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Filing Dt:
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10/16/2001
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Title:
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DEEP SUBMICRON SILICIDE BLOCKING
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Issue Dt:
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06/15/2004
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Application #:
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09981200
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Filing Dt:
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10/17/2001
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Title:
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VORTEX UNIT FOR PROVIDING A DESIRED ENVIRONMENT FOR A SEMICONDUCTOR PROCESS
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Patent #:
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Issue Dt:
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03/07/2006
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09981474
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Filing Dt:
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10/17/2001
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Title:
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PRESCALER ARCHITECTURE CAPABLE OF NON INTEGER DIVISION
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09986912
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Filing Dt:
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11/13/2001
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Title:
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INTEGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
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Issue Dt:
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07/15/2003
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Application #:
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09990698
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Filing Dt:
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11/09/2001
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Title:
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METHODS AND STRUCTURE FOR PIPELINED READ RETURN CONTROL IN A SHARED RAM CONTROLLER
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09991063
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Filing Dt:
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11/21/2001
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Title:
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AUTOMATIC NEXUS RESTORE
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09991187
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Filing Dt:
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11/14/2001
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Title:
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METHOD OF FORMING METAL FUSES IN CMOS PROCESSES WITH COPPER INTERCONNECT
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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09991202
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Filing Dt:
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11/14/2001
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Title:
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SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09991238
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Filing Dt:
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11/09/2001
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Title:
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METHODS AND STRUCTURE FOR SEQUENCING OF ACTIVATION COMMANDS IN A HIGH-PERFORMANCE DDR SDRAM MEMORY CONTROLLER
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09991574
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Filing Dt:
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11/20/2001
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Title:
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CHANGING CLOCK DELAYS IN AN INTEGRATED CIRCUIT FOR SKEW OPTIMIZATION
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09992041
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Filing Dt:
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11/16/2001
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Title:
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RATE 64/65 (D=0, G=11/I=10) RUN LENGTH LIMITED MODULATION CODE
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Patent #:
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Issue Dt:
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02/28/2006
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09992043
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Filing Dt:
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11/16/2001
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Title:
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SHARED EMBEDDED TRACE MACROCELL
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Issue Dt:
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09/07/2004
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09993015
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Filing Dt:
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11/05/2001
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Title:
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METHOD AND APPARATUS FOR AUTOMATIC MARKING OF INTERGRATED CIRCUITS IN WAFER SCALE TESTING
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Issue Dt:
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05/06/2003
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09993466
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Filing Dt:
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11/05/2001
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Title:
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CHIP-OVER-CHIP INTEGRATED CIRCUIT PACKAGE
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Issue Dt:
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04/27/2004
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09994082
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Filing Dt:
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11/21/2001
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Pub Dt:
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10/31/2002
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Title:
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SYSTEM AND METHOD EMPLOYING A STATIC LOGICAL IDENTIFIER IN CONJUCTION WITH A LOOK UP TABLE TO PROVIDE ACCESS TO A TARGET
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Issue Dt:
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04/15/2003
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09994083
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11/21/2001
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Title:
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METHOD AND APPARATUS FOR IMPROVING THE TOLERANCE OF INTEGRATED RESISTORS
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10/18/2005
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09994090
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11/16/2001
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Pub Dt:
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10/31/2002
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SELECTABLE LOGICAL IDENTIFIER MAPPING
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06/01/2004
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09994459
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11/26/2001
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Title:
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CIRCULAR BUFFER CONTROL CIRCUIT AND METHOD OF OPERATION THEREOF
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Issue Dt:
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02/03/2004
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09994517
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11/27/2001
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Pub Dt:
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05/29/2003
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Title:
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COMPILED VARIABLE INTERNAL SELF TIME MEMORY
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Issue Dt:
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12/30/2003
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Application #:
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09994567
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Filing Dt:
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11/27/2001
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Title:
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HIGH DENSITY INPUT OUTPUT
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Issue Dt:
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08/10/2004
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09996042
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11/28/2001
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Pub Dt:
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05/29/2003
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Title:
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FAST SAMPLING TEST BENCH
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Issue Dt:
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11/09/2004
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Application #:
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09996118
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Filing Dt:
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11/27/2001
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Title:
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LOW RESISTANCE METAL INTERCONNECT LINES AND A PROCESS FOR FABRICATING THEM
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Issue Dt:
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05/25/2004
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09996122
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Filing Dt:
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11/27/2001
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Title:
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METHODS AND STRUCTURE FOR USING A HIGHER FREQUENCY CLOCK TO SHORTEN A MASTER DELAY LINE
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Issue Dt:
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07/27/2004
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09997071
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Filing Dt:
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11/28/2001
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Title:
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PROCESS FOR INHIBITING EDGE PEELING OF COATING ON SEMICONDUCTOR SUBSTRATE DURING FORMATION OF INTEGRATED CIRCUIT STRUCTURE THEREON
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06/01/2004
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09997757
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11/30/2001
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Title:
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ENHANCED FAULT COVERAGE
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07/06/2004
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09997776
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Filing Dt:
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11/30/2001
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Pub Dt:
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06/05/2003
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Title:
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METHOD AND APPARATUS FOR ACCESSING ROM PCI MEMORY ABOVE 64 K
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02/28/2006
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09997888
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Filing Dt:
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11/29/2001
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Title:
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DISTRIBUTED DELAY PREDICTION OF MULTI-MILLION GATE DEEP SUB-MICRON ASIC DESIGNS
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02/10/2004
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09997889
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11/30/2001
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Pub Dt:
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10/31/2002
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Title:
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SYSTEM AND METHOD EMPLOYING A DYNAMIC LOGICAL IDENTIFIER
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12/24/2002
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09998671
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Filing Dt:
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11/29/2001
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Title:
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DYNAMIC SUPPLY CONTROL FOR LINE DRIVER
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Issue Dt:
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08/31/2004
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09998738
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10/31/2001
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Title:
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INTEGRATED DYNAMIC LOAD BALANCING BY AN INPUT/OUTPUT INTERFACE
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01/30/2007
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09999330
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10/25/2001
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Title:
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INTEGER BASED ADAPTIVE ALGORITHM FOR DE-JITTER BUFFER CONTROL
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02/07/2006
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09999375
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10/31/2001
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EMBEDDED INPUT/OUTPUT INTERFACE FAILOVER
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11/02/2004
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09999391
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10/31/2001
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Title:
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INTEGRATED DYNAMIC MULTIPATHING FILTER
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04/22/2003
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09999726
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10/24/2001
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Title:
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CLOCK GATING CELL FOR USE IN A CELL LIBRARY
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05/11/2004
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09999848
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10/24/2001
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SHALLOW TRENCH ISOLATION STRUCTURE FOR LASER THERMAL PROCESSING
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06/24/2003
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09999872
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10/19/2001
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Title:
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FIRST STAGE SALICIDATION OF COBALT DURING COBALT DEPOSITION OR SUBSEQUENT TI OR TIN CAP DEPOSITION USING ENERGY FROM A DIRECTIONAL PLASMA
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12/09/2003
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10000243
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10/18/2001
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FAST FREE MEMORY ADDRESS CONTROLLER
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05/31/2005
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10000597
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10/24/2001
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SCAN CHAIN TESTING OF INTEGRATED CIRCUITS WITH HARD-CORES
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10/14/2003
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10000716
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10/31/2001
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Title:
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AHB SEGMENTATION BRIDGE BETWEEN BUSSES HAVING DIFFERENT NATIVE DATA WIDTHS
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05/10/2005
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10001518
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10/30/2001
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POWER MONITORING AND REDUCTION FOR EMBEDDED IO PROCESSORS
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12/17/2002
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10001839
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11/21/2001
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Title:
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DIRECT ATTACH OF INTERRUPT CONTROLLER TO PROCESSOR MODULE
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12/13/2005
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10001875
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11/19/2001
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05/22/2003
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Title:
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MECHANISM FOR ENCODING AND DECODING UPGRADEABLE RPC/XDR STRUCTURES
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04/05/2005
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10001889
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11/19/2001
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05/22/2003
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METHOD FOR THE ACCELERATION AND SIMPLIFICATION OF FILE SYSTEM LOGGING TECHNIQUES USING STORAGE DEVICE SNAPSHOTS
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Issue Dt:
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09/16/2003
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Application #:
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10002413
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Filing Dt:
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10/23/2001
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Title:
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LOW TEMPERATURE COEFFICIENT RESISTOR
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10002479
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Filing Dt:
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11/15/2001
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Title:
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METHOD AND APPARATUS FOR ENHANCING CORRECTION POWER OF REVERSE ORDER ERROR CORRECTION CODES
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10002499
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Filing Dt:
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11/02/2001
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Title:
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SELF-REPAIRING INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10002672
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Filing Dt:
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10/23/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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HEADER DETECT CONFIGURATION WITHIN A DVD-RAM READ DEVICE AND METHODS OF ACQUIRING AND MAINTAINING PHASE LOCK IN A WOBBLE PHASE LOCK LOOP
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Patent #:
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Issue Dt:
|
03/04/2003
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Application #:
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10002831
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Filing Dt:
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10/26/2001
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Title:
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PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL
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Patent #:
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|
Issue Dt:
|
09/02/2003
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Application #:
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10002981
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Filing Dt:
|
10/26/2001
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Title:
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PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE COMPRISING LAYER OF LOW K DIELECTRIC MATERIAL HAVING ANTIREFLECTIVE PROPERTIES IN AN UPPER SURFACE
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Patent #:
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Issue Dt:
|
08/13/2002
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Application #:
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10003763
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Filing Dt:
|
11/01/2001
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Title:
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NOISE REDUCTION AUTO PHASING CIRCUIT FOR SWITCHED CAPACITOR CIRCUITS
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Patent #:
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|
Issue Dt:
|
12/23/2003
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Application #:
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10003823
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Filing Dt:
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10/31/2001
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Title:
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VERILOG TO VITAL TRANSLATOR
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Patent #:
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|
Issue Dt:
|
05/24/2005
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Application #:
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10004208
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Filing Dt:
|
11/01/2001
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Title:
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MULTIPLE MEMORY SYSTEM SUPPORT THROUGH SEGMENT ASSIGNMENT
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Patent #:
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|
Issue Dt:
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05/20/2003
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Application #:
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10004461
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Filing Dt:
|
11/01/2001
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Title:
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METHOD FOR CREATING SELF-ALIGNED ALLOY CAPPING LAYERS FOR COPPER INTERCONNECT STRUCTURES
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Patent #:
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|
Issue Dt:
|
07/27/2004
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Application #:
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10005062
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Filing Dt:
|
12/03/2001
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Title:
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METHOD AND SYSTEM FOR IMPLEMENTING INCREMENTAL CHANGE TO CIRCUIT DESIGN
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|
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Patent #:
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|
Issue Dt:
|
09/23/2003
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Application #:
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10005097
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Filing Dt:
|
12/05/2001
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Title:
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DIE ATTACH BACKING GRINDING
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|
|
Patent #:
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|
Issue Dt:
|
01/11/2005
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Application #:
|
10006162
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Filing Dt:
|
12/06/2001
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Title:
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METHOD AND APPARATUS TO MANAGE INDEPENDENT MEMORY SYSTEMS AS A SHARED VOLUME
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|
|
Patent #:
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|
Issue Dt:
|
10/26/2004
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Application #:
|
10006398
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Filing Dt:
|
11/30/2001
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Title:
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ALIGNMENT PROCESS FOR INTEGRATED CIRCUIT STRUCTURES ON SEMICONDUCTOR SUBSTRATE USING SCATTEROMETRY MEASUREMENTS OF LATENT IMAGES IN SPACED APART TEST FIELDS ON SUBSTRATE
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|
|
Patent #:
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|
Issue Dt:
|
04/22/2003
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Application #:
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10006540
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Filing Dt:
|
11/30/2001
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Title:
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METHOD FOR PREVENTING BORDERLESS CONTACT TO WELL LEAKAGE
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Patent #:
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|
Issue Dt:
|
02/14/2006
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Application #:
|
10007245
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Filing Dt:
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10/22/2001
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Title:
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DATA READY INDICATOR BETWEEN DIFFERENT CLOCK DOMAINS
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|
|
Patent #:
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|
Issue Dt:
|
03/25/2003
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Application #:
|
10007405
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Filing Dt:
|
12/04/2001
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Title:
|
PROCESS FOR TREATING POROUS LOW K DIELECTRIC MATERIAL IN DAMASCENE STRUCTURE TO FORM A NON-POROUS DIELECTRIC DIFFUSION BARRIER LAYER ON ETCHED VIA AND TRENCH SURFACES IN THE POROUS LOW K DIELECTRIC MATERIAL
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Patent #:
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|
Issue Dt:
|
11/18/2003
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Application #:
|
10008089
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Filing Dt:
|
11/13/2001
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Title:
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DIRECT TRANSFORMATION OF ENGINEERING CHANGE ORDERS TO SYNTHESIZED IC CHIP DESIGNS
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Patent #:
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|
Issue Dt:
|
03/16/2004
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Application #:
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10008170
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Filing Dt:
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10/19/2001
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Title:
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HIGH SPEED LOW NOISE TRANSISTOR
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|
Patent #:
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|
Issue Dt:
|
03/28/2006
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Application #:
|
10011153
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Filing Dt:
|
12/05/2001
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Title:
|
DSL LINE INTERFACE HAVING LOW-PASS FILTER CHARACTERISTIC WITH REDUCED EXTERNAL COMPONENTS
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|
Patent #:
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|
Issue Dt:
|
06/20/2006
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Application #:
|
10011796
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Filing Dt:
|
12/05/2001
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Title:
|
LONG PATH AT-SPEED TESTING
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|
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Patent #:
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|
Issue Dt:
|
01/03/2006
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Application #:
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10012257
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Filing Dt:
|
11/08/2001
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Publication #:
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|
Pub Dt:
|
09/12/2002
| | | | |
Title:
|
WRITE COMPENSATION FOR DATA STORAGE AND COMMUNICATION SYSTEMS
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|
|
Patent #:
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|
Issue Dt:
|
07/29/2003
|
Application #:
|
10012616
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Filing Dt:
|
12/12/2001
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Title:
|
METHOD AND APPARATUS FOR VARYING TARGET BEHAVIOR IN A SCSI ENVIRONMENT
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|
|
Patent #:
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|
Issue Dt:
|
01/01/2008
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Application #:
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10012821
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Filing Dt:
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12/10/2001
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Title:
|
REACTOR SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
11/11/2003
|
Application #:
|
10012986
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Filing Dt:
|
12/05/2001
|
Title:
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METHODS AND STRUCTURE FOR READ DATA SYNCHRONIZATION WITH MINIMAL LATENCY
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|
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Patent #:
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|
Issue Dt:
|
09/02/2003
|
Application #:
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10013572
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Filing Dt:
|
12/11/2001
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Publication #:
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|
Pub Dt:
|
06/12/2003
| | | | |
Title:
|
INTEGRATED INDUCTOR IN SEMICONDUCTOR MANUFACTURING
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|