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Reel/Frame:033102/0270   Pages: 90
Recorded: 06/06/2014
Attorney Dkt #:040981-0072
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 3258
Page 19 of 33
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
Patent #:
Issue Dt:
11/29/2005
Application #:
09960572
Filing Dt:
09/21/2001
Title:
BLOCK MOVE ENGINE WITH GAMMA AND COLOR CONVERSIONS
2
Patent #:
Issue Dt:
05/25/2004
Application #:
09960578
Filing Dt:
09/21/2001
Title:
VIDEO SAMPLING STRUCTURE CONVERSION IN BMME
3
Patent #:
Issue Dt:
01/07/2003
Application #:
09960765
Filing Dt:
09/21/2001
Title:
INDIUM FIELD IMPLANT FOR PUNCHTHROUGH PROTECTION IN SEMICONDUCTOR DEVICES
4
Patent #:
Issue Dt:
12/27/2005
Application #:
09960771
Filing Dt:
09/21/2001
Title:
INTEGRATION OF VIDEO PROCESSING INTO A BLOCK MOVE ENGINE
5
Patent #:
Issue Dt:
03/14/2006
Application #:
09961596
Filing Dt:
09/24/2001
Title:
HIGH RATE PRODUCT CODE DECODING FOR PARTIAL RESPONSE CHANNEL
6
Patent #:
Issue Dt:
04/13/2004
Application #:
09962541
Filing Dt:
09/24/2001
Title:
ALGORITHM FOR MAINTAINING MAXIMUM STREAMING PERFORMANCE OF MIRRORED DISKS
7
Patent #:
Issue Dt:
03/25/2003
Application #:
09962630
Filing Dt:
09/24/2001
Title:
VARIABLE DYNAMIC RANGE ANALOG-TO-DIGITAL CONVERTER
8
Patent #:
Issue Dt:
04/13/2004
Application #:
09962645
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
03/27/2003
Title:
BUFFER PARTITIONING FOR MANAGING MULTIPLE DATA STREAMS
9
Patent #:
Issue Dt:
11/04/2003
Application #:
09964011
Filing Dt:
09/26/2001
Title:
VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN
10
Patent #:
Issue Dt:
03/28/2006
Application #:
09964030
Filing Dt:
09/26/2001
Title:
METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN
11
Patent #:
Issue Dt:
09/16/2003
Application #:
09964157
Filing Dt:
09/26/2001
Title:
METHOD AND APPARATUS FOR THE USE OF EMBEDDED RESISTANCE TO LINEARIZE AND IMPROVE THE MATCHING PROPERTIES OF TRANSISTORS
12
Patent #:
Issue Dt:
12/26/2006
Application #:
09965292
Filing Dt:
09/27/2001
Title:
INFINIBAND ISOLATION BRIDGE MERGED WITH ARCHITECTURE OF AN INFINIBAND TRANSLATION BRIDGE
13
Patent #:
Issue Dt:
05/09/2006
Application #:
09966327
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
09/05/2002
Title:
REDUCING THE EFFECT OF SIMULTANEOUS SWITCHING NOISE
14
Patent #:
Issue Dt:
05/18/2004
Application #:
09966651
Filing Dt:
09/28/2001
Title:
HIGH FREQUENCY ELECTROCHEMICAL DEPOSITION
15
Patent #:
Issue Dt:
05/10/2005
Application #:
09966867
Filing Dt:
09/28/2001
Title:
SYSTEM AND METHOD FOR OPTIMIZING REMOTE DATA CONTENT DISTRIBUTION
16
Patent #:
Issue Dt:
04/27/2004
Application #:
09967074
Filing Dt:
09/28/2001
Title:
FABRICATION OF METAL CONTACTS FOR DEEP-SUBMICRON TECHNOLOGIES
17
Patent #:
Issue Dt:
12/17/2002
Application #:
09967195
Filing Dt:
09/28/2001
Title:
TRANSMISSION EQUALIZATION SYSTEM AND AN INTEGRATED CIRCUIT PACKAGE EMPLOYING THE SAME
18
Patent #:
Issue Dt:
06/14/2005
Application #:
09968008
Filing Dt:
10/02/2001
Title:
INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
19
Patent #:
Issue Dt:
06/14/2005
Application #:
09968009
Filing Dt:
10/02/2001
Title:
INTERGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
20
Patent #:
Issue Dt:
12/02/2003
Application #:
09968286
Filing Dt:
10/01/2001
Title:
DIE POWER DISTRIBUTION SYSTEM
21
Patent #:
Issue Dt:
10/29/2002
Application #:
09968944
Filing Dt:
10/02/2001
Title:
METHOD OF MAKING INTERCONNECT STRUCTURE INCLUDING DIAMOND BARRIER LAYER
22
Patent #:
Issue Dt:
02/22/2005
Application #:
09969377
Filing Dt:
10/02/2001
Title:
IO BASED EMBEDDED PROCESSOR CLOCK SPEED CONTROL
23
Patent #:
Issue Dt:
11/11/2003
Application #:
09970392
Filing Dt:
10/03/2001
Publication #:
Pub Dt:
04/10/2003
Title:
LATENT DEFECT CLASSIFICATION SYSTEM
24
Patent #:
Issue Dt:
10/29/2002
Application #:
09971329
Filing Dt:
10/04/2001
Title:
PHOTOLITHOGRAPHY OVERLAY CONTROL
25
Patent #:
Issue Dt:
09/19/2006
Application #:
09972330
Filing Dt:
10/05/2001
Title:
REQUEST AND COMPLETION QUEUE LOAD BALANCING
26
Patent #:
Issue Dt:
05/23/2006
Application #:
09973153
Filing Dt:
10/09/2001
Title:
WEB BASED OLA MEMORY GENERATOR
27
Patent #:
Issue Dt:
07/20/2004
Application #:
09973267
Filing Dt:
10/08/2001
Title:
FIELD PROGRAMMABLE UNIVERSAL SERIAL BUS APPLICATION SPECIFIC INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
28
Patent #:
Issue Dt:
02/04/2003
Application #:
09974251
Filing Dt:
10/10/2001
Title:
LIQUID LEVEL HEIGHT MEASUREMENT SYSTEM
29
Patent #:
Issue Dt:
10/03/2006
Application #:
09975293
Filing Dt:
10/11/2001
Title:
CONSTRUCTION OF AN OPTIMIZED SEC-DED CODE AND LOGIC FOR SOFT ERRORS IN SEMICONDUCTOR MEMORIES
30
Patent #:
Issue Dt:
04/29/2003
Application #:
09975871
Filing Dt:
10/12/2001
Title:
INTEGRATED CIRCUIT PACKAGE VIA
31
Patent #:
Issue Dt:
08/16/2005
Application #:
09978141
Filing Dt:
10/15/2001
Title:
AUTOMATIC METHOD AND SYSTEM FOR INSTANTIATING BUILT-IN -TEST (BIST) MODULES IN ASIC MEMORY DESIGNS
32
Patent #:
Issue Dt:
07/01/2003
Application #:
09981154
Filing Dt:
10/16/2001
Title:
DEEP SUBMICRON SILICIDE BLOCKING
33
Patent #:
Issue Dt:
06/15/2004
Application #:
09981200
Filing Dt:
10/17/2001
Title:
VORTEX UNIT FOR PROVIDING A DESIRED ENVIRONMENT FOR A SEMICONDUCTOR PROCESS
34
Patent #:
Issue Dt:
03/07/2006
Application #:
09981474
Filing Dt:
10/17/2001
Title:
PRESCALER ARCHITECTURE CAPABLE OF NON INTEGER DIVISION
35
Patent #:
Issue Dt:
07/15/2003
Application #:
09986912
Filing Dt:
11/13/2001
Title:
INTEGRATED DESIGN SYSTEM AND METHOD FOR REDUCING AND AVOIDING CROSSTALK
36
Patent #:
Issue Dt:
07/15/2003
Application #:
09990698
Filing Dt:
11/09/2001
Title:
METHODS AND STRUCTURE FOR PIPELINED READ RETURN CONTROL IN A SHARED RAM CONTROLLER
37
Patent #:
Issue Dt:
01/28/2003
Application #:
09991063
Filing Dt:
11/21/2001
Title:
AUTOMATIC NEXUS RESTORE
38
Patent #:
Issue Dt:
12/16/2003
Application #:
09991187
Filing Dt:
11/14/2001
Title:
METHOD OF FORMING METAL FUSES IN CMOS PROCESSES WITH COPPER INTERCONNECT
39
Patent #:
Issue Dt:
02/21/2006
Application #:
09991202
Filing Dt:
11/14/2001
Title:
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
40
Patent #:
Issue Dt:
09/02/2003
Application #:
09991238
Filing Dt:
11/09/2001
Title:
METHODS AND STRUCTURE FOR SEQUENCING OF ACTIVATION COMMANDS IN A HIGH-PERFORMANCE DDR SDRAM MEMORY CONTROLLER
41
Patent #:
Issue Dt:
04/15/2003
Application #:
09991574
Filing Dt:
11/20/2001
Title:
CHANGING CLOCK DELAYS IN AN INTEGRATED CIRCUIT FOR SKEW OPTIMIZATION
42
Patent #:
Issue Dt:
11/05/2002
Application #:
09992041
Filing Dt:
11/16/2001
Title:
RATE 64/65 (D=0, G=11/I=10) RUN LENGTH LIMITED MODULATION CODE
43
Patent #:
Issue Dt:
02/28/2006
Application #:
09992043
Filing Dt:
11/16/2001
Title:
SHARED EMBEDDED TRACE MACROCELL
44
Patent #:
Issue Dt:
09/07/2004
Application #:
09993015
Filing Dt:
11/05/2001
Title:
METHOD AND APPARATUS FOR AUTOMATIC MARKING OF INTERGRATED CIRCUITS IN WAFER SCALE TESTING
45
Patent #:
Issue Dt:
05/06/2003
Application #:
09993466
Filing Dt:
11/05/2001
Title:
CHIP-OVER-CHIP INTEGRATED CIRCUIT PACKAGE
46
Patent #:
Issue Dt:
04/27/2004
Application #:
09994082
Filing Dt:
11/21/2001
Publication #:
Pub Dt:
10/31/2002
Title:
SYSTEM AND METHOD EMPLOYING A STATIC LOGICAL IDENTIFIER IN CONJUCTION WITH A LOOK UP TABLE TO PROVIDE ACCESS TO A TARGET
47
Patent #:
Issue Dt:
04/15/2003
Application #:
09994083
Filing Dt:
11/21/2001
Title:
METHOD AND APPARATUS FOR IMPROVING THE TOLERANCE OF INTEGRATED RESISTORS
48
Patent #:
Issue Dt:
10/18/2005
Application #:
09994090
Filing Dt:
11/16/2001
Publication #:
Pub Dt:
10/31/2002
Title:
SELECTABLE LOGICAL IDENTIFIER MAPPING
49
Patent #:
Issue Dt:
06/01/2004
Application #:
09994459
Filing Dt:
11/26/2001
Title:
CIRCULAR BUFFER CONTROL CIRCUIT AND METHOD OF OPERATION THEREOF
50
Patent #:
Issue Dt:
02/03/2004
Application #:
09994517
Filing Dt:
11/27/2001
Publication #:
Pub Dt:
05/29/2003
Title:
COMPILED VARIABLE INTERNAL SELF TIME MEMORY
51
Patent #:
Issue Dt:
12/30/2003
Application #:
09994567
Filing Dt:
11/27/2001
Title:
HIGH DENSITY INPUT OUTPUT
52
Patent #:
Issue Dt:
08/10/2004
Application #:
09996042
Filing Dt:
11/28/2001
Publication #:
Pub Dt:
05/29/2003
Title:
FAST SAMPLING TEST BENCH
53
Patent #:
Issue Dt:
11/09/2004
Application #:
09996118
Filing Dt:
11/27/2001
Title:
LOW RESISTANCE METAL INTERCONNECT LINES AND A PROCESS FOR FABRICATING THEM
54
Patent #:
Issue Dt:
05/25/2004
Application #:
09996122
Filing Dt:
11/27/2001
Title:
METHODS AND STRUCTURE FOR USING A HIGHER FREQUENCY CLOCK TO SHORTEN A MASTER DELAY LINE
55
Patent #:
Issue Dt:
07/27/2004
Application #:
09997071
Filing Dt:
11/28/2001
Title:
PROCESS FOR INHIBITING EDGE PEELING OF COATING ON SEMICONDUCTOR SUBSTRATE DURING FORMATION OF INTEGRATED CIRCUIT STRUCTURE THEREON
56
Patent #:
Issue Dt:
06/01/2004
Application #:
09997757
Filing Dt:
11/30/2001
Title:
ENHANCED FAULT COVERAGE
57
Patent #:
Issue Dt:
07/06/2004
Application #:
09997776
Filing Dt:
11/30/2001
Publication #:
Pub Dt:
06/05/2003
Title:
METHOD AND APPARATUS FOR ACCESSING ROM PCI MEMORY ABOVE 64 K
58
Patent #:
Issue Dt:
02/28/2006
Application #:
09997888
Filing Dt:
11/29/2001
Title:
DISTRIBUTED DELAY PREDICTION OF MULTI-MILLION GATE DEEP SUB-MICRON ASIC DESIGNS
59
Patent #:
Issue Dt:
02/10/2004
Application #:
09997889
Filing Dt:
11/30/2001
Publication #:
Pub Dt:
10/31/2002
Title:
SYSTEM AND METHOD EMPLOYING A DYNAMIC LOGICAL IDENTIFIER
60
Patent #:
Issue Dt:
12/24/2002
Application #:
09998671
Filing Dt:
11/29/2001
Title:
DYNAMIC SUPPLY CONTROL FOR LINE DRIVER
61
Patent #:
Issue Dt:
08/31/2004
Application #:
09998738
Filing Dt:
10/31/2001
Title:
INTEGRATED DYNAMIC LOAD BALANCING BY AN INPUT/OUTPUT INTERFACE
62
Patent #:
Issue Dt:
01/30/2007
Application #:
09999330
Filing Dt:
10/25/2001
Title:
INTEGER BASED ADAPTIVE ALGORITHM FOR DE-JITTER BUFFER CONTROL
63
Patent #:
Issue Dt:
02/07/2006
Application #:
09999375
Filing Dt:
10/31/2001
Title:
EMBEDDED INPUT/OUTPUT INTERFACE FAILOVER
64
Patent #:
Issue Dt:
11/02/2004
Application #:
09999391
Filing Dt:
10/31/2001
Title:
INTEGRATED DYNAMIC MULTIPATHING FILTER
65
Patent #:
Issue Dt:
04/22/2003
Application #:
09999726
Filing Dt:
10/24/2001
Title:
CLOCK GATING CELL FOR USE IN A CELL LIBRARY
66
Patent #:
Issue Dt:
05/11/2004
Application #:
09999848
Filing Dt:
10/24/2001
Title:
SHALLOW TRENCH ISOLATION STRUCTURE FOR LASER THERMAL PROCESSING
67
Patent #:
Issue Dt:
06/24/2003
Application #:
09999872
Filing Dt:
10/19/2001
Title:
FIRST STAGE SALICIDATION OF COBALT DURING COBALT DEPOSITION OR SUBSEQUENT TI OR TIN CAP DEPOSITION USING ENERGY FROM A DIRECTIONAL PLASMA
68
Patent #:
Issue Dt:
12/09/2003
Application #:
10000243
Filing Dt:
10/18/2001
Title:
FAST FREE MEMORY ADDRESS CONTROLLER
69
Patent #:
Issue Dt:
05/31/2005
Application #:
10000597
Filing Dt:
10/24/2001
Title:
SCAN CHAIN TESTING OF INTEGRATED CIRCUITS WITH HARD-CORES
70
Patent #:
Issue Dt:
10/14/2003
Application #:
10000716
Filing Dt:
10/31/2001
Title:
AHB SEGMENTATION BRIDGE BETWEEN BUSSES HAVING DIFFERENT NATIVE DATA WIDTHS
71
Patent #:
Issue Dt:
05/10/2005
Application #:
10001518
Filing Dt:
10/30/2001
Title:
POWER MONITORING AND REDUCTION FOR EMBEDDED IO PROCESSORS
72
Patent #:
Issue Dt:
12/17/2002
Application #:
10001839
Filing Dt:
11/21/2001
Title:
DIRECT ATTACH OF INTERRUPT CONTROLLER TO PROCESSOR MODULE
73
Patent #:
Issue Dt:
12/13/2005
Application #:
10001875
Filing Dt:
11/19/2001
Publication #:
Pub Dt:
05/22/2003
Title:
MECHANISM FOR ENCODING AND DECODING UPGRADEABLE RPC/XDR STRUCTURES
74
Patent #:
Issue Dt:
04/05/2005
Application #:
10001889
Filing Dt:
11/19/2001
Publication #:
Pub Dt:
05/22/2003
Title:
METHOD FOR THE ACCELERATION AND SIMPLIFICATION OF FILE SYSTEM LOGGING TECHNIQUES USING STORAGE DEVICE SNAPSHOTS
75
Patent #:
Issue Dt:
09/16/2003
Application #:
10002413
Filing Dt:
10/23/2001
Title:
LOW TEMPERATURE COEFFICIENT RESISTOR
76
Patent #:
Issue Dt:
11/23/2004
Application #:
10002479
Filing Dt:
11/15/2001
Title:
METHOD AND APPARATUS FOR ENHANCING CORRECTION POWER OF REVERSE ORDER ERROR CORRECTION CODES
77
Patent #:
Issue Dt:
12/13/2005
Application #:
10002499
Filing Dt:
11/02/2001
Title:
SELF-REPAIRING INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME
78
Patent #:
Issue Dt:
04/19/2005
Application #:
10002672
Filing Dt:
10/23/2001
Publication #:
Pub Dt:
05/22/2003
Title:
HEADER DETECT CONFIGURATION WITHIN A DVD-RAM READ DEVICE AND METHODS OF ACQUIRING AND MAINTAINING PHASE LOCK IN A WOBBLE PHASE LOCK LOOP
79
Patent #:
Issue Dt:
03/04/2003
Application #:
10002831
Filing Dt:
10/26/2001
Title:
PROCESS FOR FORMING COMPOSITE OF BARRIER LAYERS OF DIELECTRIC MATERIAL TO INHIBIT MIGRATION OF COPPER FROM COPPER METAL INTERCONNECT OF INTEGRATED CIRCUIT STRUCTURE INTO ADJACENT LAYER OF LOW K DIELECTRIC MATERIAL
80
Patent #:
Issue Dt:
09/02/2003
Application #:
10002981
Filing Dt:
10/26/2001
Title:
PROCESS FOR FORMING INTEGRATED CIRCUIT STRUCTURE COMPRISING LAYER OF LOW K DIELECTRIC MATERIAL HAVING ANTIREFLECTIVE PROPERTIES IN AN UPPER SURFACE
81
Patent #:
Issue Dt:
08/13/2002
Application #:
10003763
Filing Dt:
11/01/2001
Title:
NOISE REDUCTION AUTO PHASING CIRCUIT FOR SWITCHED CAPACITOR CIRCUITS
82
Patent #:
Issue Dt:
12/23/2003
Application #:
10003823
Filing Dt:
10/31/2001
Title:
VERILOG TO VITAL TRANSLATOR
83
Patent #:
Issue Dt:
05/24/2005
Application #:
10004208
Filing Dt:
11/01/2001
Title:
MULTIPLE MEMORY SYSTEM SUPPORT THROUGH SEGMENT ASSIGNMENT
84
Patent #:
Issue Dt:
05/20/2003
Application #:
10004461
Filing Dt:
11/01/2001
Title:
METHOD FOR CREATING SELF-ALIGNED ALLOY CAPPING LAYERS FOR COPPER INTERCONNECT STRUCTURES
85
Patent #:
Issue Dt:
07/27/2004
Application #:
10005062
Filing Dt:
12/03/2001
Title:
METHOD AND SYSTEM FOR IMPLEMENTING INCREMENTAL CHANGE TO CIRCUIT DESIGN
86
Patent #:
Issue Dt:
09/23/2003
Application #:
10005097
Filing Dt:
12/05/2001
Title:
DIE ATTACH BACKING GRINDING
87
Patent #:
Issue Dt:
01/11/2005
Application #:
10006162
Filing Dt:
12/06/2001
Title:
METHOD AND APPARATUS TO MANAGE INDEPENDENT MEMORY SYSTEMS AS A SHARED VOLUME
88
Patent #:
Issue Dt:
10/26/2004
Application #:
10006398
Filing Dt:
11/30/2001
Title:
ALIGNMENT PROCESS FOR INTEGRATED CIRCUIT STRUCTURES ON SEMICONDUCTOR SUBSTRATE USING SCATTEROMETRY MEASUREMENTS OF LATENT IMAGES IN SPACED APART TEST FIELDS ON SUBSTRATE
89
Patent #:
Issue Dt:
04/22/2003
Application #:
10006540
Filing Dt:
11/30/2001
Title:
METHOD FOR PREVENTING BORDERLESS CONTACT TO WELL LEAKAGE
90
Patent #:
Issue Dt:
02/14/2006
Application #:
10007245
Filing Dt:
10/22/2001
Title:
DATA READY INDICATOR BETWEEN DIFFERENT CLOCK DOMAINS
91
Patent #:
Issue Dt:
03/25/2003
Application #:
10007405
Filing Dt:
12/04/2001
Title:
PROCESS FOR TREATING POROUS LOW K DIELECTRIC MATERIAL IN DAMASCENE STRUCTURE TO FORM A NON-POROUS DIELECTRIC DIFFUSION BARRIER LAYER ON ETCHED VIA AND TRENCH SURFACES IN THE POROUS LOW K DIELECTRIC MATERIAL
92
Patent #:
Issue Dt:
11/18/2003
Application #:
10008089
Filing Dt:
11/13/2001
Title:
DIRECT TRANSFORMATION OF ENGINEERING CHANGE ORDERS TO SYNTHESIZED IC CHIP DESIGNS
93
Patent #:
Issue Dt:
03/16/2004
Application #:
10008170
Filing Dt:
10/19/2001
Title:
HIGH SPEED LOW NOISE TRANSISTOR
94
Patent #:
Issue Dt:
03/28/2006
Application #:
10011153
Filing Dt:
12/05/2001
Title:
DSL LINE INTERFACE HAVING LOW-PASS FILTER CHARACTERISTIC WITH REDUCED EXTERNAL COMPONENTS
95
Patent #:
Issue Dt:
06/20/2006
Application #:
10011796
Filing Dt:
12/05/2001
Title:
LONG PATH AT-SPEED TESTING
96
Patent #:
Issue Dt:
01/03/2006
Application #:
10012257
Filing Dt:
11/08/2001
Publication #:
Pub Dt:
09/12/2002
Title:
WRITE COMPENSATION FOR DATA STORAGE AND COMMUNICATION SYSTEMS
97
Patent #:
Issue Dt:
07/29/2003
Application #:
10012616
Filing Dt:
12/12/2001
Title:
METHOD AND APPARATUS FOR VARYING TARGET BEHAVIOR IN A SCSI ENVIRONMENT
98
Patent #:
Issue Dt:
01/01/2008
Application #:
10012821
Filing Dt:
12/10/2001
Title:
REACTOR SYSTEM
99
Patent #:
Issue Dt:
11/11/2003
Application #:
10012986
Filing Dt:
12/05/2001
Title:
METHODS AND STRUCTURE FOR READ DATA SYNCHRONIZATION WITH MINIMAL LATENCY
100
Patent #:
Issue Dt:
09/02/2003
Application #:
10013572
Filing Dt:
12/11/2001
Publication #:
Pub Dt:
06/12/2003
Title:
INTEGRATED INDUCTOR IN SEMICONDUCTOR MANUFACTURING
Assignor
1
Exec Dt:
04/06/2007
Assignee
1
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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