|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08476434
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
REDUCTION OF FALSE LOCKING OF CODE WORDS IN CONCATENATED DECODERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/1997
|
Application #:
|
08477490
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
CONFIGURATION MANAGEMENT AND AUTOMATED TEST SYSTEM FOR ASIC DESIGN SOFTWARE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08477827
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
OPTICAL CORRECTIVE TECHNIQUES WITH RETICLE FORMATION AND RETICLE STITCHING TO PROVIDE DESIGN FLEXIBILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/1997
|
Application #:
|
08481799
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
KEYED END EFFECTOR FOR CMP PAD CONDITIONER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/1996
|
Application #:
|
08482763
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
HIERARCHICAL CLOCK DISTRIBUTION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08484003
|
Filing Dt:
|
01/09/1996
|
|
Title:
|
INPUT-OUTPUT (I/O) STRUCTURE WITH CAPACITIVELY TRIGGERED THYRISTOR FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08484849
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
METHOD OF FABRICATING A GATE ARRAY INTERGRATED CIRCUIT INCLUDING INTER CONNECTABLE MACRO-ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08485060
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
MULTIPLE PIN DIE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08485517
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
APPARATUS AND METHOD USING OPTICAL ENERGY FOR SPECIFYING AND QUANTITATIVELY CONTROLLING CHEMICALLY-REACTIVE COMPONENTS OF SEMICONDUCTOR PROCESSING PLASMA ETCHING GAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/1997
|
Application #:
|
08485865
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
MULTI-CHIP-MODULE (MCM) MICROCIRCUIT INCLUDING MULTIPLE PROCESSORS AND ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08486803
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SILICIDATION PROCESS WITH ETCH STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1996
|
Application #:
|
08488075
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SELF-ALIGNED TWIN WELL PROCESS HAVING A SIO2-POLYSILICON-SIO2 BARRIER MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1998
|
Application #:
|
08491433
|
Filing Dt:
|
06/16/1995
|
|
Title:
|
METHOD FOR LOCAL RIP-UP AND REROUTE OF SIGNAL PATHS IN AN IC DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08496861
|
Filing Dt:
|
06/30/1995
|
|
Title:
|
IMAGE SENSOR ARRAY WITH PICTURE ELEMENT SENSOR TESTABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/1998
|
Application #:
|
08501284
|
Filing Dt:
|
07/12/1995
|
|
Title:
|
ERRORS AND ERASURES CORRECTING REED-SOLOMON DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08501289
|
Filing Dt:
|
07/12/1995
|
|
Title:
|
METHOD OF MAKING COMBINED METAL OXIDE SEMICONDUCTOR AND JUNCTION FIELD EFFECT TRANSISTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/1998
|
Application #:
|
08502300
|
Filing Dt:
|
07/13/1995
|
|
Title:
|
SEMICONDUCTOR CHIP HAVING IDENTIFICATION/ENCRYPTION CODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/1996
|
Application #:
|
08502566
|
Filing Dt:
|
07/13/1995
|
|
Title:
|
COMBINED JFET & MOS TRANSISTOR DEVICE, CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
08505044
|
Filing Dt:
|
07/21/1995
|
|
Title:
|
APPARATUS AND METHOD FOR RECOVERING A CLOCK SIGNAL WHICH IS EMBEDDED IN AN INCOMING DATA STREAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/1998
|
Application #:
|
08506148
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
METHOD AND APPARATUS FOR ENHANCING THROUGHPUT OF DISK ARRAY DATA TRANSFERS IN A CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08506164
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
METHOD OF IMPROVING MOLDING OF AN OVERMOLDED PACKAGE BODY ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/1998
|
Application #:
|
08506293
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
METHOD AND APPARTUS FOR TRANSFERRING DATA IN A CONTROLLER HAVING CENTRALIZED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/1997
|
Application #:
|
08506821
|
Filing Dt:
|
07/25/1995
|
|
Title:
|
PROCESS MONITOR FOR CMOS INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08512678
|
Filing Dt:
|
08/08/1995
|
|
Title:
|
AUTOMATING PHOTOLITHOGRAPHY IN THE FABRICATION OF INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08514013
|
Filing Dt:
|
08/11/1995
|
|
Title:
|
VIDEO STORAGE UNIT ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08514479
|
Filing Dt:
|
08/11/1995
|
|
Title:
|
DUAL BUS ARCHITECTURE FOR A STORAGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/1996
|
Application #:
|
08515434
|
Filing Dt:
|
08/15/1995
|
|
Title:
|
PACKET ERROR PROPAGATION FOR MPEG TRANSPORT DEMULTIPLEXERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
08517142
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/1998
|
Application #:
|
08517153
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL DRAM ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08517171
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
CAD FOR HEXAGONAL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08517189
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL SENSE CELL ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08517236
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL ARCHITECTURE WITH TRIANGULAR SHAPED CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08517266
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL SRAM ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08517339
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRI-DIRECTIONAL INTERCONNECT ARCHITECTURE FOR SRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08517406
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
ARCHITECTURE HAVING DIAMOND SHAPED OR PARALLELOGRAM SHAPED CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
|
Application #:
|
08517441
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
POLYDIRECTIONAL NON-ORTHOGINAL THREE LAYER INTERCONNECT ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08517451
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRIANGULAR SEMICONDUCTOR 'NAND' GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08517463
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRANSISTORS HAVING DYNAMICALLY ADJUSTABLE CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08517508
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
HEXAGONAL FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08517892
|
Filing Dt:
|
08/21/1995
|
|
Title:
|
TRIANGULAR SEMICONDUCTOR OR GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1997
|
Application #:
|
08520030
|
Filing Dt:
|
08/28/1995
|
|
Title:
|
LEAK DETECTION SYSTEM FOR A GAS MANIFOLD OF A CHEMICAL VAPOR DEPOSITION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/1997
|
Application #:
|
08520058
|
Filing Dt:
|
08/28/1995
|
|
Title:
|
A METHOD OF FORMING A LAYER OF MATERIAL ON A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/1996
|
Application #:
|
08521795
|
Filing Dt:
|
08/31/1995
|
|
Title:
|
IMPLANTATION OF A SEMICONDUCTOR SUBSTRATE WITH CONTROLLED AMOUNT OF NOBLE GAS IONS TO REDUCE CHANNELING AND/OR DIFFUSION OF A BORON DOPANT SUBSEQUENTLY IMPLANTED INTO THE SUBSTRATE TO FORM P- LDD REGION OF A PMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08525839
|
Filing Dt:
|
09/08/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING MULTIWAY PARTITIONING WITH CONSTRAINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08527660
|
Filing Dt:
|
09/13/1995
|
|
Title:
|
METHOD AND APPARATUS FOR DETECTING ASSERTION OF MULTIPLE SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/1997
|
Application #:
|
08527704
|
Filing Dt:
|
09/13/1995
|
|
Title:
|
FAST WORD LINE DECODER FOR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08531659
|
Filing Dt:
|
09/21/1995
|
|
Title:
|
HIGH SURFACE AREA TRENCHES FOR AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08531727
|
Filing Dt:
|
09/21/1995
|
|
Title:
|
INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08534228
|
Filing Dt:
|
09/26/1995
|
|
Title:
|
RECEIVER CIRCUIT HAVING ADAPTIVE EQUALIZER WITH CHARACTERISTICS DETERMINED BY SIGNAL ENVELOPE MEASUREMENT AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/1997
|
Application #:
|
08536002
|
Filing Dt:
|
09/29/1995
|
|
Title:
|
HIGH DENSITY CMOS INTEGRATED CIRCUIT WITH HEAT TRANSFER STRUCTURE FOR IMPROVED COOLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08536004
|
Filing Dt:
|
09/29/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING GENERALIZED ASSIGNMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08538629
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
METHOD OF CENTERING A HIGH PRESSURE LID SEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/1998
|
Application #:
|
08538630
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
HIGH PRESSURE LID SEAL CLIP APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08538631
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
HIGH CONTACT DENSITY BALL GRID ARRAY PACKAGE FOR FLIP-CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/1998
|
Application #:
|
08539188
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CONFIGURABLE BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08539189
|
Filing Dt:
|
10/04/1995
|
|
Title:
|
CENTERING LID SEAL CLIP APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1997
|
Application #:
|
08540336
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
SUPERSCALAR MICROPROCESSOR ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08540350
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
RISC PROCESSOR HAVING COPROCESSOR FOR EXECUTING CIRCULAR MASK INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/1998
|
Application #:
|
08540382
|
Filing Dt:
|
10/06/1995
|
|
Title:
|
CPU PIPELINE HAVING QUEUING STAGE TO FACILITATE BRANCH INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08542191
|
Filing Dt:
|
10/12/1995
|
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING DATA TO A PARALLEL PROCESSING ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08542283
|
Filing Dt:
|
10/12/1995
|
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED VIDEO FILTER PROCESSING USING EFFICIENT PIXEL REGISTER AND DATA ORGANIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/1998
|
Application #:
|
08543767
|
Filing Dt:
|
10/16/1995
|
|
Title:
|
BIST JITTER TOLERANCE MEASUREMENT TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/1997
|
Application #:
|
08545462
|
Filing Dt:
|
10/19/1995
|
|
Title:
|
DEFECT ISOLATION USING SCAN-PATH TESTING AND ELECTRON BEAM PROBING IN MULTI-LEVEL HIGH DENSITY ASICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/1997
|
Application #:
|
08545879
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
METHOD AND APPARATUS FOR TESTING OF SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08545880
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
APPARATUS AND METHOD FOR MEASURING QUIESCENT CURRENT UTILIZING TIMESET SWITCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/1997
|
Application #:
|
08545954
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
PROCESS FOR PREDICTING PROPAGATION DELAY USING LINEAR INTERPOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08546003
|
Filing Dt:
|
10/20/1995
|
|
Title:
|
I/O SYSTEM FOR REDUCING MAIN PROCESSOR OVERHEAD IN INITIATING I/O REQUESTS AND SERVICING I/O COMPLETION EVENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08546861
|
Filing Dt:
|
10/23/1995
|
|
Title:
|
METHODS AND STRUCTURE TO MAINTAIN A TWO LEVEL CACHE IN A RAID CONTROLLER AND THEREBY SELECTING A PREFERRED POSTING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/1997
|
Application #:
|
08546921
|
Filing Dt:
|
10/23/1995
|
|
Title:
|
PROCESS AND STRUCTURE FOR REDUCTION OF CHANNELING DURING IMPLANTATION OF SOURCE AND DRAIN REGIONS IN FORMATION OF MOS INTEGRATED CIRCUIT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/1997
|
Application #:
|
08547038
|
Filing Dt:
|
10/23/1995
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING AN INTERLACED IMAGE ON AN DISPLAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/1997
|
Application #:
|
08547166
|
Filing Dt:
|
10/24/1995
|
|
Title:
|
STRUCTURE AND METHOD FOR A MULTISTANDARD VIDEO ENCODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08547177
|
Filing Dt:
|
10/24/1995
|
|
Title:
|
METHOD AND CIRCUIT FOR FETCHING A 2-D REFERENCE PICTURE AREA FROM AN EXTERNAL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/1997
|
Application #:
|
08548369
|
Filing Dt:
|
11/01/1995
|
|
Title:
|
SCAN COMPATIBLE 3-STATE BUS CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08549383
|
Filing Dt:
|
10/27/1995
|
|
Title:
|
METHODS AND STRUCTURE TO MAINTAIN RAID CONFIGURATION INFORMATION ON DISKS OF THE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08549384
|
Filing Dt:
|
10/27/1995
|
|
Title:
|
APPARATUS AND METHOD FOR ANALYZING AND MODIFYING DATA TRANSFER REQUESTS IN A RAID SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/1998
|
Application #:
|
08550922
|
Filing Dt:
|
10/31/1995
|
|
Title:
|
MICROPROCESSOR SHIFTER USING ROTATION AND MASKING OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08550944
|
Filing Dt:
|
10/31/1995
|
|
Title:
|
MASK DECODER CIRCUIT OPTIMIZED FOR DATA PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08552461
|
Filing Dt:
|
11/09/1995
|
|
Title:
|
PROCESS FOR MAKING INTEGRATED CIRCUIT STRUCTURE COMPRISING LOCAL AREA INTERCONNECTS FORMED OVER SEMICONDUCTOR SUBSTRATE BY SELECTIVE DEPOSITION ON SEED LAYER IN PATTERNED TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1998
|
Application #:
|
08556599
|
Filing Dt:
|
11/13/1995
|
|
Title:
|
ESD PROTECTION FOR DEEP SUBMICRON CMOS DEVICES WITH MINIMUM TRADEOFF FOR LATCHUP BEHAVIOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08557721
|
Filing Dt:
|
11/13/1995
|
|
Title:
|
PROCESS FOR FORMING LOW DIELECTRIC CONSTANT LAYERS USING FULLERENES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08560588
|
Filing Dt:
|
11/20/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING FUZZY CELL CLUSTERIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08560834
|
Filing Dt:
|
11/20/1995
|
|
Title:
|
COMPUTER IMPLEMENTED METHOD FOR LEVELING INTERCONNECT WIRING DENSITY IN A CELL PLACEMENT FOR AN INTEGRATED CIRCUIT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08560848
|
Filing Dt:
|
11/20/1995
|
|
Title:
|
PHYSICAL DESIGN AUTOMATION SYSTEM AND PROCESS FOR DESIGNING INTEGRATED CIRCUIT CHIPS USING HIGHLY PARALLEL SIEVE OPTIMIZATION WITH MULTIPLE "JIGGLES"
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/1997
|
Application #:
|
08567894
|
Filing Dt:
|
12/06/1995
|
|
Title:
|
MICROELECTRONIC INTEGRATED CIRCUIT INCLUDING TRIANGULAR SEMICONDUCTOR "OR" GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08567944
|
Filing Dt:
|
12/06/1995
|
|
Title:
|
ENHANCED BRANCH DELAY SLOT HANDLING WITH SINGLE EXCEPTION PROGRAM COUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/1998
|
Application #:
|
08569782
|
Filing Dt:
|
12/08/1995
|
|
Title:
|
MPEG-2 INVERSE TELECINE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08570153
|
Filing Dt:
|
12/11/1995
|
|
Title:
|
A METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A BUS IN A DATA PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1997
|
Application #:
|
08571724
|
Filing Dt:
|
12/13/1995
|
|
Title:
|
OUTPUT BUFFER HAVING TRANSMISSION GATE AND ISOLATED SUPPLY TERMINALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08572665
|
Filing Dt:
|
12/14/1995
|
|
Title:
|
METHOD OF MAKING CMOS DYNAMIC RANDOM-ACCESS MEMORY STRUCTURES AND THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08573892
|
Filing Dt:
|
12/18/1995
|
|
Title:
|
SYSTEMS HAVING SHAPED, SELF-ALIGNING MICRO-BUMP STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/1997
|
Application #:
|
08575793
|
Filing Dt:
|
12/22/1995
|
|
Title:
|
5 VOLT DRIVER IN A 3 VOLT CMOS PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1998
|
Application #:
|
08578118
|
Filing Dt:
|
12/27/1995
|
|
Title:
|
METHOF OF FORMING A HIGH ELECTROMIGRATION RESISTANT METALLIZATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08578227
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
VARIABLE BIT RATE ENCODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1998
|
Application #:
|
08578228
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
FADE DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08578229
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
RATE CONTROL WITH PANIC MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08578230
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
SCENE CHANGE DETECTION USING QUANTIZATION SCALE FACTOR RATE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/1997
|
Application #:
|
08578231
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
AN VIDEO ENCODER WHICH USES INTRA-CODING WHEN AN ACTIVITY LEVEL OF A CURRENT MACRO BLOCK IS SMALLER THAN A THRESHOLD LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
|
Application #:
|
08578811
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
METHOD FOR PERFORMING RATE CONTROL IN A VIDEO ENCODER WHICH PROVIDES A BIT BUDGET FOR EACH FRAME WHILE EMPLOYING VIRTUAL BUFFERS AND VIRTUAL BUFFER VERIFIERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/1998
|
Application #:
|
08578812
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
METHOD OF ENCODING VIDEO USING MASTER AND SLAVE ENCODERS WHEREIN BIT BUDGETS FOR FRAMES TO BE ENCODED ARE BASED ON ENCODED FRAMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1998
|
Application #:
|
08578813
|
Filing Dt:
|
12/26/1995
|
|
Title:
|
THREE STAGE HIERARCHAL MOTION VECTOR DETERMINATION
|
|
