|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10614402
|
Filing Dt:
|
07/03/2003
|
|
Title:
|
INTEGRATD CIRCUIT DESIGN FOR BOTH INPUT OUTPUT LIMITED AND CORE LIMITED INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10614776
|
Filing Dt:
|
07/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
PROCESS FOR PLANARIZING UPPER SURFACE OF DAMASCENE WIRING STRUCTURE FOR INTEGRATED CIRCUIT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10614956
|
Filing Dt:
|
07/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR IMPROVED INPUT/OUTPUT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10615063
|
Filing Dt:
|
07/08/2003
|
|
Title:
|
ISOLATED STRIPLINE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10615558
|
Filing Dt:
|
07/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
HARD MASK REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10616623
|
Filing Dt:
|
07/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
OPTIMIZING IC CLOCK STRUCTURES BY MINIMIZING CLOCK UNCERTAINTY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
10619531
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
INTRA ESTIMATION CHROMA MODE 0 SUB-BLOCK DEPENDENT PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10620057
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
MEASUREMENT OF PACKAGE INTERCONNECT IMPEDANCE USING TESTER AND SUPPORTING TESTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10620074
|
Filing Dt:
|
07/14/2003
|
|
Title:
|
SEMICONDUCTOR PACKAGE HAVING A THERMALLY AND ELECTRICALLY CONNECTED HEATSPREADER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10620105
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
METHOD TO MAINTAIN DATA INTEGRITY DURING FLASH FILE TRANSFER TO RAID CONTROLLER FLASH USING A TERMINAL EMULATION PROGRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
10620581
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
FLEXIBLE ARCHITECTURE COMPONENT (FAC) FOR EFFICIENT DATA INTEGRATION AND INFORMATION INTERCHANGE USING WEB SERVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10621737
|
Filing Dt:
|
07/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS OF IC IMPLEMENTATION BASED ON C++ LANGUAGE DESCRIPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10623329
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
INTRA 4 X 4 MODES 3, 7 AND 8 AVAILABILITY DETERMINATION INTRA ESTIMATION AND COMPENSATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
10624253
|
Filing Dt:
|
07/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
METHOD AND/OR CIRCUIT FOR BINARY ARITHMETIC DECODING DECISIONS BEFORE TERMINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10624264
|
Filing Dt:
|
07/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH ON-CHIP CLOCK FREQUENCY MATCHING TO UPSTREAM HEAD END EQUIPMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10624347
|
Filing Dt:
|
07/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
METHODS AND SYSTEMS FOR AUTOMATIC VERIFICATION OF SPECIFICATION DOCUMENT TO HARDWARE DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10626825
|
Filing Dt:
|
07/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
ARCHITECTURE FOR A SEA OF PLATFORMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10627289
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
LOW GATE RESISTANCE LAYOUT PROCEDURE FOR RF TRANSISTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
10628194
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
STANDARD ATA QUEUING AUTOMATION IN SERIAL ATA INTERFACE FOR CREATING A FRAME INFORMATION STRUCTURE (FIS) CORRESPONDING TO COMMAND FROM TRANSPORT LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
10628614
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
WAFER EDGE DEFECT INSPECTION USING CAPTURED IMAGE ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10628986
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
METHOD OF MAPPING LOGIC FAILURES IN AN INTEGRATED CIRCUIT DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10629496
|
Filing Dt:
|
07/29/2003
|
|
Title:
|
SELECTIVE HIGH K DIELECTRICS REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10629507
|
Filing Dt:
|
07/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
VIDEO DECODING DURING I-FRAME DECODE AT RESOLUTION CHANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10631328
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
METHOD OF BALANCED COEFFICIENT OF THERMAL EXPANSION FOR FLIP CHIP BALL GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10631528
|
Filing Dt:
|
07/31/2003
|
|
Title:
|
METHOD AND APPARATUS FOR REDUCING MICROTRENCHING FOR BORDERLESS VIAS CREATED IN A DUAL DAMASCENE PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10631610
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MEASURING HIGH SPEED GLITCH ENERGY IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10632622
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
METHOD FOR PROVIDING CLOCK-NET AWARE DUMMY METAL USING DUMMY REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
10632881
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING SAS/FIBRE TARGET BEHAVIOR FROM A HOST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
10633224
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
CLOSED-LOOP SYSTEM FOR MASTERING, CERTIFICATION AND PRODUCTION OF COMPACT DISCS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10633856
|
Filing Dt:
|
08/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
UNIVERSAL GATES FOR ICS AND TRANSFORMATION OF NETLISTS FOR THEIR IMPLEMENTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10634416
|
Filing Dt:
|
08/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR INTEGRATING SIX SIGMA METHODOLOGY INTO INSPECTION RECEIVING PROCESS OF OUTSOURCED SUBASSEMBLIES, PARTS, AND MATERIALS: ACCEPTANCE, REJECTION, TRENDING, TRACKING AND CLOSED LOOP CORRECTIVE ACTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10634634
|
Filing Dt:
|
08/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
10635015
|
Filing Dt:
|
08/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
3-PRONG SECURITY/RELIABILITY/REAL-TIME DISTRIBUTED ARCHITECTURE OF INFORMATION HANDLING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10635276
|
Filing Dt:
|
08/06/2003
|
|
Title:
|
SUBSTRATE VOLTAGE CONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10637385
|
Filing Dt:
|
08/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD TO IMPROVE THE CONTROL OF ELECTRO-POLISHING BY USE OF A PLATING ELECTRODE AN ELECTROLYTE BATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10639338
|
Filing Dt:
|
08/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
REDUCED COMPLEXITY EFFICIENT BINARIZATION METHOD AND/OR CIRCUIT FOR MOTION VECTOR RESIDUALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10639701
|
Filing Dt:
|
08/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
STATIC TIMING ANALYSIS APPROACH FOR MULTI-CLOCK DOMAIN DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10640738
|
Filing Dt:
|
08/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
METHOD OF ROUTING A REDISTRIBUTION LAYER TRACE IN AN INTEGRATED CIRCUIT DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10641768
|
Filing Dt:
|
08/14/2003
|
|
Title:
|
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10642954
|
Filing Dt:
|
08/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
METHODS AND SYSTEMS FOR END-TO-END DATA PROTECTION IN A MEMORY CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10643463
|
Filing Dt:
|
08/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
TYPE CONFIGURABLE MEMORY METHODOLOGY FOR USE WITH METAL PROGRAMMABLE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10644116
|
Filing Dt:
|
08/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
WHOLE-WAFER PHOTOEMISSION ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
10645900
|
Filing Dt:
|
08/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR SCAN TESTING LATCH BASED RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10646535
|
Filing Dt:
|
08/22/2003
|
|
Title:
|
SYSTEM AND METHOD FOR EFFICIENTLY TESTING A LARGE RANDOM ACCESS MEMORY SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10646570
|
Filing Dt:
|
08/22/2003
|
|
Title:
|
MICROCHANNEL FORMATION FOR FUSES, INTERCONNECTS, CAPACITORS, AND INDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10647863
|
Filing Dt:
|
08/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
ZERO CAPACITANCE BONDPAD UTILIZING ACTIVE NEGATIVE CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10647993
|
Filing Dt:
|
08/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
SHARING FUSE BLOCKS BETWEEN MEMORIES IN HARD-BISR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10648038
|
Filing Dt:
|
08/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
MEMORY MAPPING FOR PARALLEL TURBO DECODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10648054
|
Filing Dt:
|
08/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
MULTI-LAYER STAGGERED POWER BUS LAYOUT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10648602
|
Filing Dt:
|
08/25/2003
|
|
Title:
|
FORMING COPPER INTERCONNECTS WITH SN COATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10648967
|
Filing Dt:
|
08/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
MEMORY WINDOW MANAGER FOR CONTROL STRUCTURE ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10650192
|
Filing Dt:
|
08/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
DESIGN AND USE OF A SPACER CELL TO SUPPORT RECONFIGURABLE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10650296
|
Filing Dt:
|
08/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
METHOD OF CLOCK DRIVEN CELL PLACEMENT AND CLOCK TREE SYNTHESIS FOR INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10650395
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
HIGH QUALITY FACTOR SPIRAL INDUCTOR THAT UTILIZES ACTIVE NEGATIVE CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10652453
|
Filing Dt:
|
08/29/2003
|
|
Title:
|
BONDING PAD ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
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10653588
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Filing Dt:
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09/02/2003
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Publication #:
|
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Pub Dt:
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03/03/2005
| | | | |
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Title:
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WIDELY TUNEABLE AND FULLY DIFFERENTIAL LC OSCILLATOR UTILIZING AN ACTIVE INDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
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Application #:
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10653593
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Filing Dt:
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09/02/2003
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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WIDELY TUNABLE RING OSCILLATOR UTILIZING ACTIVE NEGATIVE CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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06/14/2005
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Application #:
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10654520
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Filing Dt:
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08/30/2003
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Publication #:
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|
Pub Dt:
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03/03/2005
| | | | |
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Title:
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VARIABLE GAIN CURRENT FEEDBACK AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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08/23/2005
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Application #:
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10655053
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Filing Dt:
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09/03/2003
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|
Publication #:
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Pub Dt:
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03/03/2005
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Title:
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RECONFIGURABLE MEMORY ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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06/20/2006
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Application #:
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10655191
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Filing Dt:
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09/04/2003
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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CONTROLLER ARCHITECTURE FOR MEMORY MAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
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Application #:
|
10656195
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Filing Dt:
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09/04/2003
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Publication #:
|
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Pub Dt:
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03/10/2005
| | | | |
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Title:
|
DATA STREAM FREQUENCY REDUCTION AND/OR PHASE SHIFT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
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10658017
|
Filing Dt:
|
09/08/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
|
METHOD OF TRANSLATING A NET DESCRIPTION OF AN INTEGRATED CIRCUIT DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
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Application #:
|
10658168
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Filing Dt:
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09/08/2003
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|
Publication #:
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Pub Dt:
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03/24/2005
| | | | |
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Title:
|
METHOD OF QUALIFYING A PROCESS TOOL WITH WAFER DEFECT MAPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
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Application #:
|
10659134
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Filing Dt:
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09/10/2003
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|
Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
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APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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04/11/2006
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Application #:
|
10659138
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Filing Dt:
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09/10/2003
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
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Title:
|
FIRST TIME SILICON AND PROTO TEST CELL NOTIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
10660888
|
Filing Dt:
|
09/12/2003
|
|
Publication #:
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|
Pub Dt:
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03/17/2005
| | | | |
|
Title:
|
STORAGE RECOVERY USING A DELTA LOG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10661013
|
Filing Dt:
|
09/12/2003
|
|
Publication #:
|
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Pub Dt:
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03/17/2005
| | | | |
|
Title:
|
WAFER EDGE INSPECTION DATA GATHERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10662188
|
Filing Dt:
|
09/15/2003
|
|
Publication #:
|
|
Pub Dt:
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03/17/2005
| | | | |
|
Title:
|
METAL PROGRAMMABLE PHASE-LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10664137
|
Filing Dt:
|
09/17/2003
|
|
Publication #:
|
|
Pub Dt:
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03/24/2005
| | | | |
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Title:
|
CUSTOM CLOCK INTERCONNECTS ON A STANDARDIZED SILICON PLATFORM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
10664636
|
Filing Dt:
|
09/19/2003
|
|
Title:
|
USER INTERFACE SOFTWARE DEVELOPMENT TOOL AND METHOD FOR ENHANCING THE SEQUENCING OF
INSTRUCTIONS WITHIN A SUPERSCALAR MICROPROCESSOR PIPELINE BY DISPLAYING AND MANIPULATING INSTRUCTIONS IN THE PIPELINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10665927
|
Filing Dt:
|
09/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
|
Title:
|
METHOD OF NOISE ANALYSIS AND CORRECTION OF NOISE VIOLATIONS FOR AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10667010
|
Filing Dt:
|
09/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
TEST SCHEDULE ESTIMATOR FOR LEGACY BUILDS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10667812
|
Filing Dt:
|
09/22/2003
|
|
Publication #:
|
|
Pub Dt:
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03/24/2005
| | | | |
|
Title:
|
METHOD FOR OPTIMIZING EXECUTION TIME OF PARALLEL PROCESSOR PROGRAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
10667911
|
Filing Dt:
|
09/22/2003
|
|
Publication #:
|
|
Pub Dt:
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03/24/2005
| | | | |
|
Title:
|
DEVICE FOR SIMULTANEOUS DISPLAY OF VIDEO AT TWO RESOLUTIONS WITH DIFFERENT FRACTIONS OF ACTIVE REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10667948
|
Filing Dt:
|
09/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
METHOD AND/OR APPARATUS FOR REDUCING THE COMPLEXITY OF NON-REFERENCE FRAME ENCODING USING SELECTIVE RECONSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10668021
|
Filing Dt:
|
09/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
PAD CONDITIONER SETUP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10668875
|
Filing Dt:
|
09/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
HIGH PERFORMANCE VOLTAGE CONTROL DIFFUSION RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
10669930
|
Filing Dt:
|
09/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
MULTI-STANDARD VARIABLE BLOCK SIZE MOTION ESTIMATION PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10671352
|
Filing Dt:
|
09/25/2003
|
|
Publication #:
|
|
Pub Dt:
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03/31/2005
| | | | |
|
Title:
|
DIGITAL PROGRAMMABLE DELAY SCHEME WITH AUTOMATIC CALIBRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10672125
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VOLTAGE-DOWN CIRCUIT REGULATOR AND CHARGE SHARING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
10672390
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
Systems and methods for configuring ports of an SAS domain
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10672538
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
ROUTING FOR REDUCING IMPEDANCE DISTORTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10672752
|
Filing Dt:
|
09/25/2003
|
|
Title:
|
METHOD AND SYSTEM FOR DECODING BIPHASE-MARK ENCODED DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10673721
|
Filing Dt:
|
09/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
FUNCTIONALITY BASED PACKAGE DESIGN FOR INTEGRATED CIRCUIT BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10674165
|
Filing Dt:
|
09/29/2003
|
|
Publication #:
|
|
Pub Dt:
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03/31/2005
| | | | |
|
Title:
|
SINGLE VCO/LOOP FILTER TO CONTROL A WOBBLE AND READ CIRCUIT OF A DVD AND/OR CD RECORDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10676602
|
Filing Dt:
|
10/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
SUBSTRATE-BIASED I/O AND POWER ESD PROTECTION CIRCUITS IN DEEP-SUBMICRON TWIN-WELL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10679004
|
Filing Dt:
|
10/02/2003
|
|
Title:
|
MECHANISM FOR IMPROVING THE STRUCTURAL INTEGRITY OF LOW-K FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10680047
|
Filing Dt:
|
10/07/2003
|
|
Title:
|
NONINTRUSIVE WAFER MARKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10681554
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
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04/14/2005
| | | | |
|
Title:
|
ROBUST HIGH DENSITY SUBSTRATE DESIGN FOR THERMAL CYCLING RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10681757
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
HIGH PERFORMANCE RAID MAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10682012
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
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04/14/2005
| | | | |
|
Title:
|
METHOD, SYSTEM, AND PRODUCT FOR PROXY-BASED METHOD TRANSLATIONS FOR MULTIPLE DIFFERENT FIRMWARE VERSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10682149
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD OF CREATING VIRTUAL DATA PATHS USING A MULTIPLE-PATH DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10682631
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
SUPPORTING MOTION VECTORS OUTSIDE PICTURE BOUNDARIES IN MOTION ESTIMATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10683101
|
Filing Dt:
|
10/09/2003
|
|
Title:
|
SLOTTED BONDING PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10683369
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
INCREMENTAL DUMMY METAL INSERTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10684119
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
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04/29/2004
| | | | |
|
Title:
|
IDDQ TEST METHODOLOGY BASED ON THE SENSITIVITY OF FAULT CURRENT TO POWER SUPPLY VARIATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2006
|
Application #:
|
10684733
|
Filing Dt:
|
10/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
EFFICIENT IMPLEMENTATION OF MULTIPLE CLOCK DOMAIN ACCESSES TO DIFFUSED MEMORIES IN STRUCTURED ASICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10685987
|
Filing Dt:
|
10/15/2003
|
|
Publication #:
|
|
Pub Dt:
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04/21/2005
| | | | |
|
Title:
|
METHOD, APPARATUS AND PROGRAM FOR MIGRATING BETWEEN STRIPED STORAGE AND PARITY STRIPED STORAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10687991
|
Filing Dt:
|
10/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
PAGE BOUNDARY DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10688023
|
Filing Dt:
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10/16/2003
|
|
Title:
|
INTEGRATED NAND AND NOR-TYPE FLASH MEMORY DEVICE AND METHOD OF USING THE SAME
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