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Reel/Frame:033102/0270   Pages: 90
Recorded: 06/06/2014
Attorney Dkt #:040981-0072
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 3258
Page 28 of 33
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
Patent #:
7065721
Issue Dt:
06/20/2006
Application #:
10757752
Filing Dt:
01/14/2004
Publication #:
US20050028123
Pub Dt:
02/03/2005
Title:
OPTIMIZED BOND OUT METHOD FOR FLIP CHIP WAFERS
2
Patent #:
7921082
Issue Dt:
04/05/2011
Application #:
10764205
Filing Dt:
01/23/2004
Publication #:
US20050165863
Pub Dt:
07/28/2005
Title:
FILE RECOVERY UNDER LINUX OPERATING SYSTEM
3
Patent #:
6897798
Issue Dt:
05/24/2005
Application #:
10765387
Filing Dt:
01/26/2004
Title:
METHOD AND APPARATUS FOR CONTROLLING SWITCHING NOISE IN DIGITAL-TO-ANALOG INTERFACE
4
Patent #:
6888367
Issue Dt:
05/03/2005
Application #:
10767314
Filing Dt:
01/28/2004
Title:
METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT CORE MODULES
5
Patent #:
7076746
Issue Dt:
07/11/2006
Application #:
10768558
Filing Dt:
01/29/2004
Publication #:
US20050034086
Pub Dt:
02/10/2005
Title:
METHOD AND APPARATUS FOR MAPPING PLATFORM-BASED DESIGN TO MULTIPLE FOUNDRY PROCESSES
6
Patent #:
NONE
Issue Dt:
Application #:
10768588
Filing Dt:
01/29/2004
Publication #:
US20050034087
Pub Dt:
02/10/2005
Title:
Method and apparatus for mapping platform-based design to multiple foundry processes
7
Patent #:
7469070
Issue Dt:
12/23/2008
Application #:
10774913
Filing Dt:
02/09/2004
Publication #:
US20050179572
Pub Dt:
08/18/2005
Title:
METHOD FOR SELECTION OF CONTEXTS FOR ARITHMETIC CODING OF REFERENCE PICTURE AND MOTION VECTOR RESIDUAL BITSTREAM SYNTAX ELEMENTS
8
Patent #:
6971944
Issue Dt:
12/06/2005
Application #:
10779966
Filing Dt:
02/17/2004
Publication #:
US20050181706
Pub Dt:
08/18/2005
Title:
METHOD AND CONTROL SYSTEM FOR IMPROVING CMP PROCESS BY DETECTING AND REACTING TO HARMONIC OSCILLATION
9
Patent #:
7117310
Issue Dt:
10/03/2006
Application #:
10780971
Filing Dt:
02/18/2004
Publication #:
US20050182906
Pub Dt:
08/18/2005
Title:
SYSTEMS AND METHODS FOR CACHE SYNCHRONIZATION BETWEEN REDUNDANT STORAGE CONTROLLERS
10
Patent #:
7131103
Issue Dt:
10/31/2006
Application #:
10793055
Filing Dt:
03/04/2004
Publication #:
US20050198608
Pub Dt:
09/08/2005
Title:
CONDUCTOR STACK SHIFTING
11
Patent #:
7116743
Issue Dt:
10/03/2006
Application #:
10794080
Filing Dt:
03/04/2004
Title:
DIGITAL PHASE LOCK LOOP
12
Patent #:
7230460
Issue Dt:
06/12/2007
Application #:
10794418
Filing Dt:
08/26/2004
Title:
DIGITAL VISUAL INTERFACE
13
Patent #:
7264906
Issue Dt:
09/04/2007
Application #:
10794683
Filing Dt:
03/05/2004
Publication #:
US20050196681
Pub Dt:
09/08/2005
Title:
OPC BASED ILLUMINATION OPTIMIZATION WITH MASK ERROR CONSTRAINTS
14
Patent #:
7299158
Issue Dt:
11/20/2007
Application #:
10799851
Filing Dt:
03/12/2004
Publication #:
US20050203862
Pub Dt:
09/15/2005
Title:
PROCESS CONTROL DATA COLLECTION
15
Patent #:
7325222
Issue Dt:
01/29/2008
Application #:
10800219
Filing Dt:
03/12/2004
Publication #:
US20050204328
Pub Dt:
09/15/2005
Title:
METHOD AND APPARATUS FOR VERIFYING THE POST-OPTICAL PROXIMITY CORRECTED MASK WAFER IMAGE SENSITIVITY TO RETICLE MANUFACTURING ERRORS
16
Patent #:
7395522
Issue Dt:
07/01/2008
Application #:
10801310
Filing Dt:
03/16/2004
Publication #:
US20050229144
Pub Dt:
10/13/2005
Title:
YIELD PROFILE MANIPULATOR
17
Patent #:
7430202
Issue Dt:
09/30/2008
Application #:
10802114
Filing Dt:
03/15/2004
Publication #:
US20050030943
Pub Dt:
02/10/2005
Title:
SYSTEM AND METHOD OF TRIBUTARY TIME-SPACE SWITCHING
18
Patent #:
7290066
Issue Dt:
10/30/2007
Application #:
10803301
Filing Dt:
03/18/2004
Publication #:
US20050210159
Pub Dt:
09/22/2005
Title:
METHODS AND STRUCTURE FOR IMPROVED TRANSFER RATE PERFORMANCE IN A SAS WIDE PORT ENVIRONMENT
19
Patent #:
7398486
Issue Dt:
07/08/2008
Application #:
10803516
Filing Dt:
03/17/2004
Publication #:
US20050210422
Pub Dt:
09/22/2005
Title:
METHOD AND APPARATUS FOR PERFORMING LOGICAL TRANSFORMATIONS FOR GLOBAL ROUTING
20
Patent #:
7325081
Issue Dt:
01/29/2008
Application #:
10807968
Filing Dt:
03/24/2004
Publication #:
US20050216814
Pub Dt:
09/29/2005
Title:
CRC DATA PROTECTION SCHEME FOR NON-BLOCK-ORIENTED DATA
21
Patent #:
7114133
Issue Dt:
09/26/2006
Application #:
10809939
Filing Dt:
03/25/2004
Publication #:
US20040221248
Pub Dt:
11/04/2004
Title:
BROKEN SYMMETRY FOR OPTIMIZATION OF RESOURCE FABRIC IN A SEA-OF-PLATFORM ARCHITECTURE
22
Patent #:
7200832
Issue Dt:
04/03/2007
Application #:
10810294
Filing Dt:
03/26/2004
Publication #:
US20050229132
Pub Dt:
10/13/2005
Title:
MACRO CELL FOR INTEGRATED CIRCUIT PHYSICAL LAYER INTERFACE
23
Patent #:
7231587
Issue Dt:
06/12/2007
Application #:
10812286
Filing Dt:
03/29/2004
Publication #:
US20050216815
Pub Dt:
09/29/2005
Title:
EMBEDDED PICTURE PSNR/CRC DATA IN COMPRESSED VIDEO BITSTREAM
24
Patent #:
7171518
Issue Dt:
01/30/2007
Application #:
10817302
Filing Dt:
04/02/2004
Publication #:
US20050228942
Pub Dt:
10/13/2005
Title:
DATA STORAGE SYSTEM RECOVERY FROM DISK FAILURE DURING SYSTEM OFF-LINE CONDITION
25
Patent #:
7620743
Issue Dt:
11/17/2009
Application #:
10817419
Filing Dt:
04/01/2004
Publication #:
US20050223388
Pub Dt:
10/06/2005
Title:
SYSTEM AND METHOD FOR IMPLEMENTING MULTIPLE INSTANTIATED CONFIGURABLE PERIPHERALS IN A CIRCUIT DESIGN
26
Patent #:
7185301
Issue Dt:
02/27/2007
Application #:
10819254
Filing Dt:
04/06/2004
Publication #:
US20050226056
Pub Dt:
10/13/2005
Title:
GENERIC METHOD AND APPARATUS FOR IMPLEMENTING SOURCE SYNCHRONOUS INTERFACE IN PLATFORM ASIC
27
Patent #:
7119432
Issue Dt:
10/10/2006
Application #:
10820494
Filing Dt:
04/07/2004
Publication #:
US20050224955
Pub Dt:
10/13/2005
Title:
METHOD AND APPARATUS FOR ESTABLISHING IMPROVED THERMAL COMMUNICATION BETWEEN A DIE AND A HEATSPREADER IN A SEMICONDUCTOR PACKAGE
28
Patent #:
7463781
Issue Dt:
12/09/2008
Application #:
10824152
Filing Dt:
04/14/2004
Publication #:
US20050232505
Pub Dt:
10/20/2005
Title:
LOW OVERHEAD CONTEXT INITIALIZATIONS FOR ARITHMETIC VIDEO CODECS
29
Patent #:
7103858
Issue Dt:
09/05/2006
Application #:
10824509
Filing Dt:
04/14/2004
Publication #:
US20050235244
Pub Dt:
10/20/2005
Title:
PROCESS AND APPARATUS FOR CHARACTERIZING INTELLECTUAL PROPERTY FOR INTEGRATION INTO AN IC PLATFORM ENVIRONMENT
30
Patent #:
7270942
Issue Dt:
09/18/2007
Application #:
10825342
Filing Dt:
04/14/2004
Publication #:
US20050088640
Pub Dt:
04/28/2005
Title:
OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
31
Patent #:
7219317
Issue Dt:
05/15/2007
Application #:
10828408
Filing Dt:
04/19/2004
Publication #:
US20050235234
Pub Dt:
10/20/2005
Title:
METHOD AND COMPUTER PROGRAM FOR VERIFYING AN INCREMENTAL CHANGE TO AN INTEGRATED CIRCUIT DESIGN
32
Patent #:
7210113
Issue Dt:
04/24/2007
Application #:
10830542
Filing Dt:
04/23/2004
Publication #:
US20050240889
Pub Dt:
10/27/2005
Title:
PROCESS AND APPARATUS FOR PLACING CELLS IN AN IC FLOORPLAN
33
Patent #:
7219321
Issue Dt:
05/15/2007
Application #:
10830739
Filing Dt:
04/25/2004
Publication #:
US20050240746
Pub Dt:
10/27/2005
Title:
PROCESS AND APPARATUS FOR MEMORY MAPPING
34
Patent #:
7606692
Issue Dt:
10/20/2009
Application #:
10832226
Filing Dt:
04/26/2004
Publication #:
US20050240387
Pub Dt:
10/27/2005
Title:
GATE-LEVEL NETLIST REDUCTION FOR SIMULATING TARGET MODULES OF A DESIGN
35
Patent #:
8315588
Issue Dt:
11/20/2012
Application #:
10835936
Filing Dt:
04/30/2004
Publication #:
US20050245226
Pub Dt:
11/03/2005
Title:
RESISTIVE VOLTAGE-DOWN REGULATOR FOR INTEGRATED CIRCUIT RECEIVERS
36
Patent #:
7386120
Issue Dt:
06/10/2008
Application #:
10837454
Filing Dt:
04/30/2004
Publication #:
US20050243994
Pub Dt:
11/03/2005
Title:
ECHO CANCELLER HAVING A FREQUENCY DOMAIN ACTIVE REGION LOCATION ESTIMATOR
37
Patent #:
7026961
Issue Dt:
04/11/2006
Application #:
10837922
Filing Dt:
05/03/2004
Publication #:
US20050258982
Pub Dt:
11/24/2005
Title:
REAL TIME BINARY ARITHMETIC ENCODING
38
Patent #:
7343519
Issue Dt:
03/11/2008
Application #:
10838081
Filing Dt:
05/03/2004
Publication #:
US20050257081
Pub Dt:
11/17/2005
Title:
DISK DRIVE POWER CYCLE SCREENING METHOD AND APPARATUS FOR DATA STORAGE SYSTEM
39
Patent #:
6990420
Issue Dt:
01/24/2006
Application #:
10842879
Filing Dt:
05/10/2004
Publication #:
US20050251354
Pub Dt:
11/10/2005
Title:
METHOD OF ESTIMATING A LOCAL AVERAGE CROSSTALK VOLTAGE FOR A VARIABLE VOLTAGE OUTPUT RESISTANCE MODEL
40
Patent #:
7086015
Issue Dt:
08/01/2006
Application #:
10844664
Filing Dt:
05/12/2004
Publication #:
US20050257180
Pub Dt:
11/17/2005
Title:
METHOD OF OPTIMIZING RTL CODE FOR MULTIPLEX STRUCTURES
41
Patent #:
7360133
Issue Dt:
04/15/2008
Application #:
10847691
Filing Dt:
05/18/2004
Publication #:
US20050262460
Pub Dt:
11/24/2005
Title:
METHOD FOR CREATING A JTAG TAP CONTROLLER IN A SLICE FOR USE DURING CUSTOM INSTANCE CREATION TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL
42
Patent #:
7188330
Issue Dt:
03/06/2007
Application #:
10847692
Filing Dt:
05/18/2004
Publication #:
US20050262465
Pub Dt:
11/24/2005
Title:
HANDLING OF UNUSED COREWARE WITH EMBEDDED BOUNDARY SCAN CHAINS TO AVOID THE NEED OF A BOUNDARY SCAN SYNTHESIS TOOL DURING CUSTOM INSTANCE CREATION
43
Patent #:
7023252
Issue Dt:
04/04/2006
Application #:
10848979
Filing Dt:
05/19/2004
Publication #:
US20050258881
Pub Dt:
11/24/2005
Title:
CHIP LEVEL CLOCK TREE DESKEW CIRCUIT
44
Patent #:
7117475
Issue Dt:
10/03/2006
Application #:
10848994
Filing Dt:
05/18/2004
Publication #:
US20050262467
Pub Dt:
11/24/2005
Title:
METHOD AND SYSTEM FOR UTILIZING AN ISOFOCAL CONTOUR TO PERFORM OPTICAL AND PROCESS CORRECTIONS
45
Patent #:
7042242
Issue Dt:
05/09/2006
Application #:
10852902
Filing Dt:
05/25/2004
Publication #:
US20050264314
Pub Dt:
12/01/2005
Title:
BUILT-IN SELF TEST TECHNIQUE FOR PROGRAMMABLE IMPEDANCE DRIVERS FOR RAPIDCHIP AND ASIC DRIVERS
46
Patent #:
7240237
Issue Dt:
07/03/2007
Application #:
10853040
Filing Dt:
05/25/2004
Publication #:
US20050278568
Pub Dt:
12/15/2005
Title:
METHOD AND SYSTEM FOR HIGH BANDWIDTH FAULT TOLERANCE IN A STORAGE SUBSYSTEM
47
Patent #:
6903985
Issue Dt:
06/07/2005
Application #:
10853637
Filing Dt:
05/24/2004
Title:
METHOD AND CIRCUIT FOR MATCHING SENSE AMPLIFIER TRIGGER SIGNAL TIMING TO DATA BIT LINE SEPARATION TIMING IN A SELF-TIMED MEMORY ARRAY
48
Patent #:
7508869
Issue Dt:
03/24/2009
Application #:
10855748
Filing Dt:
05/27/2004
Publication #:
US20050265438
Pub Dt:
12/01/2005
Title:
APPARATUS METHOD AND SYSTEM FOR CHARACTERIZING A COMMUNICATION CHANNEL AND INCREASING DATA THROUGHPUT
49
Patent #:
7065734
Issue Dt:
06/20/2006
Application #:
10859857
Filing Dt:
06/02/2004
Publication #:
US20050273751
Pub Dt:
12/08/2005
Title:
METHOD OF GENERATING MULTIPLE HARDWARE DESCRIPTION LANGUAGE CONFIGURATIONS FOR A PHASE LOCKED LOOP FROM A SINGLE GENETIC MODEL FOR INTEGRATED CIRCUIT DESIGN
50
Patent #:
7412678
Issue Dt:
08/12/2008
Application #:
10859874
Filing Dt:
06/02/2004
Publication #:
US20050273741
Pub Dt:
12/08/2005
Title:
METHOD AND COMPUTER PROGRAM FOR MANAGEMENT OF SYNCHRONOUS AND ASYNCHRONOUS CLOCK DOMAIN CROSSING IN INTEGRATED CIRCUIT DESIGN
51
Patent #:
7478303
Issue Dt:
01/13/2009
Application #:
10862039
Filing Dt:
06/04/2004
Publication #:
US20050273681
Pub Dt:
12/08/2005
Title:
SYSTEM AND METHOD FOR TESTING NODES IN A NETWORK
52
Patent #:
7223616
Issue Dt:
05/29/2007
Application #:
10862049
Filing Dt:
06/04/2004
Publication #:
US20050272174
Pub Dt:
12/08/2005
Title:
TEST STRUCTURES IN UNUSED AREAS OF SEMICONDUCTOR INTEGRATED CIRCUITS AND METHODS FOR DESIGNING THE SAME
53
Patent #:
7471337
Issue Dt:
12/30/2008
Application #:
10863908
Filing Dt:
06/09/2004
Publication #:
US20050276282
Pub Dt:
12/15/2005
Title:
METHOD OF AUDIO-VIDEO SYNCHRONIZATION
54
Patent #:
7436060
Issue Dt:
10/14/2008
Application #:
10865179
Filing Dt:
06/09/2004
Publication #:
US20050275086
Pub Dt:
12/15/2005
Title:
SEMICONDUCTOR PACKAGE AND PROCESS UTILIZING PRE-FORMED MOLD CAP AND HEATSPREADER ASSEMBLY
55
Patent #:
7039556
Issue Dt:
05/02/2006
Application #:
10867003
Filing Dt:
06/14/2004
Publication #:
US20050288896
Pub Dt:
12/29/2005
Title:
SUBSTRATE PROFILE ANALYSIS
56
Patent #:
7013192
Issue Dt:
03/14/2006
Application #:
10867014
Filing Dt:
06/14/2004
Publication #:
US20050278678
Pub Dt:
12/15/2005
Title:
SUBSTRATE CONTACT ANALYSIS
57
Patent #:
7146463
Issue Dt:
12/05/2006
Application #:
10868555
Filing Dt:
06/15/2004
Publication #:
US20050278484
Pub Dt:
12/15/2005
Title:
METHODS AND STRUCTURE FOR OPTIMIZING DISK SPACE UTILIZATION
58
Patent #:
7168052
Issue Dt:
01/23/2007
Application #:
10875128
Filing Dt:
06/23/2004
Publication #:
US20060010092
Pub Dt:
01/12/2006
Title:
YIELD DRIVEN MEMORY PLACEMENT SYSTEM
59
Patent #:
7205803
Issue Dt:
04/17/2007
Application #:
10879438
Filing Dt:
06/29/2004
Publication #:
US20050285653
Pub Dt:
12/29/2005
Title:
HIGH SPEED FULLY SCALEABLE, PROGRAMMABLE AND LINEAR DIGITAL DELAY CIRCUIT
60
Patent #:
7042296
Issue Dt:
05/09/2006
Application #:
10879443
Filing Dt:
06/29/2004
Publication #:
US20060033544
Pub Dt:
02/16/2006
Title:
DIGITAL PROGRAMMABLE DELAY SCHEME TO CONTINUOUSLY CALIBRATE AND TRACK DELAY OVER PROCESS, VOLTAGE AND TEMPERATURE
61
Patent #:
7198546
Issue Dt:
04/03/2007
Application #:
10879629
Filing Dt:
06/29/2004
Publication #:
US20050287927
Pub Dt:
12/29/2005
Title:
METHOD TO MONITOR PAD WEAR IN CMP PROCESSING
62
Patent #:
7181710
Issue Dt:
02/20/2007
Application #:
10879768
Filing Dt:
06/28/2004
Publication #:
US20050289491
Pub Dt:
12/29/2005
Title:
DEVICE FOR ESTIMATING CELL DELAY FROM A TABLE WITH ADDED VOLTAGE SWING
63
Patent #:
8869104
Issue Dt:
10/21/2014
Application #:
10881663
Filing Dt:
06/30/2004
Publication #:
US20060005167
Pub Dt:
01/05/2006
Title:
Object code configuration tool
64
Patent #:
7015096
Issue Dt:
03/21/2006
Application #:
10883137
Filing Dt:
07/01/2004
Title:
BIMETALLIC OXIDE COMPOSITIONS FOR GATE DIELECTRICS
65
Patent #:
7117472
Issue Dt:
10/03/2006
Application #:
10887599
Filing Dt:
07/09/2004
Publication #:
US20060010408
Pub Dt:
01/12/2006
Title:
PLACEMENT OF A CLOCK SIGNAL SUPPLY NETWORK DURING DESIGN OF INTEGRATED CIRCUITS
66
Patent #:
7365015
Issue Dt:
04/29/2008
Application #:
10889901
Filing Dt:
07/13/2004
Publication #:
US20060011994
Pub Dt:
01/19/2006
Title:
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING SI1-XGEX AS SACRIFICIAL MATERIAL
67
Patent #:
7246216
Issue Dt:
07/17/2007
Application #:
10891393
Filing Dt:
07/14/2004
Publication #:
US20060015473
Pub Dt:
01/19/2006
Title:
DYNAMIC PARTITIONING OF STORAGE MEDIA FOR MIXED APPLICATIONS
68
Patent #:
7415691
Issue Dt:
08/19/2008
Application #:
10894781
Filing Dt:
07/20/2004
Publication #:
US20060020927
Pub Dt:
01/26/2006
Title:
METHOD AND SYSTEM FOR OUTPUTTING A SEQUENCE OF COMMANDS AND DATA DESCRIBED BY A FLOWCHART
69
Patent #:
7634748
Issue Dt:
12/15/2009
Application #:
10897655
Filing Dt:
07/22/2004
Publication #:
US20060031798
Pub Dt:
02/09/2006
Title:
SPECIAL ENGINEERING CHANGE ORDER CELLS
70
Patent #:
7660355
Issue Dt:
02/09/2010
Application #:
10898125
Filing Dt:
07/23/2004
Publication #:
US20050147173
Pub Dt:
07/07/2005
Title:
LOW COMPLEXITY TRANSCODING BETWEEN VIDEO STREAMS USING DIFFERENT ENTROPY CODING
71
Patent #:
7216280
Issue Dt:
05/08/2007
Application #:
10900224
Filing Dt:
07/27/2004
Publication #:
US20050235188
Pub Dt:
10/20/2005
Title:
METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
72
Patent #:
7308627
Issue Dt:
12/11/2007
Application #:
10900642
Filing Dt:
07/27/2004
Publication #:
US20050015651
Pub Dt:
01/20/2005
Title:
SELF-TIMED RELIABILITY AND YIELD VEHICLE WITH GATED DATA AND CLOCK
73
Patent #:
7096748
Issue Dt:
08/29/2006
Application #:
10900869
Filing Dt:
07/28/2004
Publication #:
US20060021453
Pub Dt:
02/02/2006
Title:
EMBEDDED STRAIN GAUGE IN PRINTED CIRCUIT BOARDS
74
Patent #:
7254732
Issue Dt:
08/07/2007
Application #:
10901518
Filing Dt:
07/29/2004
Publication #:
US20050005178
Pub Dt:
01/06/2005
Title:
METHOD AND APPARATUS OF AUTOMATIC POWER MANAGEMENT CONTROL FOR SERIAL ATA DEVICE DIRECTLY ATTACHED TO SAS/SATA HOST CONTROLLER
75
Patent #:
7330989
Issue Dt:
02/12/2008
Application #:
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Filing Dt:
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Pub Dt:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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100
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Pub Dt:
02/23/2006
Title:
SYSTEMS AND METHODS FOR TAG INFORMATION VALIDATION IN WIDE PORT SAS CONNECTIONS
Assignor
1
LSI LOGIC CORPORATION
Exec Dt:
04/06/2007
Assignee
1
LSI CORPORATION
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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