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02/24/2005
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03/02/2006
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03/02/2006
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03/02/2006
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03/02/2006
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03/02/2006
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03/02/2006
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03/09/2006
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03/23/2006
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08/19/2008
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03/23/2006
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03/23/2006
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04/06/2006
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03/30/2006
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03/30/2006
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04/06/2006
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02/19/2008
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04/20/2006
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METHOD OF SCREENING ASIC DEFECTS USING INDEPENDENT COMPONENT ANALYSIS OF QUIESCENT CURRENT MEASUREMENTS
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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10970211
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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ARBITRATING ACCESS FOR A PLURALITY OF DATA CHANNEL INPUTS WITH DIFFERENT CHARACTERISTICS
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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10971216
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Filing Dt:
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10/22/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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DRIVING MULTIPLE CONSECUTIVE BITS IN A SERIAL DATA STREAM AT MULTIPLE VOLTAGE LEVELS
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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10971911
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Filing Dt:
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10/23/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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DEBUGGING SIMULATION OF A CIRCUIT CORE USING PATTERN RECORDER, PLAYER & CHECKER
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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10971961
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Filing Dt:
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10/22/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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LOCAL INTERCONNECT MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10972892
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Filing Dt:
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10/25/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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PROGRAMMABLE POWER PERSONALITY CARD
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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10973585
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Filing Dt:
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10/26/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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CORRECTION-CALCULATION ALGORITHM FOR ESTIMATION OF THE SIGNAL TO NOISE RATIO IN HIGH BIT RATE DMT MODULATION
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10973851
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Filing Dt:
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10/25/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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CONTACT RING DESIGN FOR REDUCING BUBBLE AND ELECTROLYTE EFFECTS DURING ELECTROCHEMICAL PLATING IN MANUFACTURING
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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10974103
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD AND APPARATUS FOR IMPROVED INCREASED BIT-DEPTH DISPLAY FROM A TRANSFORM DECODER BY RETAINING ADDITIONAL INVERSE TRANSFORM BITS
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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10975315
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Filing Dt:
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10/28/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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TEST CLOCKING SCHEME
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10975981
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Filing Dt:
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10/27/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD OF OPTIMIZING CRITICAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10976518
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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PROCESS FOR DESIGNING BASE PLATFORMS FOR IC DESIGN TO PERMIT RESOURCE RECOVERY AND FLEXIBLE MACRO PLACEMENT, BASE PLATFORM FOR ICS, AND PROCESS OF CREATING ICS
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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10978755
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Filing Dt:
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11/01/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SERIAL DATA LINK USING DECISION FEEDBACK EQUALIZATION
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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10980373
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Filing Dt:
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11/03/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE (SAS) CONNECTION EMULATION FOR DIRECT ATTACHED SERIAL ADVANCED TECHNOLOGY ATTACHEMNT (SATA)
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10980945
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Filing Dt:
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11/03/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10984286
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Filing Dt:
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11/09/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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HIGH PERFORMANCE DIODE-IMPLANTED VOLTAGE-CONTROLLED POLY RESISTORS FOR MIXED-SIGNAL AND RF APPLICATIONS
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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10985289
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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DELAY LOCKED LOOP HAVING INTERNAL TEST PATH
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10987240
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Filing Dt:
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11/12/2004
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Title:
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METHOD AND APPARATUS FOR DYNAMICALLY BIASING SWITCHING ELEMENTS IN CURRENT-STEERING DAC
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10987356
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR SELF-ADJUSTING INPUT DELAY IN DDR-BASED MEMORY SYSTEMS
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10988081
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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METHOD AND SYSTEM OF GENERIC IMPLEMENTATION OF SHARING TEST PINS WITH I/O CELLS
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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10988122
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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USE OF A KNOWN COMMON-MODE VOLTAGE FOR INPUT OVERVOLTAGE PROTECTION IN PSEUDO-DIFFERENTIAL RECEIVERS
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10988156
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR SUMMING DC VOLTAGES
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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10989698
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Filing Dt:
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11/16/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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SYSTEM AND/OR METHOD FOR IMPLEMENTING EFFICIENT TECHNIQUES FOR TESTING COMMON INFORMATION MODEL PROVIDERS
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10990237
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Filing Dt:
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11/16/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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MEMORY TILING ARCHITECTURE
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10990589
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Filing Dt:
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11/17/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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MEMORY GENERATION AND PLACEMENT
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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10991107
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Filing Dt:
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11/17/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/11/2009
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10991844
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Filing Dt:
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11/18/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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TRANSMIT/RECEIVE DATA PATHS FOR VOICE-OVER-INTERNET (VOIP) COMMUNICATION SYSTEMS
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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10991903
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Filing Dt:
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11/18/2004
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Pub Dt:
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05/18/2006
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Title:
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METHODS AND STRUCTURE FOR BYPASSING MEMORY MANAGEMENT MAPPING AND TRANSLATION FEATURES
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Issue Dt:
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12/04/2007
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10992389
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11/17/2004
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Publication #:
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Pub Dt:
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06/08/2006
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Title:
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METHOD AND TEST APPARATUS FOR TESTING INTEGRATED CIRCUITS USING BOTH VALID AND INVALID TEST DATA
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Patent #:
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Issue Dt:
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12/05/2006
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10992941
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11/19/2004
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Pub Dt:
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05/25/2006
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Title:
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METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
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Issue Dt:
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08/14/2007
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10992999
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11/19/2004
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05/25/2006
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Title:
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MULTIPLE BUFFER INSERTION IN GLOBAL ROUTING
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Issue Dt:
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05/06/2008
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10993283
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11/19/2004
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05/25/2006
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Title:
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METHODS AND STRUCTURES FOR EFFICIENT STORAGE OF TASK FILE INFORMATION IN SERIAL ATA ENVIRONMENTS
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03/13/2007
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10993603
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11/19/2004
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07/14/2005
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Title:
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PROCESS AND APPARATUS FOR GENERATING A STRONG PHASE SHIFT OPTICAL PATTERN FOR USE IN AN OPTICAL DIRECT WRITE LITHOGRAPHY PROCESS
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05/01/2007
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10994114
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11/19/2004
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05/25/2006
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Title:
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METHOD OF ESTIMATING A TOTAL PATH DELAY IN AN INTEGRATED CIRCUIT DESIGN WITH STOCHASTICALLY WEIGHTED CONSERVATISM
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10/07/2008
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10995777
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11/23/2004
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05/25/2006
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Title:
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VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
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11/09/2010
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10997006
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11/24/2004
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05/25/2006
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Title:
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METHOD AND/OR APPARATUS FOR PARSING COMPRESSED VIDEO BITSTREAMS
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Issue Dt:
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01/01/2008
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10999468
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11/30/2004
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06/01/2006
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Title:
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VERIFICATION OF RRAM TILING NETLIST
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Issue Dt:
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10/16/2007
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10999481
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11/30/2004
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Pub Dt:
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06/22/2006
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Title:
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RRAM COMMUNICATION SYSTEM
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05/08/2007
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10999493
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11/30/2004
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07/13/2006
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Title:
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METHOD AND BIST ARCHITECTURE FOR FAST MEMORY TESTING IN PLATFORM-BASED INTEGRATED CIRCUIT
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12/11/2007
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10999720
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11/30/2004
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06/15/2006
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MASTER CONTROLLER ARCHITECTURE
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12/08/2009
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10999825
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11/30/2004
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06/01/2006
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Title:
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PARALLEL VIDEO ENCODER WITH WHOLE PICTURE DEBLOCKING AND/OR WHOLE PICTURE COMPRESSED AS A SINGLE SLICE
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04/03/2007
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11000104
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11/30/2004
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Publication #:
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Pub Dt:
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06/01/2006
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Title:
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RRAM MEMORY TIMING LEARNING TOOL
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Issue Dt:
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02/17/2009
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11002576
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12/01/2004
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06/01/2006
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Title:
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AUTOMATIC RECOGNITION OF GEOMETRIC POINTS IN A TARGET IC DESIGN FOR OPC MASK QUALITY CALCULATION
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